JP2518517B2 - Communication bus monitoring device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication bus monitoring device, and more particularly to a communication bus monitoring system in a communication system in which a plurality of nodes are connected to a common transmission / reception communication bus and communicate with each other via the communication bus. Is.

[0002]

2. Description of the Related Art A conventional communication bus monitoring system of this type is intended to detect a bus abnormality between a plurality of nodes connected to a bus. Data is transmitted / received between one node and another node connected to the bus, and if there is no response to this transmission / reception, a bus abnormality is detected.

[0003]

In such a conventional communication bus monitoring method, when a plurality of nodes are connected to the bus, the bus monitoring is performed by software control. It takes a long time to detect the bus abnormality. Therefore, there is a drawback that the load of software increases.

Further, particularly in the case of the bus connection system having a redundant system, it is necessary to monitor not only the active system but also the standby system, so that there is a drawback that the load of software further increases.

Therefore, the present invention has been made in order to solve the drawbacks of the prior art, and its purpose is to easily perform bus monitoring by hardware and to easily identify a failure point. Another object of the present invention is to provide a communication bus monitoring device adapted to perform the above.

[0006]

SUMMARY OF THE INVENTION In accordance with the present invention, a communication bus including one node and a plurality of other nodes connected to the one node via a communication bus, each node having a unique identification address. Monitoring device, wherein the one node includes means for generating a predetermined pattern signal,
Means for transmitting the pattern signal and the identification address of the other node to the communication bus as a pair, each of the other nodes responding to reception of the pattern signal from the communication bus. Comparing the subsequent identification address with its own identification address and returning the reception pattern signal and the reception address to the communication bus when they match, the one node further includes: And a means for monitoring the communication bus according to the reception state of the pattern signal and the identification address.

[0007]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention. In this example, the main master node 10
1 and sub-slave (cascade) nodes 102 to 104 are interconnected by communication buses 11 and 12. The communication bus comprises a transmission bus 11 and a reception bus 12, and a control bus 13 is further provided.

The master node 101 is a path pattern generating circuit 1 for generating a predetermined specific pattern signal.
And an address generation circuit 2 for generating an identification address assigned to each slave node 102-104.
And a multiplexing circuit 3 that multiplexes the pattern signal and the address and sends them to the transmission bus 11, and a transmission buffer 8 that is turned on / off by a control signal of the control bus 13 to perform signal transmission to the transmission bus 11. are doing.

Further, the master node 101 is the reception bus 1
A separation circuit 6 that separates the received signal from 2 into a pattern signal and an address, a pattern detection circuit 4 that detects this separated reception pattern signal, and a match between the separated reception address and the transmitted transmission address are detected. And an address comparison circuit 5 that operates.

Since the slave nodes 102 to 104 have the same configuration, only the node 102 will be described. When the node 102 detects the pattern signal in the reception signal from the transmission bus 11, the node 102 detects the coincidence between the reception address and its own address in response to the detection, and sends back a response to the master node. It is turned on / off by the control signal of the bus 13 and the reception bus 1
2 and a transmission buffer 9 for returning a response to

In such a configuration, the master node 101
Then, the path pattern generation circuit 1 first generates a fixed pattern signal, and then the address generation circuit 2 generates the address of the slave node 102. Then, in the multiplexing circuit 3, the fixed pattern signal and the address signal are multiplexed so as to be superimposed in one frame, and are transmitted to the transmission bus 11 via the buffer 8.

In the next frame, the fixed pattern signal and the address of the slave node 103 are multiplexed and transmitted. Further, in the next frame, the fixed pattern signal and the address of the slave node 104 are multiplexed, and thereafter, the transmission operation more than the number of slave nodes is sequentially repeated.

In the node 102, when the address detection circuit 7 receives the pattern signal from the transmission bus 11, the address following it is compared with its own address.
When the two addresses match, the address detection circuit 7 returns the received pattern signal and received address as a response to the reception bus 12 via the buffer 9. If the two addresses do not match, no response is returned to the reception bus 12.

In the master node 101, each node 102
The separation circuit 6 receives the response returned from
At, the pattern signal and the address are separated. The separated reception pattern signal is input to the path pattern detection circuit 4, and when the fixed pattern is not detected, it is determined that the bus is abnormal.

In the address comparison circuit 5, the address output from the address generation circuit 2 and the received address from the separation circuit 6 are compared, and if they do not match, it is determined that a bus error has occurred. In this way, when it is determined that the bus is abnormal, the failure location is specified by the address unique to each node at that time.

When the above bus monitoring operation is completed and the bus is in operation, the buffers 8 and 9 are turned off by the control signal of the control bus 13 in order to prohibit the transmission of signals to the buses 11 and 12.

Although the node 101 is the master node and the other nodes 102 to 104 are the slave nodes, this is merely a matter of calling and is not limited.

[0019]

As described above, according to the present invention, the bus abnormality can be detected and the failure location can be specified in a short time only by the hardware control, so that the load of the software can be reduced and the bus line of the redundant configuration can be obtained. However, there is an effect that it is possible to easily monitor both the active system and the standby system without increasing the load on the software.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Path Pattern Generation Circuit 2 Address Generation Circuit 3 Multiplexing Circuit 4 Path Pattern Detection Circuit 5 Address Comparison Circuit 6 Separation Circuit 7 Address Detection Circuit 8, 9 Transmission Buffer 11 Transmission Bus 12 Reception Bus 13 Control Bus 101 Master Nodes 102-104 Slave node

Claims (3)

(57) [Claims] 1. A monitoring device for a communication bus, comprising: a node; and a plurality of other nodes connected to the one node via a communication bus and each having a unique identification address. The node has means for generating a predetermined pattern signal, and means for transmitting the pattern signal and the identification address of the other node to the communication bus as a pair, and each of the other nodes is Responding to the reception of the pattern signal from the communication bus, comparing the subsequent identification address with its own identification address, and returning the reception pattern signal and the reception address to the communication bus when they match. and, said one node further have a, a monitoring unit which forms the monitoring of the communication bus in accordance with the reception state of the pattern signal and the identification address from said communication bus Communication bus monitoring device according to claim Rukoto. 2. The monitoring means receives from the communication bus.
Has a means to detect the pattern signal, the presence or absence of this detection
It is characterized in that the abnormality of the communication bus is determined by
The communication bus monitoring device according to claim 1. 3. The monitoring means identifies from the communication bus.
Having means for comparing the address with the transmitted identification address,
Based on this comparison result, individual failure detection of the node is performed.
The communication bus monitoring device according to claim 1 or 2, characterized in that
Place.