JPH05129851A - Differential amplifier circuit - Google Patents
Differential amplifier circuitInfo
- Publication number
- JPH05129851A JPH05129851A JP28530291A JP28530291A JPH05129851A JP H05129851 A JPH05129851 A JP H05129851A JP 28530291 A JP28530291 A JP 28530291A JP 28530291 A JP28530291 A JP 28530291A JP H05129851 A JPH05129851 A JP H05129851A
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- transistor
- circuit
- amplifier circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Amplifiers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は差動増幅回路に関し、特
にエミッタフォロワ回路を前置きし低ノイズ，高入力イ
ンピーダンス，低消費電力の差動増幅回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit and, more particularly, to a differential amplifier circuit having an emitter follower circuit in front and having low noise, high input impedance and low power consumption.
【０００２】[0002]
【従来の技術】従来の差動増幅回路において、差動増幅
回路の前にエミッタフォロワ回路を付加した回路例が、
図３である。図３において、トランジスタＱ１，Ｑ２
と、それらの共通エミッタに接続された定電流源Ｉ０，
負荷抵抗Ｒ１，Ｒ２とから構成された差動増幅回路と、
それに前置きしたトランジスタＱ３，Ｑ４及び定電流源
Ｉ１，Ｉ２からなるエミッタフォロワ回路がある。2. Description of the Related Art An example of a conventional differential amplifier circuit in which an emitter follower circuit is added before the differential amplifier circuit is
It is FIG. In FIG. 3, transistors Q1 and Q2
And a constant current source I0 connected to their common emitter,
A differential amplifier circuit including load resistors R1 and R2;
There is an emitter follower circuit consisting of transistors Q3 and Q4 and constant current sources I1 and I2 placed in front of it.
【０００３】定電流源Ｉ１，Ｉ２による電流は、エミッ
タフォロワ回路を構成するトランジスタＱ３，Ｑ４のバ
イアス電流となり、定電流源Ｉ０はトランジスタＱ１，
Ｑ２による差動増幅回路のバイアス電流となる。The currents from the constant current sources I1 and I2 serve as bias currents for the transistors Q3 and Q4 which form the emitter follower circuit, and the constant current source I0 serves as the transistor Q1 and Q1.
It becomes the bias current of the differential amplifier circuit by Q2.
【０００４】[0004]
【発明が解決しようとする課題】このような従来の差動
増幅回路では、高入力インピーダンスの特性を得るため
に、差動増幅回路の前にエミッタフォロワ回路を置いて
いるが、この回路で低ノイズの特性が必要であるとき、
エミッタフォロワ回路のバイアス電流を多くする必要が
あるが、そのためにはエミッタフォロワ回路のバイアス
電流を多くしなければならず、そのバイアス電流を多く
すると消費電流も増え、半導体集積回路とする場合には
電力消費が大きく、パッケージの許容損失内に収まらな
くなるという欠点がある。また電池駆動のセットにおい
ては、電池の寿命が短くなるという欠点もある。In such a conventional differential amplifier circuit, an emitter follower circuit is placed in front of the differential amplifier circuit in order to obtain the characteristic of high input impedance. When noise characteristics are needed,
It is necessary to increase the bias current of the emitter follower circuit, but for that purpose, it is necessary to increase the bias current of the emitter follower circuit. If the bias current is increased, current consumption also increases. It has a drawback that it consumes a lot of power and does not fit within the power dissipation of the package. In addition, in a battery-driven set, there is a drawback that the life of the battery is shortened.
【０００５】本発明の目的は、前記欠点を解決し、消費
電力を小さくした差動増幅回路を提供することにある。An object of the present invention is to solve the above-mentioned drawbacks and to provide a differential amplifier circuit with reduced power consumption.
【０００６】[0006]
【課題を解決するための手段】本発明の差動増幅回路の
構成は、差動増幅回路を構成する第１，第２のトランジ
スタとエミッタフォロワ回路を構成する第３，第４のト
ランジスタとを備えた差動増幅回路において、前記第３
のトランジスタのエミッタを前記第１のトランジスタの
ベース及び第１，第３の負荷抵抗に接続し、前記第４の
トランジスタのエミッタを前記第２のトランジスタのベ
ース及び第２，第４の負荷抵抗に接続し、前記第１のト
ランジスタのコレクタに前記第１，第２の負荷抵抗の共
通接続点を接続し、前記第２のトランジスタのコレクタ
に前記第３，第４の負荷抵抗の共通接続点を接続し、前
記第１，第２のトランジスタの共通エミッタに定電流源
を接続したことを特徴とする。The structure of a differential amplifier circuit of the present invention comprises a first and a second transistor forming a differential amplifier circuit and a third and a fourth transistor forming an emitter follower circuit. In the differential amplifier circuit provided, the third
The emitter of the second transistor is connected to the base of the first transistor and the first and third load resistors, and the emitter of the fourth transistor is connected to the base of the second transistor and the second and fourth load resistors. And a common connection point of the first and second load resistors is connected to the collector of the first transistor, and a common connection point of the third and fourth load resistors is connected to the collector of the second transistor. And a constant current source is connected to the common emitter of the first and second transistors.
【０００７】[0007]
【実施例】図１は本発明の一実施例の差動増幅回路を示
す回路図である。1 is a circuit diagram showing a differential amplifier circuit according to an embodiment of the present invention.
【０００８】図１において、本発明の一実施例の差動増
幅回路は、ｎｐｎ型トランジスタＱ１，Ｑ２と、負荷抵
抗Ｒ１，Ｒ２，Ｒ３，Ｒ４，及び定電流源Ｉ０とからな
る差動増幅回路と、それに前置きするエミッタフォロワ
回路を構成するｎｐｎ型ランジスタＱ３，Ｑ４と、電源
Ｖｃｃ及び信号源Ｖｓとを備えている。In FIG. 1, a differential amplifier circuit according to an embodiment of the present invention comprises a npn-type transistor Q1 and Q2, load resistors R1, R2, R3 and R4, and a constant current source I0. And npn-type transistors Q3 and Q4 forming an emitter follower circuit, a power supply Vcc and a signal source Vs.
【０００９】エミッタフォロワ回路のトランジスタＱ
３，Ｑ４のベース間には信号源Ｖｓが印加し、そのトラ
ンジスタＱ３，Ｑ４のエミッタ間に負荷抵抗Ｒ１，Ｒ
２，及び抵抗Ｒ３，Ｒ４をそれぞれ直列に接続する。ま
たトランジスタＱ３，Ｑ４のそれぞれのエミッタは差動
増幅回路を構成するトランジスタＱ１，Ｑ２のそれぞれ
のベースに接続され、そのトランジスタＱ１，Ｑ２のコ
レクタは負荷抵抗Ｒ１，Ｒ２の共通接続点及び抵抗Ｒ
３，Ｒ４の共通接続点にそれぞれ接続され、またトラン
ジスタＱ１，Ｑ２の共通エミッタには定電流源Ｉ０が接
続されている。Transistor Q of the emitter follower circuit
A signal source Vs is applied between the bases of Q3 and Q4, and load resistors R1 and R are applied between the emitters of the transistors Q3 and Q4.
2, and resistors R3 and R4 are connected in series. Further, the emitters of the transistors Q3 and Q4 are connected to the bases of the transistors Q1 and Q2 that form the differential amplifier circuit, and the collectors of the transistors Q1 and Q2 are the common connection point of the load resistors R1 and R2 and the resistor R.
3, R4 are connected to a common connection point of addition to the common emitter of the transistors Q1, Q2 are connected to a constant current source I0.
【００１０】図２は本発明の他の実施例の差動増幅回路
を示す回路図である。FIG. 2 is a circuit diagram showing a differential amplifier circuit according to another embodiment of the present invention.
【００１１】図２において、本実施例は、図１の回路を
ｐｎｐ型のトランジスタＱ１，Ｑ２，Ｑ３，Ｑ４で構成
したもので、これらトランジスタの変更にともない、接
続関係も変更されている。動作は図１と同様である。In FIG. 2, the present embodiment is the one in which the circuit of FIG. 1 is composed of pnp type transistors Q1, Q2, Q3 and Q4, and the connection relationship is changed with the change of these transistors. The operation is similar to that of FIG.
【００１２】[0012]
【発明の効果】以上、本発明の実施例によれば、エミッ
タフォロワ回路のバイアス電流を次の差動増幅回路のバ
イアス電流として使用する回路構成にしたので、低ノイ
ズ特性を必要とする差動増幅回路でエミッタフォロワ回
路のバイアス電流を多くした時、従来回路での回路電流
Ｉｃｃは、Ｉｃｃ＝Ｉ０＋Ｉ１＋Ｉ２（Ｉ０：差動増幅
回路のバイアス電流、Ｉ１，Ｉ２：エミッタフォロワ回
路のバイアス電流）となるが、本発明の差動増幅回路で
はエミッタフォロワ回路のバイアス電流を差動増幅回路
のバイアス電流とするため回路電流Ｉｃｃは、Ｉｃｃ＝
Ｉ０となり、従来回路より回路電流を少なくできるため
消費電力が小さくなるという効果がある。As described above, according to the embodiment of the present invention, since the bias current of the emitter follower circuit is used as the bias current of the next differential amplifier circuit, the differential circuit requiring the low noise characteristic is used. When the bias current of the emitter follower circuit is increased in the amplifier circuit, the circuit current Icc in the conventional circuit becomes Icc = I0 + I1 + I2 (I0: bias current of the differential amplifier circuit, I1, I2: bias current of the emitter follower circuit). However, in the differential amplifier circuit of the present invention, since the bias current of the emitter follower circuit is used as the bias current of the differential amplifier circuit, the circuit current Icc is Icc =
Since it becomes I0, and the circuit current can be reduced as compared with the conventional circuit, there is an effect that the power consumption becomes small.
【００１３】ここでトランジスタのノイズＶＮは次式の
ようになる。The noise VN of the transistor is given by the following equation.
【００１４】 [0014]
【００１５】この式において、ノイズＶＮを１ｍＶ以下
にしようとすると、バイアス電流Ｉｃを５ｍＡ以上流さ
なくてはならない。これを従来回路の回路電流の式と本
実施例の式にあてはめると、従来回路では、Ｉｃｃ＝Ｉ
０＋Ｉ１＋Ｉ２＝１０ｍＡ＋５ｍＡ＋５ｍＡ＝２０ｍＡ
となるが、本実施例の回路では、Ｉｃｃ＝Ｉ０＝１０ｍ
Ａとなり、従来回路の回路電流の半分でよいことにな
る。In this equation, if the noise VN is to be set to 1 mV or less, the bias current Ic must be 5 mA or more. When this is applied to the formula of the circuit current of the conventional circuit and the formula of the present embodiment, Icc = I in the conventional circuit.
0 + I1 + I2 = 10mA + 5mA + 5mA = 20mA
However, in the circuit of this embodiment, Icc = I0 = 10 m
A, which is half the circuit current of the conventional circuit.
【００１６】また、入力インピーダンスも従来回路と同
様に高入力インピーダンスとなる。また、図１のｎｐｎ
型トランジスタを、図２の様に、ｐｎｐ型トランジスタ
にしても同様の効果がある。Also, the input impedance becomes a high input impedance as in the conventional circuit. In addition, npn in FIG.
If the type transistor is a pnp type transistor as shown in FIG. 2, the same effect can be obtained.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の一実施例の差動増幅回路を示す回路図
である。FIG. 1 is a circuit diagram showing a differential amplifier circuit according to an embodiment of the present invention.
【図２】本発明の他の実施例の回路図である。FIG. 2 is a circuit diagram of another embodiment of the present invention.
【図３】従来の差動増幅回路を示す回路図である。FIG. 3 is a circuit diagram showing a conventional differential amplifier circuit.
Ｑ１，Ｑ２ 差動増幅回路を構成するトランジスタ Ｑ３，Ｑ４ エミッタフォロワ回路を構成するトラン
ジスタ Ｒ１〜Ｒ４ 負荷抵抗 Ｉ０〜Ｉ２ バイアス電流用定電流源 Ｖｓ 入力信号源 Ｖｃｃ 電源Q1, Q2 Transistors constituting differential amplifier circuit Q3, Q4 Transistors constituting emitter follower circuit R1 to R4 Load resistors I0 to I2 Constant current source for bias current Vs Input signal source Vcc power source
Claims (2)
ランジスタとエミッタフォロワ回路を構成する第３，第
４のトランジスタとを備えた差動増幅回路において、前
記第３のトランジスタのエミッタを前記第１のトランジ
スタのベース及び第１，第３の負荷抵抗に接続し、前記
第４のトランジスタのエミッタを前記第２のトランジス
タのベース及び第２，第４の負荷抵抗に接続し、前記第
１のトランジスタのコレクタに前記第１，第２の負荷抵
抗の共通接続点を接続し、前記第２のトランジスタのコ
レクタに前記第３，第４の負荷抵抗の共通接続点を接続
し、前記第１，第２のトランジスタの共通エミッタに定
電流源を接続したことを特徴とする差動増幅回路。1. A differential amplifier circuit comprising first and second transistors forming a differential amplifier circuit and third and fourth transistors forming an emitter follower circuit, wherein the emitter of the third transistor is an emitter. Is connected to the base of the first transistor and the first and third load resistors, and the emitter of the fourth transistor is connected to the base of the second transistor and the second and fourth load resistors, The common connection point of the first and second load resistors is connected to the collector of the first transistor, and the common connection point of the third and fourth load resistors is connected to the collector of the second transistor, A differential amplifier circuit characterized in that a constant current source is connected to a common emitter of the first and second transistors.
ｐｎ型またはｐｎｐ型である請求項１記載の差動増幅回
路。2. The first to fourth transistors are all n
The differential amplifier circuit according to claim 1, which is a pn type or a pnp type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3285302A JP3036925B2 (en) | 1991-10-31 | 1991-10-31 | Differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3285302A JP3036925B2 (en) | 1991-10-31 | 1991-10-31 | Differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05129851A true JPH05129851A (en) | 1993-05-25 |
| JP3036925B2 JP3036925B2 (en) | 2000-04-24 |
Family
ID=17689770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3285302A Expired - Lifetime JP3036925B2 (en) | 1991-10-31 | 1991-10-31 | Differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036925B2 (en) |
-
1991
- 1991-10-31 JP JP3285302A patent/JP3036925B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3036925B2 (en) | 2000-04-24 |
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