JPH04227105A - Current-voltage conversion circuit - Google Patents

Abstract

PURPOSE:To widen a dynamic range, to improve an S/N, and to attain low power consumption by connecting between the output of each complementary buffer circuit with an impedance circuit, and outputting a current on the impedance circuit. CONSTITUTION:An input signal S1 is outputted to one terminal of a resistor 22 via a buffer circuit formed with TRs22-37. Meanwhile, a negative side input signal S2 is inputted to the other terminal of the resistor 22 via a buffet circuit formed with TRs42-55. Thereby, the signal can be inputted to the other terminal of the resistor 22 via the buffer circuit formed with the TRs22-37, and the buffer circuit formed with the TRs42-59. In such a way, both circuits form the buffer circuits which amplify the positive side and negative side input signals S1, S2. The current 11 proportional to the potential difference of the signals S1, S2 flows on the resistor 22, which enables the signals S1, S2 to be voltage- current converted. A TR62 forms a differential amplifier circuit with TRs64-72, and the input current of the TR62 is outputted via a TR72.

Description

[Detailed description of the invention]

0001

[Table of Contents] The present invention will be explained in the following order. Industrial applications Conventional technology (Figure 2) Problems to be solved by the invention (Figure 2) Means to solve problems (Figure 1) Effect (Figure 1) Example (1) First embodiment (Figure 1) (2) Other examples Effect of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current-voltage conversion circuit, and can be applied to, for example, a differential amplifier circuit integrated into an integrated circuit.

0003

2. Description of the Related Art Conventionally, in a differential amplifier circuit integrated into an integrated circuit, input signals are processed by converting them into voltage and current, for example, using the method proposed in Japanese Unexamined Patent Publication No. 59-2410. .

That is, as shown in FIG. 2, in the voltage-current conversion circuit 1, the emitters of transistors 2 and 3 are connected by a resistor 4, and the emitters of the transistors 2 and 3 are connected via current sources 5 and 6. and connect it to the negative power supply VEE. Furthermore, the voltage-current conversion circuit 1 supplies positive side and negative side input signals S1 and S2 to the bases of transistors 2 and 3, respectively.

Here, the current values I1 of current sources 5 and 6 are set equal, and the collectors of transistors 2 and 3 are connected to current mirror circuits of transistors 7 and 8, respectively. In this way, assuming that the potential difference between input signals S1 and S2 is ΔV [V], and the resistance value of resistor 4 is R, the current I flowing through resistor 4 can be calculated using the following formula:

It can be expressed as [Equation 1]. Thereby, by receiving the collector output of the transistor 3 with, for example, a current mirror circuit, a current output expressed by equation (1) can be obtained, and the current output can be processed by a desired processing circuit.

[0006]

By the way, when securing a large dynamic range in this type of current-voltage conversion circuit 1, the current I1 of the current sources 5 and 6 must be adjusted so that the transistors 2 and 3 operate reliably. It is necessary to set it to a large value commensurate with the dynamic range.

However, when the current value I1 is set to a large value, the power consumption increases and the SN of the output current increases.
There is a problem that the ratio deteriorates.

Further, when it is desired to increase the gain, it is necessary to increase the resistance value R of the resistor 4, but there is also the problem that increasing the resistance value R deteriorates the SN ratio. The present invention has been made in consideration of the above points, and aims to propose a voltage-current conversion circuit that can widen the dynamic range, has a good signal-to-noise ratio, and has low power consumption.

[0009]

[Means for Solving the Problems] In order to solve the problems, in the present invention, the first buffer circuits 22 to 37, R1 to R7, which input the first input signal S1, and the second input signal S2, second buffer circuits 42 to 59 for input;
R9 to R20 and first and second buffer circuits 22 to 3
7. Impedance circuit R22 that connects the outputs of R1 to R7, 42 to 59, and R9 to R20, and a current output circuit 57 that outputs the current I1 flowing through the impedance circuit R22.
, 59, 60, 64, R18, R20, R24, R25
and first buffer circuits 22 to 37, R1 to R7.
are a PNP type first transistor 30 which receives the first input signal S1 at its base, an NPN type second transistor 31 which receives the first input signal S1 at its base, and an emitter output of the first transistor 30. NP received based on
A PNP type in which the base receives the emitter outputs of the N-type third transistor 35 and the second transistor 31, connects the emitter to the emitter of the third transistor 35, and outputs the emitter output to one end of the impedance circuit R22. The second buffer circuits 42 to 59 and R9 to R20 each include a PNP type fifth transistor 50 which receives the second input signal S2 as a base;
A sixth NPN transistor 51 that receives the second input signal S2 at its base, a seventh NPN transistor 55 that receives the emitter output of the fifth transistor 50 at its base, and an emitter output of the sixth transistor 51. is received at the base, the emitter is connected to the emitter of the seventh transistor 55, and the emitter output is connected to the impedance circuit R2.
PNP type eighth transistor 58 outputs to the other end of 2
and has.

0010

[Operation] First and second buffer circuits 22-37, R1-R7 and 42-59, R9-R20 configured similarly.
If connected by the impedance circuit R22, the first and second buffer circuits 22 to 37, R1 to R7 and 42
59 and R9 to R20 can be supplied with positive side and negative side input signals S1 and S2 to form a buffer circuit that operates in a complementary manner. As a result, impedance circuit R22
The current I1 flowing through the buffer changes in proportion to the signal level difference between the first and second input signals S1 and S2, and the input signals S1 and S2 can be converted into voltage and current. Circuits 22-37, R1-R7 and 42-
59, R9 to R20 can be operated with a small operating current.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment In FIG. 1, 20 indicates a differential amplifier circuit as a whole;
A positive side input signal S1 is applied to the transistor 22. The transistor 22 forms a differential pair with the transistor 23, has its emitter connected to the transistor 24, and has its collector connected to the positive power supply VCC.

Here, the transistor 24 receives a reference voltage VR1 at its base, forms a constant current source together with a resistor R1,
This drives transistors 22 and 23. The transistor 23 has a collector connected to a constant current source formed by transistors 26, 27, 28 and resistors R2, R3, and R4, and is supplied with a predetermined current determined by a reference voltage VR1. As a result, the transistors 22 and 23 as a whole constitute a buffer circuit, and the positive side input signal S
After correcting the offset voltage of transistor 1, the following transistor 3
Output to 0 and 31.

Transistor 30 is formed of a PNP transistor, and has its collector connected to the positive power supply VCC via transistor 32 and resistor R5. Furthermore, the emitter of the transistor 30 is connected to the constant current source of the transistor 33 and the resistor R6, and the emitter output is outputted to the transistor 35.

The transistor 31 is formed of an NPN transistor, and has its collector connected to the negative power supply VEE, and its emitter connected to the positive power supply VCC via the transistor 36 and resistor R7. At this time, the transistor 32
and 36 are arranged to form a current mirror circuit, so that equal collector currents flow through the transistors 30 and 31.

Transistor 35 is an NPN transistor, and receives the emitter output of transistor 30 and connects its collector to negative power supply VEE. The transistor 37 is a PNP transistor that inputs the emitter output of the transistor 31, and its collector is connected to the positive power supply VCC.
The emitter of the transistor 35 is connected to the emitter of the transistor 35. As a result, the emitter potential of the transistor 37 changes in proportion to the signal level of the positive input signal S1.

At this time, in the transistor 37, the emitter output is fed back to the transistor 23, thereby reducing the offset voltage of the emitter output with respect to the positive input signal S1. As a result, transistors 22 to 37, resistors R1 to
R7 as a whole constitutes a first buffer circuit that amplifies the positive input signal S1.

The transistor 42 receives the negative input signal S2 at its base, forms a differential pair with the transistor 43, has its emitter connected to the transistor 44, and has its collector connected to the positive power supply VCC. Here, transistor 44 receives reference voltage VR1 at its base, forms a constant current source together with resistor R9, and drives transistors 42 and 43.

The transistor 43 is a transistor 46,
A constant current source formed by resistors R10, R11, and R12 is connected to the collector, and a predetermined current determined by the reference voltage VR1 is supplied. As a result, the transistor 42
and 43 constitute a buffer circuit having the same configuration as the transistors 22 and 23, and receive the negative side input signal S2.
After correcting the offset voltage of the following transistor 50
and output to 51.

Transistor 50 is formed of a PNP transistor, and has its collector connected to the positive power supply VCC via transistor 52 and resistor R14. Furthermore, the emitter of the transistor 50 is connected to the constant current source of the transistor 53 and the resistor R15, and the emitter output is connected to the constant current source of the transistor 53 and the resistor R15.
Output to 5.

The transistor 51 is formed of an NPN transistor, and has its collector connected to the negative power supply VEE, and its emitter connected to the positive power supply VCC via the transistor 56 and resistor R16. At this time, transistor 5
2 and 56 are arranged to form a current mirror circuit, so that equal collector currents flow through transistors 50 and 51.

Transistor 55 is an NPN transistor, and has its collector connected to negative power supply VEE via transistor 57 and resistor R18. The transistor 58 is a PNP transistor that receives the emitter output of the transistor 51, has a collector connected to the positive power supply VCC via a transistor 59 and a resistor R20, and has an emitter connected to the emitter of the transistor 55. As a result, the emitter potential of the transistor 58 changes in proportion to the signal level of the negative side input signal S2.

At this time, the emitter output of the transistor 58 is fed back to the transistor 43, thereby reducing the offset voltage of the emitter output with respect to the negative side input signal S2. As a result, transistors 52 to 59, R9 to R20
In this case, the second buffer circuit as a whole amplifies the negative side input signal S2. At this time, while the first buffer circuit amplifies the positive input signal S1, the second buffer circuit amplifies the negative input signal S2. A complementary buffer circuit is constructed in which the emitter output changes accordingly.

Resistor R22 connects transistors 37 and 58
A current I1 proportional to the voltage between the emitters of the transistors 37 and 58 flows through the resistor R22. That is, by configuring a complementary buffer circuit with the first and second buffer circuits, the voltage between the emitters of transistors 37 and 58 is
It is proportional to the potential difference ΔV between the positive side and negative side input signals S1 and S2.

Therefore, if the emitters are connected by a resistor R22, the resistance value of the resistor R22 is set as R1, and the current I1 of the resistor R22 is expressed by the following equation.

It can be expressed by the following relational expression. As a result, the input signal S1
and S2 can be converted into voltage and current.

At this time, a complementary buffer circuit was formed using the transistors 22 to 37 and transistors 42 to 59, and the outputs of the buffer circuit were connected by the resistor R22 for voltage-current conversion, so that in the buffer circuit, Current that flows steadily (hereinafter referred to as idling current)
can be made smaller. Therefore, the power consumption of the differential amplifier circuit 20 can be reduced accordingly, and deterioration of the S/N ratio can be effectively avoided.

Furthermore, by converting voltage to current using the complementary buffer circuit in this way, the idling current can be set regardless of the signal levels of the input signals S1 and S2, and a correspondingly large dynamic range can be obtained. . Further, the resistance value of the resistor R22 can be set to a small value, and the voltage-current conversion gain can be increased accordingly.

The transistor 57 is a transistor 60,
A current mirror circuit is formed together with the resistor R24, and the emitter current I2 of the transistor 55 is folded back and output to the transistor 62. The transistor 59 forms a current mirror circuit together with the transistor 64 and the resistor R25,
The emitter current I3 of the transistor 58 is turned back and output to the transistor 62.

As a result, the emitter current I2 of the transistor 57 is expressed by the following equation using the current I1 of the resistor R22 and the emitter current I3 of the transistor 59.

It can be expressed by the following relational expression, where the current I2 is canceled on the input side of the transistor 62, and thus only the voltage-current conversion result can be input to the transistor 62.

The transistor 62 forms a differential pair with the transistor 64, and has its emitter connected to a constant current source formed by the transistor 66 and the resistor R26. At this time, the collector of the transistor 64 is directly connected to the positive power supply VCC, whereas the transistor 62 is connected to the positive power supply VCC through the transistor 68 and the resistor R27.
Connect the collector to CC.

The transistor 68 is a transistor 69,
70 and the resistors R27, R28, and R29 form a current mirror circuit, and supply a predetermined current determined by the reference voltage VR1 to the transistor 62.

Transistor 72 is connected to the positive power supply VCC, receives the collector output of transistor 62, and has its emitter connected to a constant current source of transistor 73 and resistor R30. As a result, the transistors 62 to 72 form a high gain differential amplifier circuit as a whole.

Furthermore, the transistor 72 feeds back the emitter output to the transistor 62 via the resistor R32, so that the transistors 62 to 72 as a whole are connected to the transistor 62.
The input current is converted into current and voltage and output.

By performing voltage-to-current conversion using the complementary buffer circuit, it is possible to obtain a differential amplifier circuit with a large dynamic range, low power consumption, and a good S/N ratio.

In the above configuration, the positive input signal S1 is outputted to one end of the resistor R22 via a buffer circuit formed of transistors 22-37. On the other hand, the negative input signal S2 is input to the other end of the resistor 22 via a buffer circuit formed by transistors 42-59. Thereby, the buffer circuit formed by the transistors 22-37 and the buffer circuit formed by the transistors 42-59 form a complementary buffer circuit that amplifies the positive side and negative side input signals S1 and S2.

As a result, in the resistor R22, (
2) A current I1 expressed by the formula can flow, and the input signals S1, S
2 can be converted into voltage and current, and at this time, by using a complementary buffer circuit, it is possible to effectively avoid deterioration of the S/N ratio with low power consumption. You can also get a large dynamic cleanse.

The current I1 of the resistor R22 is input to the transistor 62 together with the current I3 of the transistor 59 via the transistor 57 and the transistor 60. At this time, the current I3 of the transistor 59 is input to the transistor 62 via a separate transistor 64, so that the current I1 of the resistor R22 is input to the transistor 64.
can only be entered.

The transistor 62 is connected to the transistors 64 to 64.
72 to form a differential amplifier circuit, and the transistor 6
The input current of 2 is output through transistor 72. At this time, the output signal of the transistor 72 is fed back to the transistor 62 via the resistor R32, so that the input current of the transistor 62 can be converted into a voltage and output.

According to the above configuration, by inputting the positive side and negative side input signals to the complementary buffer circuit, connecting the outputs of the complementary buffer circuit with a resistor, and outputting the current flowing through the resistor. , it is possible to set the idling current of the complementary buffer circuit independently of the input signal, thereby reducing the idling current while maintaining the dynamic range, and obtaining a voltage-current conversion circuit with low power consumption and high S/N ratio. can.

(2) Other Embodiments Although the above-mentioned embodiments have described the case where the voltage-current conversion circuit according to the present invention is applied to a differential amplifier circuit, the present invention is not limited to this, and can be applied to various signal It can be widely applied to processing circuits.

Further, in the above embodiment, a case was described in which the buffer circuits are connected by the resistor R22, but the present invention is not limited to this. For example, in addition to the resistor R22, various time constant circuits for frequency characteristic compensation may be connected. You may also do so.

[0042]

As described above, according to the present invention, by connecting the outputs of complementary buffer circuits with an impedance circuit and outputting the current flowing through the impedance circuit, the complementary buffer circuit can be operated independently of the input signal. The idling current can be reduced, and the dynamic range is widened accordingly.
A voltage-current conversion circuit with low power consumption and high SN ratio can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a differential amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional voltage-current conversion circuit.

[Explanation of symbols]

1, 20...Voltage-current conversion circuit, 2, 3, 7, 8, 22
~72...transistor, 4, R1-R32...resistance.

Claims (1)

[Claims] 1. An impedance connecting a first buffer circuit to which a first input signal is input, a second buffer circuit to which a second input signal is input, and the outputs of the first and second buffer circuits. circuit, and a current output circuit that outputs a current flowing through the impedance circuit, and the first buffer circuit receives a PN signal based on the first input signal.
a P-type first transistor, a NPN-type second transistor whose base receives the first input signal, and an NP-type transistor whose base receives the emitter output of the first transistor.
A PNP type transistor including an N-type third transistor, which receives the emitter output of the second transistor at its base, connects the emitter to the emitter of the third transistor, and outputs the emitter output to one end of the impedance circuit. Fourth
The second buffer circuit has a transistor of
a PNP-type fifth transistor that receives the second input signal at its base; an NPN-type sixth transistor that receives the second input signal at its base; and a base that receives the emitter output of the fifth transistor. A PNP type seventh transistor of NPN type, which receives the emitter output of the sixth transistor at its base, connects the emitter to the emitter of the seventh transistor, and outputs the emitter output to the other end of the impedance circuit. A voltage-current conversion circuit comprising an eighth transistor.