JP2503887B2 - Variable gain circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

An object of the present invention is to realize a variable gain circuit which is stable and has a wide band regardless of changes in gain.

[0002]

2. Description of the Related Art In high speed communication such as optical communication, a gain variable circuit having a wide band and a wide variable gain range is required. Therefore, variable gain amplifiers are connected in multiple stages to realize a wide variable gain. In that case, there is a problem in stabilizing the output DC level of each gain variable amplifier when the gain is variable.

FIG. 3 shows a conventional example of a variable gain circuit for reducing fluctuations in DC level (reference: KAZUO).
YAMAGUTI et al. "400 Mbit / s
Optical Generator Inte
"Grated Circuit", pp.186, Fi
g. 4, IEEE Journal on Selec
ted Areas in Communicatio
ns, vol. sac-4, No. 1, January
1986).

This circuit is composed of a pair of transistors 1 and 2, a current source 14 and load resistors 10 and 11, a basic differential amplifier circuit, current shunting transistors 3, 5, 6 and 8 and a DC level stabilizing circuit. Transistor 9 and current fluctuation detection resistor 1
3 and a DC level stabilizing circuit.

The gain control is performed by shunting the signal currents flowing through the transistor pairs 1 and 2 by the transistor pairs 3, 5 and 6, 8 whose shunting ratio changes according to the ratio of the control voltages Vgc1 and Vgc2. The smaller the current ratio flowing through the resistor, the smaller the gain. In the present invention, it is possible to provide a gain variable circuit in which the current flowing in the transistors 5 and 6 is converted into a voltage by the resistor 13 and the DC level fluctuation of the output Vout is reduced via the transistor 9 to enable a wide gain change. To aim.

[0006]

In the above-mentioned prior art, the direct current flowing through the differential transistor pair 1 and 2 is I, the current shunt ratio is α, 1-α (0 ≦ α ≦ 1), and the resistor 13 is used.
Is RB, the value of the resistor 10 is RL, the base-emitter voltage of the transistor 9 and the emitter current are Vbe,
If Ie, the DC level of the output Vout is Vout = Vcc-2 (1-α) RB-Vbe (Ie) -αIRL (1).

Further, Ie becomes Ie = 2α (2). When RB = RL / 2, the equation (1) becomes Vout = Vcc-IRL-Vbe (Ie) (3), and only the emitter current dependency of Vbe of the transistor 9 remains. However, since Ie changes from (2) to 0 to 2 I, the fluctuation of Vbe cannot be ignored. For example, when the gain variable width is 20 dB, the fluctuation width becomes about 300 mV and is directly connected to the amplifier circuit of the next stage. In this case, instability of operation due to bias fluctuation cannot be avoided.

An object of the present invention is to reduce the above-mentioned DC level fluctuation.

[0009]

[Means for Solving the Problems] Means for solving the above problems exist in the following two items.

[1] In a gain variable circuit for controlling the gain of a signal amplification circuit used in an electronic circuit,
Amplifier composed of the differential transistor pair composed of the transistor (1) and the second transistor (2), two load resistors (10, 11) and a current source (14), and gain control It is composed of a circuit (A).

The base of the first transistor (1) is connected to the signal input terminal Vin, and the base of the second transistor (2) is connected to the signal input terminal [Vin]. One end of the current source (14) is connected to both emitters of the differential transistor pair, and the other end is connected to the low voltage side power supply terminal Vee.

The gain control circuit (A) is composed of seven transistors from the third to the ninth and one resistor. The emitter of the third transistor (3), the emitter of the fourth transistor (4) and the emitter of the fifth transistor (5) are connected to the collector of the first transistor (1) of the differential transistor pair. .

The emitter of the sixth transistor (6), the emitter of the seventh transistor (7) and the emitter of the eighth transistor (8) are the second of the differential transistor pair.
Connected to the collector of the transistor (2). The base of the third transistor (3) and the base of the eighth transistor (8) are connected to one gain control terminal Vgc1.

The base of the fourth transistor (4) and the fifth
The base of the transistor (5), the base of the sixth transistor (6), and the base of the seventh transistor (7) are connected to the other gain control terminal Vgc2.

The collector of the third transistor (3) and one terminal of the first load resistor (10) are connected to the output terminal Vout.
The collector of the eighth transistor (8) and one terminal of the second load resistor (11) are connected to the output inverting terminal [Vout]. The other terminals of the first load resistor (10) and the second load resistor (11), the collector of the fourth transistor (4) and the collector of the seventh transistor (7) are connected to the ninth transistor (9). ) Is connected to the emitter.

The collector of the fifth transistor (5), the collector of the sixth transistor (6) and the third resistor (1
3) One terminal is connected to the base of the ninth transistor (9), and the other terminal of the third resistor (13) and the collector of the ninth transistor (9) are high-voltage side power supply terminals. Variable gain circuit characterized by being connected to Vcc.

[2] A tenth transistor (15) and an eleventh transistor (16) are added, and the first transistor
The emitter of the 0 transistor (15) is the collector of the first transistor (1), and the base is the gain control terminal V
The collector of the eleventh transistor (16) is connected to the collector of the second transistor (2), the base of the eleventh transistor (16) is connected to the other gain control terminal Vgc2, and the collector of the eleventh transistor (16) is connected to the high voltage side. The variable gain circuit according to the above [1], which is connected to each of the voltage side power supply terminals Vcc.

[0018]

According to the first aspect of the present invention, the first current shunt transistor connected to the load resistor and the second current shunt transistor connected to the current fluctuation detecting resistor in the current shunt transistor pair of the conventional circuit are provided. A third shunt transistor that always shunts at the same ratio regardless of the transistor and the gain control voltage is provided, and this third shunt current is added to the first shunt current to form the emitter current of the DC level stabilizing transistor. .

In this circuit, in order to reduce the gain, the gain control voltage is adjusted to decrease the first shunt current flowing through the load resistor, but the third shunt current is increased. Therefore, the emitter current of the DC level stabilizing transistor is reduced. The change is small, and as a result, the fluctuation in the base-emitter potential is small. Conversely, in order to increase the gain, if the first shunt is increased, the third shunt is reduced, and the fluctuation of the emitter current is also reduced.

Here, in FIG. 1, the direct current collector currents flowing through the differential pair transistors 1 and 2 are I respectively, and the shunt ratios of the transistor 3 and (transistor 4 + transistor 5) and the transistor 8 and (transistor 6 + transistor 7) are shown. , Α: 1-α (0 ≤ α ≤ 1), and the shunt ratio of the transistor 5 and the transistor 4 and the transistor 6 and the transistor 7 is β: 1-β (0 ≤ β ≤ 1), the output terminal Vout DC level is R
B, the base-emitter voltage of the transistor 9 is Vbe,
When the emitter current is Ie and the resistor 10 is RL, Vout = Vcc-2β (1-α) IRB-Vbe (Ie) -αIRL (4).

When RB = RL / (2β), the equation (3) becomes Vout = Vcc-IRL-Vbe (Ie) (5), and the fluctuation of Vout is only the fluctuation of Vbe.

Here, Ie is represented by Ie = 2 (1-β (1-α)) (6).

According to the equation (6), the smaller β is, the smaller the variation of Ie due to α becomes. For example, if β = 0.1, the variation of Ie is reduced to 1/10 as compared with the equation (2). Fluctuations due to gain changes in Vout are reduced.

In addition to the first invention, a second invention of the present invention is provided with a fourth shunt transistor, which keeps the emitter current of the DC level stabilizing transistor constant regardless of the variable gain, and provides an output DC It suppresses level fluctuations to zero.

In the circuit of FIG. 2, transistors 15 and 16 are added to the circuit of FIG. In this case, transistors 3, 15, transistors 4, 5, transistors 6, 7,
When the shunt ratio is the same for each pair of transistors 8 and 16, the DC level at the output terminal Vout is Vout = Vcc-2 (1-α) I / 2RB-Vbe (Ie) -αI / 2 It becomes RL (7).

When RB = RL / 2, the equation (6) becomes Vout = Vcc-I / 2RL-Vbe (Ie) (8).

At this time, Ie is Ie = 2 (α / 2 + (1−α) / 2I) = I (9), and Ie is also constant regardless of the diversion ratio α, so that Ve
The fluctuation due to the gain change of out disappears.

[0028]

FIG. 1 is a circuit diagram showing an embodiment of the first invention. A differential transistor pair composed of a first transistor 1 and a second transistor 2 and two load resistors 1
A differential amplifier composed of 0, 11 and a current source 14;
It is composed of a gain control circuit A. First transistor 1
Is connected to the signal input terminal Vin, and the base of the second transistor 2 is connected to the signal input terminal [Vin].

One end of the current source 14 is connected to both emitters of the differential transistor pair, and the other end is connected to the low voltage side power supply terminal Vee.

The gain control circuit A includes seven circuits from the third to the ninth.
It consists of one transistor and one resistor. The emitter of the third transistor 3, the emitter of the fourth transistor 4, and the emitter of the fifth transistor 5 are connected to the collector of the first transistor 1 of the differential transistor pair. The emitter of the sixth transistor 6, the emitter of the seventh transistor 7 and the emitter of the eighth transistor 8 are connected to the collector of the second transistor 2 of the differential transistor pair.

Further, the base of the third transistor 3 and the base of the eighth transistor 8 are connected to one gain control terminal Vgc1. The base of the fourth transistor 4, the base of the fifth transistor 5, and the sixth transistor 6
And the base of the seventh transistor 7 are connected to the other gain control terminal Vgc2. The collector of the third transistor 3 and one terminal of the first load resistor 10 are connected to the output terminal Vout, and the collector of the eighth transistor 8 and one terminal of the second load resistor 11 are output inverting terminals. Connected to [Vout]. In addition, the first load resistor 10
The other terminals of the second load resistor 11, the collector of the fourth transistor 4, and the collector of the seventh transistor 7 are connected to the emitter of the ninth transistor 9.

The collector of the fifth transistor 5, the collector of the sixth transistor 6 and one terminal of the third resistor 13 are connected to the base of the ninth transistor 9 and the other end of the third resistor 13 is connected. Terminal and the ninth transistor 9
Is a current shunting transistor pair 3, 4, 5 for adjusting the gain of each collector of the differential pair transistors 1 and 2 having signal input terminals Vin and [Vin] connected to the high-voltage side power supply terminal Vcc. , 6, 7 and 8, and the shunt ratio is changed by the gain control terminals Vgc1 and Vgc2. Further, load resistors 10 and 11 are connected to the transistors 3 and 8, respectively, and outputs are taken out here.

The output DC level stabilizing circuit is composed of a current fluctuation detecting resistor 13 and a transistor 9 connected to the transistors 5 and 6. In this circuit, the size ratio of the transistor 4 and the transistor 5, and the transistor 7 and the transistor 6 is set to 9: 1, and β in the expression 6 is set to 0.1.
As a result of trial manufacture of the circuit, when the gain was varied in the conventional circuit, the DC level variation was 500 mV, but the circuit of the present invention could be suppressed to the variation of 90 mV.

As a result, the variable gain circuit of the present invention is connected in two stages, and an input / output buffer is added to this to form a variable gain amplifier. As a result, despite the variable gain width of 30 dB,
A stable variable gain amplifier was realized.

FIG. 2 is a circuit diagram showing an embodiment of the second invention.

A tenth transistor 15 and an eleventh transistor 16 are added together. The emitter of the tenth transistor 15 is the collector of the first transistor 1, the base is the gain control terminal Vgc1, and the collector is high. The eleventh transistor 16 has an emitter connected to the collector of the second transistor 2 and connected to the voltage-side power supply terminal Vcc.
The base is connected to the other gain control terminal Vgc2, and the collector is connected to the high voltage side power supply terminal Vcc.

This circuit corresponds to the transistor 1 in the embodiment of FIG.
5, 16 are added, and transistors 3, 4, 5, 6, 7,
The sizes of 8, 15 and 16 are made the same, and the transistor 3,
The flow dividing ratios of the sets of 15, the transistors 4, 5, the transistors 6, 7, and the transistors 16, 8 are the same.

As a result of trial manufacture of the circuit, the output DC level fluctuation can be suppressed to zero irrespective of the gain change. As a result, the variable gain circuit of the present invention is connected in four stages to form a variable gain amplifier. A stable and wide-band variable gain amplifier having a variable gain width of 45 dB was realized.

In the above circuit, NP is used as the transistor.
Although the N bipolar transistor is used, the transistor may be a PNP bipolar transistor or FET.

[0040]

According to the present invention, by adding the transistors 4 and 7 to the conventional variable gain circuit, the variation of the emitter current of the DC bias stabilizing transistor 9 during the variable gain can be reduced. As a result, compared to conventional circuits,
The smaller the fluctuation of the emitter current, the smaller the fluctuation of the DC bias of the output terminal.

That is, it is possible to reduce the DC level fluctuation when the gain is changed in the variable gain circuit, and to realize stable coupling with the amplifier at the next stage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional variable gain circuit.

[Explanation of symbols]

 Vin signal input terminal [Vin] signal input terminal Vout output terminal [Vout] output terminal Vgc1 gain control terminal Vgc2 gain control terminal Vcc high voltage side power supply terminal Vee low voltage side power supply terminal A gain control circuit 1, 2, 3, 4, 5,6,7,8,9,15,16 Transistor 10,11,13 Resistor 14 Current source

Claims (2)

(57) [Claims] 1. A variable gain circuit for controlling the gain of a signal amplifier circuit used in an electronic circuit, comprising: a differential transistor pair composed of a first transistor (1) and a second transistor (2); It is composed of a differential amplifier composed of two load resistors (10, 11) and a current source (14) and a gain control circuit (A), and the base of the first transistor (1) is a signal input terminal Vin.
The base of the second transistor (2) is connected to the signal input terminal [Vin], one end of the current source (14) is connected to both emitters of the differential transistor pair, and the other end is low. Voltage side power supply terminal V
The gain control circuit (A) is connected to ee and is composed of seven transistors from the third to the ninth and one resistor. The gain control circuit (A) includes the emitter of the third transistor (3) and the fourth transistor (4). ) And the emitter of the fifth transistor (5) are connected to the collector of the first transistor (1) of the differential transistor pair, and the emitter of the sixth transistor (6) and the seventh transistor (7) ( The emitter of 7) and the emitter of the eighth transistor (8) are connected to the collector of the second transistor (2) of the differential transistor pair, the base of the third transistor (3) and the eighth transistor (8). The base of (8) is connected to one of the gain control terminals Vgc1, and the base of the fourth transistor (4), the base of the fifth transistor (5) and the sixth transistor (6) are connected. And the base of the seventh transistor (7) are connected to the other gain control terminal Vgc2, and the collector of the third transistor (3) and one terminal of the first load resistor (10) are output terminals. Vout, the collector of the eighth transistor (8) and one terminal of the second load resistor (11) are connected to the output inverting terminal [Vout], and the first load resistor (10) and the second load resistor (11) The other terminal of each load resistor (11), the collector of the fourth transistor (4) and the collector of the seventh transistor (7) are connected to the emitter of the ninth transistor (9), The collector of the transistor (5), the collector of the sixth transistor (6) and one terminal of the third resistor (13) are connected to the base of the ninth transistor (9),
A variable gain circuit characterized in that the other terminal of the third resistor (13) and the collector of the ninth transistor (9) are connected to the high voltage side power supply terminal Vcc. 2. A tenth transistor (15) and an eleventh transistor (15)
The transistor (16) is added to the collector of the first transistor (1), the base of the tenth transistor (15) is the gain control terminal Vgc1, and the collector is the high voltage side power supply terminal Vcc. The emitter of the eleventh transistor (16) is connected to the collector of the second transistor (2), the base is connected to the other gain control terminal Vgc2, and the collector is connected to the high voltage side power supply terminal Vcc. The variable gain circuit according to claim 1, wherein: