JPH05129604A - Field effect transistor - Google Patents

Abstract

PURPOSE:To make temperature distribution uniform and to improve reliability by providing an active layer region which is divided and formed with at least one band-like nonconductive region between parallel to a unit field effect transistor which is provided in parallel. CONSTITUTION:A plurality of gate electrodes 102 are provided in parallel on an element region of a field effect transistor. A plurality of source electrodes 103 and a plurality of drain electrodes 104 are arranged in parallel between the gate electrodes 102 alternately parallel with the gate electrode 102. An active layer region is divided and formed in 101a and 101b with a nonconductive region 109 between which is positioned at a central part of a gate electrode by selective ion implantation and mesa separation. Since drain current does not flow in the nonconductive region 109 which divides the active layer, heat is not generated in the center of a gate electric field. Thereby, burn-out and electromigration can be restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor which is highly reliable and suitable for high output operation.

[0002]

2. Description of the Related Art In general, a field effect transistor having a plurality of unit field effect transistors arranged in parallel employs a structure in which gate, source, and drain electrodes are arranged in a comb shape.

A conventional field effect transistor will be described below with reference to FIG. 3 shows the gate, the source,
3A and 3B show a field effect transistor in which each electrode of a drain is arranged in a comb shape, FIG. 3A is a plan view showing a main part of the structure in a see-through manner, and FIG. .. In the figure, for example, a plurality of gate electrodes 302 arranged at predetermined intervals are arranged on an active layer 301 (hatched portion in the figure) having n-type conductivity selectively formed by an ion implantation method, and Source electrodes 303 and drain electrodes 304 are alternately arranged between the plurality of gate electrodes 302. Each gate electrode 302 is connected to the gate extraction electrode 305 by the bus wiring 308, and similarly, the drain electrode 304 and the source electrode 30 are connected.
3 are collected and connected to the extraction electrodes 306 and 307, respectively.

[0004]

Generally, in a field effect transistor, in a state in which a voltage is applied to the drain and gate electrodes and a drain current is applied, the relationship between the heat generated by the drain current and the heat dissipated from the front and back surfaces of the transistor. Determines the heat distribution on the transistor surface. FIG. 4 shows a plan view in which one unit of the field effect transistor is taken out, and also shows the temperature distribution in the direction parallel to the gate electrode. As is clear from this figure, the temperature near the center of the gate electrode 202 becomes high. When such a temperature distribution occurs, burnout or electromigration (Electro Mi) is higher in the high temperature portion, that is, in the central portion of the gate electrode 202 in FIG.
(gration) is likely to be accelerated and the electrical characteristics have a distribution corresponding to this temperature distribution, so that burnout due to non-uniform operation is likely to occur.

It is an object of the present invention to provide a field-effect transistor with improved reliability by improving the above-mentioned conventional drawbacks and suppressing the heat generation in the central portion in the gate electrode direction to make the temperature distribution uniform.

[0006]

A field effect transistor according to the present invention is a field effect transistor in which unit field effect transistors composed of gate, source and drain electrodes are arranged in parallel. It is characterized in that it is provided with active layer regions parallel to the direction and divided and formed with at least one strip-shaped non-conductive region interposed therebetween.

[0007]

In the field-effect transistor according to the present invention, the active layer region is divided into at least two regions with at least one strip-shaped non-conductive region parallel to the juxtaposed direction of the unit field-effect transistors. No heat is generated because no drain current flows in the non-conductive regions that separate the active layer. Therefore, by placing the non-conductive region in the part of the field-effect transistor of the conventional structure where the temperature becomes high during operation, heat generation in this part is eliminated, the peak temperature of the temperature distribution is lowered, and the distribution is made flat. You can Therefore, it is possible to suppress burnout and electromigration due to thermal runaway locally generated in the high temperature portion, and also to suppress burnout due to uneven operation due to the distribution of electric characteristics corresponding to the temperature distribution. it can.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A field effect transistor according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view (FIG. 1 (a)) and an AA in FIG. 1 (a) showing a perspective view of a field effect transistor according to an embodiment of the present invention for explaining a planar structure of an electrode and an active layer portion. The cross-sectional view (FIG.1 (b)) along a line is shown. As shown in the figure, a plurality of gate electrodes 102 are arranged in parallel on the element region of the field effect transistor, and a plurality of source electrodes 103 and drain electrodes 104 are arranged between the gate electrodes 102 in parallel with the gate electrodes 102. They are arranged in parallel alternately. The gate electrode 105 and the drain electrode 104 are provided on the gate electrode.
Drain electrode 106 and source electrode 103
A source extraction electrode 107 is connected to each of these.

The active layer region (the hatched portion in FIG. 1A) is
By the selective ion implantation or the mesa separation, the non-conductive region 109 located in the central portion of the gate electrode is divided and formed in 101a and 101b.

In the illustrated field effect transistor,
The drain current does not flow through the non-conductive region 109 at the center of the gate electrode. For this reason, heat generation in the central portion of the gate electrode is eliminated, and in the conventional temperature distribution having a peak in the central portion of the gate electrode as shown in FIG. 2, heat generation from the central portion is suppressed, so that the peak temperature decreases and the temperature distribution Becomes flat.

In this way, burnout and electromigration due to the presence of the high temperature portion can be suppressed, and burnout due to nonuniform operation corresponding to the temperature distribution can be suppressed.

Although the active layer is divided into two in the above embodiment, it may be divided into three or more depending on the temperature distribution during operation, and the division position is not limited to that in the above embodiment. Needless to say.

[0014]

As described above, according to the present invention, a temperature distribution having a peak temperature in the central portion of the gate electrode, which is difficult to avoid in the conventional field effect transistor, can be flattened and the peak can be obtained. The temperature can be lowered. Therefore, burnout and electromigration due to temperature rise during operation can be suppressed, and burnout due to nonuniform operation corresponding to temperature distribution can be suppressed. Therefore, according to the present invention, a highly reliable field effect transistor can be provided.

[Brief description of drawings]

1A is a plan view showing a field effect transistor according to an embodiment of the present invention as seen through, FIG. 1B is a cross-sectional view taken along line AA of FIG.

FIG. 2 is a diagram showing a temperature distribution in a direction parallel to a gate electrode of a field effect transistor of the present invention,

3A is a plan view showing a conventional field effect transistor as seen through, FIG. 3B is a sectional view taken along line AA of FIG.

FIG. 4 is a diagram showing a temperature distribution in a direction parallel to a gate electrode of a conventional field effect transistor,

[Explanation of symbols]

 101a, 101b Active layer 102, 202, 302 Gate electrode 103, 203, 303 Source electrode 104, 204, 304 Drain electrode 105, 305 Gate extraction electrode 106, 306 Drain extraction electrode 107, 307 Source extraction electrode 108 Bus wiring 109 Non-conductive region

Claims (1)

[Claims] 1. A field-effect transistor comprising unit field-effect transistors composed of gate, source and drain electrodes arranged in parallel, wherein at least one strip-shaped non-conductive region parallel to a direction in which the unit field-effect transistors are arranged side by side. A field effect transistor characterized by comprising an active layer region divided and formed so as to sandwich it.