CN102651365A

CN102651365A - Integrated circuit structure

Info

Publication number: CN102651365A
Application number: CN201110045949XA
Authority: CN
Inventors: 周祥明; 陈新翰
Original assignee: Elite Semiconductor Memory Technology Inc
Current assignee: Elite Semiconductor Memory Technology Inc
Priority date: 2011-02-25
Filing date: 2011-02-25
Publication date: 2012-08-29
Anticipated expiration: 2031-02-25
Also published as: CN102651365B

Abstract

The invention discloses an integrated circuit structure, which is mainly provided with a grid electrode area, a source electrode area and a drain electrode area on a substrate; the source electrode area is provided with a plurality of bulgy first finger-shaped structures; the drain electrode area is provided with a plurality of bulgy second finger-shaped structures; and the bulgy first finger-shaped structures and the bulgy second finger-shaped structures are arranged in a staggering way; and a protection ring is further arranged below the bulgy first finger-shaped structures and the bulgy second finger-shaped structures. The integrated circuit structure provided by the invention has the efficacies of high temperature resistance and electrostatic discharge protection.

Description

Integrated circuit structure

Technical field

The present invention relates to a kind of integrated circuit, refer to a kind of integrated circuit structure especially with high temperature resistant and electrostatic discharge (ESD) protection.

Background technology

In recent years, semiconductor integrated circuit generally is used in the association area of various electronic products, like PC, hand-hold electronic device and flat-panel screens or the like.For high-power IC apparatus, higher electric current will cause high-power IC apparatus to produce higher temperature, and temperature is higher, then will cause high-power IC apparatus to produce bigger electric current.Under the situation of this vicious circle, high-power IC apparatus after using a period of time, usually can take place impaired (burning out) situation and can't normal operation.Therefore, a kind of finger-like source electrode and finger-like drain electrode that is used for reducing current density promptly is developed.

Consult Fig. 1; Announce No. 7166867 field-effect transistor (FET) layout for United States Patent (USP); As shown in the drawing: this field-effect transistor 10 has source electrode 12 and drain electrode 13; This source electrode 12 all presents finger 121,131 with the adjacent portions of drain electrode 13, and each staggered finger 121, space between 131 then disposes grid 11.When these field-effect transistor 10 conductings; Because the relation of finger 121,131; Will make electronics no longer concentrate on circulation in certain specific contact hole (passage between the first metal layer (metal one) and second metal level (metal two)); But comparatively average each contact hole of flowing through that disperses reduces heating effect of current, and is overheated and burn to avoid this field-effect transistor 10.

Can avoid this field-effect transistor 10 overheated and burn though United States Patent (USP) is announced No. 7166867 finger 121,131,, but not have any description for the protection of static discharge.In general, for the protection (ESD protection) of static discharge configuration protection ring (guard ring) around integrated circuit normally, announce shown in the 20040052019th like U.S. Patent application.Yet the design of configuration protection ring (guard ring) will increase the area of its layout around integrated circuit, therefore be difficult to can be rated as practicality.

Therefore, how under the prerequisite that does not increase layout area, let integrated circuit have the effect of high temperature resistant and electrostatic discharge (ESD) protection simultaneously, real in having the thinking direction of meaning.

Summary of the invention

By being that one of main purpose of the present invention promptly is to provide a kind of integrated circuit structure, can reach effect person high temperature resistant and electrostatic discharge (ESD) protection.

For reaching above-mentioned purpose, technology of the present invention realizes as follows:

A kind of integrated circuit structure comprises: substrate; Gate regions is disposed at the top of this substrate; Source area is disposed at the top of this substrate; And the drain region, be disposed at the top of this substrate; Wherein, This source area has first finger of a plurality of protrusions; This drain region has second finger of a plurality of protrusions; The arrangement of the second finger interleaved shape of first finger of these a plurality of protrusions and these a plurality of protrusions, and second finger of first finger of these a plurality of protrusions and these a plurality of protrusions below also disposes guard ring.

Description of drawings

Fig. 1 announces No. 7166867 integrated circuit layout for United States Patent (USP).

Fig. 2 is the layout of integrated circuit structure of the present invention.

Fig. 3 is another layout of integrated circuit structure of the present invention.

Description of reference numerals

10: substrate 11: grid

12: source electrode 121: finger

13: drain electrode 131: finger

20: substrate 21: grid

22: 221: the first fingers of source electrode

23: 231: the second fingers drain

24: guard ring 30: substrate

31: grid 32: source electrode

Finger 33 in 321: the first: drain electrode

Finger 34 in 331: the second: guard ring

Embodiment

Fig. 2 is the layout of integrated circuit structure of the present invention; As shown in the drawing: this integrated circuit structure is the high power field effect transistor structure; Mainly be configuration gate regions 21, source area 22 and drain region 23 in substrate 20, and this gate regions 21 is disposed at the top of this source area 22 and this drain region 23.Wherein, This source area 22 has first finger 221 of a plurality of protrusions; This drain region 23 has second finger 231 of a plurality of protrusions; First finger 221 of these a plurality of protrusions and the arrangement of second finger, the 231 interleaved shapes of this a plurality of protrusions, and first finger 221 of these a plurality of protrusions and second finger, 231 belows of these a plurality of protrusions also dispose guard ring 24.When this high power field-effect transistor conducting; Each contact hole of flowing through that first finger 221 of these a plurality of protrusions and second finger 231 of these a plurality of protrusions will make electronics comparatively on average disperse; Relative is more high temperature resistant, can avoid this high power field-effect transistor overheated and burn.In addition, first finger 221 that is disposed at these a plurality of protrusions and this guard ring 24 of second finger, 231 belows of these a plurality of protrusions not only can not increase the layout area of this high power field-effect transistor, more can reach the effect of electrostatic discharge (ESD) protection.

Fig. 3 is another layout of integrated circuit structure of the present invention, and as shown in the drawing: this integrated circuit structure is the high power field effect transistor structure, mainly is configuration gate regions 31, source area 32 and drain region 33 in substrate 30.Wherein, This source area 32 has first finger 321 of a plurality of protrusions; This drain region 33 has second finger 331 of a plurality of protrusions; First finger 321 of these a plurality of protrusions and the arrangement of second finger, the 331 interleaved shapes of this a plurality of protrusions, and first finger 321 of these a plurality of protrusions and second finger, 331 belows of these a plurality of protrusions also dispose guard ring 34.In addition, this gate regions 31 is disposed in the space between second finger 331 of first finger 321 and these a plurality of protrusions of these a plurality of protrusions, and presents the state of meander-like.When this high power field-effect transistor conducting; Each contact hole of flowing through that first finger 321 of these a plurality of protrusions and second finger 331 of these a plurality of protrusions will make electronics comparatively on average disperse; Relative is more high temperature resistant, can avoid this high power field-effect transistor overheated and burn.In addition, first finger 321 that is disposed at these a plurality of protrusions and this guard ring 34 of second finger, 331 belows of these a plurality of protrusions not only can not increase the layout area of this high power field-effect transistor, more can reach the effect of electrostatic discharge (ESD) protection.

Though the present invention discloses as above with preferred embodiment; Right its is not that any persons skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.

Claims

1. integrated circuit structure comprises:

Substrate;

Gate regions is disposed at the top of this substrate;

Source area is disposed at the top of this substrate; And

The drain region is disposed at the top of this substrate;

Wherein, This source area has first finger of a plurality of protrusions; This drain region has second finger of a plurality of protrusions; The arrangement of the second finger interleaved shape of first finger of these a plurality of protrusions and these a plurality of protrusions, and second finger of first finger of these a plurality of protrusions and these a plurality of protrusions below also disposes guard ring.

2. according to the integrated circuit structure of claim 1, wherein, this gate regions is disposed at the top of this source area and this drain region.

3. according to the integrated circuit structure of claim 1, wherein, this gate regions is disposed in the space between second finger of first finger and these a plurality of protrusions of these a plurality of protrusions.