JPH05129559A - Structure and manufacture of bi-cmos dram cell - Google Patents

Abstract

PURPOSE: To perform integration into a small area by forming a current- detecting type cell structure using three elements in a solid structure. CONSTITUTION: A cell structure is in BiCMOS form, consisting of an n-channel MOSFET 17 and an n-channel JFET 18 and a PNP bipolar transistor 19. The n-channel MOSFET 17 functions as a MOS capacitor that is constituted of polysilicon gate oxide and a P region, while it is kept constantly turned off. The n-channel JFET 18 reads information stored in the capacitor of the MOSFET 17. The PNP bipolar transistor 19 is used to write data into a cell and selectively charges or discharges the MOS capacitor. In the case of a reading-mode operation, the bipolar transistor 19 is cut off. Since the cell is a current-detection system, it can be reduced to a substantially small area, thus increasing the reading and writing speeds.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method and a structure of a bi-simus DRAM cell (BI-CMOS DRAM CELL). In particular, in order to manufacture a high-density DRAM cell with a three-dimensional structure, the conventional 1T1C (One Transistor One C
apacitor) charge-sensing method, instead of current-sensing method Bisimos DR using three elements of three-dimensional structure
The present invention relates to the structure and manufacturing method of an AM cell. A DRAM is an element having a large storage capacity and is used in almost all semiconductor products such as computers. 16Mb DRAM is currently in the prototype stage, and 64Mb and 256Mb D
RAM will continue to be developed. From the structural point of view, the development direction of memory devices to date is a planar type (Planar type) up to 1 Mb.
For Mb and above, a stacked type and a trench type have been developed. A conventional DRAM cell, as shown in FIG.
Information is accumulated by accumulating electric charge in the capacitor 24 through the transistor 23 as a 1T1C cell including one transistor 23 and one capacitor 24. The operating principle of this 1T1C DRAM cell is that a signal of information travels back and forth between the bit line 21 and the capacitor 24 through the transfer gate transistor 23 which is turned on / off by the voltage of the word line 22. Information to be supplied is electric charge as the capacitor 2
4 and has a value represented by a charge function. In order to increase the degree of integration and increase the capacity of DRAM having such a cell structure, the area of the cell is reduced, and therefore, a method of forming a capacitor on a plane is adopted. A stacked capacitor (Stac) using multi-layered polysilicon.
It has changed to form a ked capacitor). A new manufacturing technique and a cell structure are required to develop a large-capacity storage element. In terms of manufacturing technology, there are technical problems such as a photographic transfer technology for high integration and a thin film forming technology. In addition, in the current cell structure, it is possible to reduce soft errors and to reduce substrate spacing (Substrat).
e distance) and signal reducti
Since "on" etc. are not sufficient, it is necessary to focus on the reduction of scaling as a three-dimensional approach in terms of structure. In addition, the conventional 4 Mb DRAM has a trench technology process and a polysilicon 2 layer-polycide (Polycid).
e) -Metal 4-layer interconnection (In
ter connection) technology and the process of CMOS are used, the process is complicated and the number of masks is increased to 14 or more. In a DRAM of 16 Mb or more, the process becomes more difficult because the method uses a mixture of stubs and trenches. In order to achieve higher integration and higher speed, it is necessary to develop a cell with a new three-dimensional structure, a processing technology of 0.5 μm or less, and a bisimos process technology. The present invention overcomes the above-mentioned problems and, in order to manufacture a high-density DRAM having a three-dimensional structure, uses three devices having a three-dimensional structure instead of the conventional 1T1C charge sensing method. It is an object to provide a new sensing type cell structure. In order to solve the above-mentioned problems, the present invention adopts a DRAM cell structure of bipolar and C
A three-dimensionally structured bisimos DRAM composed of 3T (3 transistors) coexisting with MOS is used. 16 Mb DRA of the present invention
The equivalent circuit of M is shown in FIG. DRAM of the present invention is n ^- channel MOSFET17 and n ^- channel JFET1
8 and a PNP bipolar transistor 19 having a bisimos type cell structure, and this cell operates in a current sensing method. In the cell of the present invention, an n ^- channel MOS is used.
The FET 17 is always turned off (TurnOff), and the polysilicon gate oxide (Poly Silicon Gate Oxide) is used.
Oxide) and a P region to act as a MOS capacitor. The n ^- channel JFET 18 is MOSFET
It is an element for reading the information stored in the capacitor of T17. The voltage stored in the capacitor of MOSFET 17 changes the thickness of the JFET channel,
Adjust the drain current of. The PNP bipolar transistor 19 is used to write data to the cell and selectively charges or discharges the MOS capacitor. In the reading mode operation, the bipolar transistor 19 is cut off. The elements constituting the bisimos DRAM cell of the present invention and their functions will be described in more detail below. 1) n ^- Channel MOSFET: The N ⁺ region forms the source and drain, and the P region forms the floating electrical substrate. When the MOSFET is turned off, it changes state with a MOS capacitor composed of a polysilicon gate oxide and a P region. 2) n ^- channel JFET; the N ⁺ region forms the source and drain, the n ^- well forms the channel, and the P region forms the gate. The JFET is used to read the stored data, and the voltage stored in the MOS capacitor adjusts the thickness of the JFET channel to adjust the drain current of the JFET. 3) PNP bipolar transistor; P
The region forms the emitter, the n-well is the base,
The P-type substrate becomes the collector. PNP bipolar transistors are used to write data to cells, which also selectively charge or discharge MOS capacitors.
For reading mode operation, the bipolar transistor is cut off. The operating principle of the cell of the present invention will be described. When writing data, -0.
A voltage of 6 [V] is applied to turn on the PNP bipolar transistor 19 to turn on the write bit line 27.
Is 0 [V] in the "0" state, and -in the "1" state.
Information is stored in the gate capacitor of MOSFET 17 by applying a voltage of 1.2 [V]. Next, when reading data, 0 [V] is applied to the word line 26 and -1.
By applying a voltage of 2 [V], JFE will be activated in the "0" state.
When T18 is "OFF" and is "1", JFE
Since T18 is turned on, the read bit line 28
The electric current starts to flow. The layout of the bisimos DRAM of the present invention is shown in FIG. When the cell size is 6F ² and the 0.5 μm design rule is used, that is, when the cell size is F = 0.5 μm, the cell size is 1.5 μm ² and can be used for a 64 Mb DRAM. FIGS. 4 and 5 are a sectional view taken along the line AA 'and a sectional view taken along the line BB' of the bisimos cell structure of the present invention shown in FIG. The PNP bipolar transistor is composed of a P type substrate (collector) 1, an N diffusion region (base) 2 and a P diffusion region (emitter) 3, and is an n-channel JFE.
T is an N ⁺ diffusion region (drain) 6 and an N diffusion region (n ^- chann)
el) 2, a word line (Source) 7, a P-type substrate 1 and a P diffusion region 3 as a gate. The MOSFET is an N ⁺ diffusion region (drain)
6, word line 7, N ⁺ poly (Gate) 5, P diffusion region (Substrate) 3, and gate oxide film (Gate oxide) 4
It consists of At this time, the P diffusion region 3, the gate oxide film 4 and the N ⁺ poly 5 function as a capacitor. A method of manufacturing the above-described bisimos DRAM cell of the present invention will be described below. 6 to 14 are explanatory views sequentially showing the manufacturing method of the present invention. First, as shown in FIG. 6, after performing a general CMOS process, field oxidation is performed to form an element isolation oxide film 8 to define an active region. Next, as shown in FIG. 7, after depositing a silicon nitride film (Nitride) 10 and a silicon oxide film (Oxide) 9, a trench region is defined as a trench mask, and then the silicon nitride film 10 and the silicon oxide film are formed. 9 and silicon substrate 1 are etched to form trench 11. Then, as shown in FIG. 8, phosphorus (Phosph
orus) is doped (1E 16 cm ⁻³ ) to form the N region 2. After that, as shown in FIG. 9, after doping with boron to form the P ⁺ region 3,
As shown in FIG. 10, a gate oxide film 4 is grown, N ⁺ poly 5 is deposited, and then a gate region is defined. Next, as shown in FIG. 11, n ⁺ source /
After forming the drain 6, as shown in FIG.
The D oxide film 12 is deposited. Next, as shown in FIG. 13, the contact 13 is opened using a contact mask, and as shown in FIG. 14, after metal is vapor-deposited, a metal line 7 is set to complete a bisimos cell. The manufacturing method of the present invention will be described in more detail. As shown in FIG. 6, after forming an initial silicon oxide film to be the element isolation oxide film 8 to a thickness of about 3000 angstroms, the initial silicon oxide film is etched using an N-well mask to form a well implant. (Ph
After removing the photoresist and well drive-in, the silicon oxide film is removed, the silicon nitride film is deposited to about 1000 angstroms, and the silicon nitride film is etched using an active mask. After hard baking, field implant is performed using a field Vt mask (cell area masking) to remove the photoresist, and after field oxidation (about 600 Å), the silicon nitride film is removed. An element isolation oxide film 8 is formed. Next, as shown in FIG. 7, the silicon nitride film 10 and the silicon oxide film 9 are deposited to about 1000 angstrom and about 1 μm, respectively, and the oxide film, the nitride film and the oxide film are removed using a trench mask. Etching is performed in order, the photoresist is removed, and then the silicon substrate 1 is etched (2 μm) to form a trench 11. Next, as shown in FIG. 8, phosphorus is doped to form an N − region 2, and boron is doped (1E 18 cm ⁻³ ) to form a P ⁺ region 3 as shown in FIG.
Then, the oxide film 9, the nitride film 10 and the oxide film (5
(About 100 Å) is sequentially removed, and as shown in FIG. 10, gate oxidation (200 Å) is performed to form a gate oxide film 4, and a channel implant and N ⁺ poly 5 are deposited. After performing the steps in sequence, poly is etched using a poly mask to remove the photoresist. After that, as shown in FIG. 11, using an n ⁺ S (source) / D (drain) mask, n ⁺ -S / D is obtained.
Implant (1E 20 cm ^-3 ) was performed to remove the photoresist, and n ⁺ -S / D annealing (Annealin
After g), a P ⁺ -S / D implant (1E 20 cm ^-3 ) is performed using a P ⁺ -S / D mask to remove the photoresist, and then CVD oxidation is performed as shown in FIG. The film 12 is vapor-deposited (1 μm), and the CVD oxide film 12 is etched using the contact mask to form the contact 13, as shown in FIG. 13, and then the photoresist is removed. Next, as shown in FIG. 14, metal (A
l) Deposition (6000 angstroms), metal is etched using a metal mask to remove the photoresist, alloy (Alloy) and passivation are sequentially performed, and then a pad mask is used. After opening the pad, the photoresistor is removed to complete the bisimos cell of the present invention. The structure of the bisimos cell of the present invention has a scaling-invariant read signal, which is a function of the stored voltage and not of the charge, so that it is compared to the case of the 1T1C cell. It can be integrated in a smaller area, and the cell not only makes the sense circuit easier to design the sense amplifier, but also allows the surrounding circuit to be integrated at a smaller pitch. Also, unlike the conventional 1T1C type cell, since it is a current sensing type, it can be reduced to a considerably small area (6F ² ), which has the effect of accelerating reading and writing. In addition, the structure has less leakage of current, is not only excellent in resistance to soft error, and has the effect that the working process is simplified because it is exactly the same as the standard SIMOS process. Especially important is the new 64 Mb DRAM
It is possible to produce a 64 Mb DRAM even in the present process of about 0.5 / 0.6 μm without the process development.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an equivalent circuit diagram of a conventional DRAM cell. FIG. 2 is an equivalent circuit diagram of the Bisimos DRAM cell of the present invention. FIG. 3 is a layout diagram of a DRAM cell of the present invention. FIG. 4 is a cross-sectional view of a DRAM cell of the present invention. FIG. 5 is a cross-sectional view of a DRAM cell of the present invention. FIG. 6 is an explanatory view of the manufacturing process of the DRAM cell of the present invention. FIG. 7 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. FIG. 8 is an explanatory view of the manufacturing process of the DRAM cell of the present invention. FIG. 9 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. FIG. 10 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. FIG. 11 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. FIG. 12 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. FIG. 13 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. FIG. 14 is an explanatory diagram of the manufacturing process of the DRAM cell of the present invention. [Description of Reference Signs] 1 P-type substrate 2 N ^- diffusion region 3 P ⁺ diffusion region 4 gate oxide film 5 N ⁺ poly 6 N ⁺ diffusion region 7 word line 8 element isolation oxide film 9 silicon oxide film 10 silicon nitride film 11 trench 12 CVD oxide film 13 Contact 17 MOSFET 18 JFET 19 PNP bipolar transistor 21 bit line 22 word line 23 transistor 24 capacitor 25 plate 26 write bit line 27 read bit line

Claims (1)

1. A PNP bipolar transistor for writing data, comprising a P-type substrate, an N ⁻ diffusion region, and a P ⁺ diffusion region, an N ⁺ diffusion region, an N ⁻ diffusion region, a word line, and P. Mold substrate, gate for data storage composed of P ⁺ diffusion region, n ^- channel JF for reading stored data
A current-sensing bisimoth DRAM cell comprising an ET, an N ⁺ diffusion region, a word line, an N ⁺ poly, a P ⁺ diffusion region and a MOSFET acting as a capacitor. 2. A step of forming a silicon oxide film for element isolation on a silicon substrate, a step of sequentially depositing a silicon nitride film and a silicon oxide film, and then forming a trench, an N ⁻ diffusion region, P in the trench. ^{A step} of sequentially forming a ⁺ diffusion region and a gate oxide film, and then forming a gate region made of n ⁺ polysilicon, an N ⁺ diffusion region as a drain after forming the gate region, and a CVD silicon oxide film, and then contacting And a method of manufacturing a bisimos DRAM cell, the method comprising the steps of forming a metal line. 4.