JPS62133753A - Dynamic memory cell - Google Patents

Abstract

PURPOSE:To contrive to microscopically form a memory cell by a method wherein the charge of a capacitor formed on the semiconductor layer is amplified by the bipolar transistor and is read out. CONSTITUTION:A P-type impurity region 16 is formed on the surface layer of an N-type well 15 and moreover, an N<+> impurity region 17 is formed in part of the region 16. An electrode 18 is formed on a top of the region 16 interposing an insulating film 6 between them. An electrode 18 is also used as a word wire WLR for readout. Both electrodes of a cell capacitor are formed of the electrode 18 and a bipolar transistor T3 is formed of the regions 17 and 16 and the well 15. Since the transistor T3 can be manufactured with good controllability, no trouble occurs with the manufacture. Moreover, since there is no need to separate the well 15 into every memory cell, the memory cell can be microscopically formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor memory devices, and particularly to dynamic memory cells.

[Technical background of the invention]

FIG. 4 shows a 4M structure of a conventional general planar type dynamic memory cell. Memory cells are formed on a semiconductor substrate 1 and are separated from each other by an insulating film 2 for element isolation. That is, impurity regions 3 and 4 are provided on the semiconductor substrate 1, and these impurity regions iii! 3 and electrode 5,
A cell capacitor is formed by the insulating film 6 sandwiched therebetween. Furthermore, a field effect transistor 1 to a transistor (FET) is formed by the impurity regions 3 and 4, the gate insulating film 7, and the gate electrode 8. This F E
The gate electrode 8 of T forms a word line WL, and the impurity region 4 is connected to a bit line BL. With this configuration, charges are transferred into and out of the cell capacitor via the FET, and reading and writing are performed as a dynamic cell.

FIG. 5 shows the structure of a conventional trench type dynamic memory cell. This is to form a groove in the semiconductor substrate 1 in order to increase the capacitance of the cell capacitor, thereby increasing the substantial area of the cell capacitor.

FIG. 6 shows the structure of a conventional dynamic memory cell in which a cell capacitor is formed outside the semiconductor substrate 1. As shown in FIG.

In this way, both electrodes 5 and 5' constituting the cell capacitor are formed outside the semiconductor substrate 1 and also above the gate electrode 8, thereby expanding the substantial area of the cell capacitor and increasing its capacitance. can.

The dynamic memory cell shown in FIG. 7 has a slightly different structure from each of the memory cells described above. An N-type well 9 is formed on a P-type semiconductor substrate 1, and this N-type well 9 includes an N+ impurity region 10° 11 and a P-type impurity region 12.
is formed.

A gate electrode 14 is formed above the P-type impurity region 12 with a gate insulating film 13 interposed therebetween. Further, a word line WL is connected to the N+ impurity region 10, a write bit line BL is connected to the gate electrode 14, and a read bit line BLR is connected to the N+ impurity region 11. FIG. 8 is an equivalent circuit of the dynamic memory cell shown in FIG. 7. Here, nodes a, b, c, and d are an N+ impurity region 10, a P-type impurity region 12, and an N+ impurity region 11, respectively.
, corresponds to N-well 9. Further, the transistor T1 is a junction FET composed of an impurity region 10, 11, 12, a gate insulating layer 13, and a gate electrode 14, and the transistor T2 is a junction FET composed of an impurity region 10, a gate insulating layer 13, and a gate electrode 14.
, and a P-type semiconductor substrate 1.

With this structure, charges are transferred to the bit line BL.
From R to the impurity region 12, storage is performed.

Reading is performed by applying a voltage to the bit line BL and observing the current flowing through the N well 9. N well 9
Since the current flowing through the impurity region 12 depends on the accumulated charge in the impurity region 12, the logic state of the memory cell can be read by observing this current. Furthermore, since this current is amplified by the bipolar transistor T2, the memory cell can function satisfactorily even if it is miniaturized.

[Problems with background technology]

As mentioned above, various structures of dynamic memory cells have been developed, but each of these conventional dynamic memory cells has drawbacks. In general, the basic principle of dynamic memory is to use a small amount of charge accumulated in a cell as a read signal and to amplify this signal with a sense amplifier. In order to increase the integration density of a memory, the cell size must be reduced, but in order to keep the amount of stored charge above a certain limit, the cell capacitance per unit area must be increased. For this reason, the dielectric materials constituting cell capacitors are becoming thinner year by year, and are approaching their physical limits. For this reason, the planar type memory cell shown in FIG. 4 has reached the limit where further integration cannot be achieved.

In order to ensure cell capacitance without reducing the thickness of the dielectric that constitutes the cell capacitor, the area of the cell capacitor must be increased. Cells of the type shown in FIGS. 5 and 6 seek solutions in this direction. However, these types of cells also have limitations that prevent them from being able to keep up with future demands for higher integration. In the trench type memory cell shown in FIG. 5, the depth of the trench is required to be deeper, and in the type memory cell shown in FIG. 6, it is required to expand upwardly of the substrate. When this three-dimensional spread occurs, various leak paths are created due to parasitic effects,
Once a certain limit is exceeded, it no longer functions as a memory.

On the other hand, the type of memory cell shown in FIG. 7 differs in principle from the above-mentioned memory cell in that the cell itself has an amplification effect. However, since the junction FET, which plays the most important role in this cell, is a parasitic element, it has the disadvantage that it is extremely difficult to control its characteristics during manufacturing. In particular, in FIG. 7, controllability near the boundary between the P-type impurity region 12 and the element isolation insulating film 2 present above the plane of the figure is poor, and variations in characteristics tend to occur for each element. If the characteristics of each element vary in this way, the sense margin decreases, causing erroneous reading and writing.

Furthermore, since the N-type well 9 must be formed separately for each memory cell, there is also the problem that extreme miniaturization cannot be achieved.

(Objective of the Invention) Therefore, an object of the present invention is to provide a dynamic memory cell that can be further miniaturized and can operate reliably.

[Summary of the invention]

The features of the present invention include, in a dynamic memory cell, a cell capacitor formed on a semiconductor base layer, a bipolar transistor having one electrode of the cell capacitor as a base and the semiconductor base layer as a collector, and a base of the bipolar transistor. a field effect transistor to which one of the source and the drain is connected;
The other electrode of the cell capacitor is connected to the word line, the emitter of the bipolar transistor is connected to the bit line, and the other of the source or drain of the field effect transistor is connected to the bit line. The electric charge is amplified and taken out by a bipolar transistor, allowing for further miniaturization than conventional memory cells and moreover ensuring reliable operation.

[Embodiments of the invention]

The present invention will be explained below based on illustrated embodiments.

FIG. 1 is a structural diagram showing an example of a dynamic memory cell according to the present invention. An N-type well 15 is formed on a P-type semiconductor substrate 1 .

The N-type tunnel 15 does not need to be formed separately for each memory cell. A P-type impurity region 16 is formed in the surface layer of the N-type well 15, and this P-type impurity region 1
An N+ impurity region 17 is formed in a part of 6. An electrode 18 is formed above the P-type impurity region 16 with the insulating film 6 interposed therebetween.

This electrode 18 also serves as a read word line wLR.

Further, a bit line BL is connected to the N+ impurity region 17. P-type impurity region 16 and electrode 1 with insulating film 6 in between
8 form both electrodes of the cell capacitor, and the N+ impurity region 17, the P type impurity region 16, and the N
Bipolar transistor T3 whose type well 15 is NPN type
will be formed. In operation, the N+ impurity region 17 serves as an emitter, and the N-type well 15 serves as a collector. Also, N
A P+ impurity region 19 is formed in the surface layer of the type well 15, separated from the P type impurity region 16.

Furthermore, a gate electrode 21 is provided via a gate insulating film 20 to form a channel between the P-type impurity region 16 and the P+ impurity region 19, forming a transistor T4 which is a P-channel FET. The gate electrode 21 also serves as a write word line wLW.

FIG. 2 shows an equivalent circuit of the memory cell shown in FIG. 1. Here, C8 is a cell capacitor, and CB is a parasitic capacitance regarding the bit line BL. Is there electricity on the P-type semiconductor substrate 1? l! V8
8, and power source ■ to the N-type well 15. If 0 is applied, the bipolar transistor T3 is connected to the power source as shown in the figure. Further, the node e corresponds to the P-type impurity region 16, and charges can be input and output through the transistor T4.

Next, the operation of this apparatus will be explained with reference to the equivalent circuit shown in FIG. 2 and the time chart shown in FIG. The logic state of the memory cell is determined based on the potential of node e.

That is, when node e is VSS, it represents logic II 1 II, and when node e is -VoC, it represents logic "O".

Now, if we consider the potentials of each part before reading out, we can see the potentials in Figure 3 (a).
, (a') as shown in periods 1-11,
The read word line WL maintains VSS, and the write word line WL maintains ■. Transistor T4 is OF
Since it is in the F1ICC state, the potential of node e during the same period is the third
As shown in figure (b), ■, 8 (Logic 111 II)
Or -cc (logic "O") is maintained, and the bit line B is precharged to 88 as shown in FIG. 3(C). Once the address to be read is determined here, time t
1, the potential of the read word line WLR changes from ■38 to ■. . rise to Since the node e is capacitively coupled to the word line WL, as shown in FIG. 3(b), as the potential of the read word line W increases, the potential V or ■,
It rises to 8. Considering that the node e is the base of the bipolar transistor T3, when the node e becomes equal to or higher than the forward operating voltage V1 of the base-emitter junction of the transistor T3, the transistor T3 is turned on. Therefore, if a logic "1" is written, the transistor T3 will eventually turn ONL, from the power supply V.0 to the bit line B.
Current flows to bit line B, as shown in Figure 3(C).
The potential of L rises to V-V. Conversely, when the logic "OTT" is written, the transistor T3 remains OFF and the potential of the bit line BL does not rise.

The potential of the bit line BL is then latched to VSS or Vcc.

Subsequently, at time t3, a restore or write operation is performed. That is, if the logic state of the cell is to be the same as the previous state, leave the bit line BL latch as is, and if the cell is to be in the opposite state, the bit line B is latched.
L is inverted and latched, and the potential of the write word line WL is lowered to V1 or lower. Here, ■ is the threshold value of the transistor T4 as a transfer gate.

As a result, the transistor T4 is turned on, and the potential of the node e becomes the same as the potential of the bit line BL.
1” (Voo) or 'O' (V88) is written. Subsequently, at time t4, the write word line WL
The potential of ■. 0, transistor T4 is turned off, and read word line WLR is lowered to V88 at time t5, the potential of capacitively coupled node e is also lowered, and V (logic II
I 11 ) or -Vo. (Logic 110 II)
It becomes S.

Now, here is the logic 1 appearing on the bit line BL during reading.
Consider the potential difference between 10 II and '1'', that is, the read margin.In the conventional memory cells shown in FIGS. 4 to 6, the amount of charge accumulated in the cell capacitor Q-C
3■o. Therefore, the potential change of the bit line BL dif
is, Vd, f= (C8/C3)Voo ・(1)
It is. If the parasitic capacitance of the bit line B[ can be reduced or the cell capacitor capacitance C8 can be increased, Vd1r can be increased and the read margin can be increased, but in reality, in conventional memory cells (C/C ,) 1/
The limit is about 10.

On the other hand, in the memory cell according to the present invention, the logic 111 II
In the case of period 1-1. , the word line WL is VS
While the potential has increased from S to ■oo, 1. Since the potential of the node e has increased only to VSS to ①, the amount of charge that has escaped from the cell capacitor C8 to the bipolar transistor T is C(Voo-V) S. Therefore, the charge supplied to the bit line BL is βC8, where β is the amplification factor of the transistor T.

(Voo-V). Since the potential of the bit line at this time (potential before being latched) is V-VF, the following relational expression regarding the charge can be obtained.

βC(V-V)=C(V-VF)...(2)S
CCB By rearranging this equation, we obtain the following equation (3). The bit line BL takes a value of Vss or v-v depending on the logic state, and if Vss=Ov, the potential change of the bit line BL is vdif-v-■, and Equation (4) is finally obtained.

(4) Comparing equations (1) and (4), the effects of the present invention become clearer. As mentioned above, generally (cs/CB)
The limit is about 1/10, but since B>1, (
In equation 4), the fractional coefficient term on the right side is not significantly affected by the value of (C8/C6) and becomes approximately 1.

Conversely, in the memory cell of the present invention, even if C8 is made smaller, it is possible to secure V1, that is, a read margin comparable to that of the conventional memory cell. Therefore, it is possible to miniaturize according to the scaling law using the existing technology as is.

Furthermore, since the NPNPNP polar transistor can be manufactured with sufficient controllability using current technology, there are no difficulties in the manufacturing process compared to the conventional memory cell shown in FIG. Further, since there is no need to separate the N-type well 15 for each memory cell, miniaturization becomes possible.

Furthermore, since writing is performed via the transistor T4, it can be easily performed regardless of the characteristics of the transistor T3.

In the above-described embodiment, the N-type semiconductor base layer was formed on the P-type semiconductor substrate 1 in the form of the N-type well 15.
An originally N-type semiconductor substrate may be used as the semiconductor base layer without providing a well structure.

However, in order to prevent soft errors caused by α rays, it is preferable to use a well structure as in this embodiment.

Further, it is also possible to adopt a structure in which the relationship between the P type and the N type in the above-described embodiment is completely reversed.

〔Effect of the invention〕

As described above, according to the present invention, in a dynamic memory cell, the charge of a cell capacitor formed on a semiconductor base layer is amplified and read out by a bipolar transistor, so that it is possible to achieve further miniaturization than conventional memory cells. This enables reliable operation. Further, since a dedicated FET gate is provided for writing, writing can be easily performed regardless of the characteristics of the bipolar transistor.

[Brief explanation of drawings]

FIG. 1 is a structural diagram showing an example of a dynamic memory cell according to the present invention, FIG. 2 is an equivalent circuit of the memory cell shown in FIG. 1, and FIG. 3 is a time chart explaining the operation of the memory cell shown in FIG. 1. , FIGS. 4 to 7 are structural diagrams showing an example of a conventional dynamic memory cell, and FIG. 8 is an equivalent circuit of the memory cell shown in FIG. 7. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film for element isolation, 3...
... Impurity region, 4... Impurity region, 5.5'...
Electrode, 6... Insulating film, 7... Gate insulating film, 8...
- Gate electrode, 9... N type well, 10... N+ impurity region, 11... N+ impurity region, 12... P type impurity region, 13... Gate insulating film, 14... Gate Electrode, 15... N-type well, 16... P-type impurity, 17... N+ impurity region, 18... Electrode, 19.
...P+ impurity region, 20...gate insulating film, 21.
...Gate electrode, T1...Junction FFT1T
2...PNP type bipolar transistor, T3...
NPN type bipolar transistor, T4...P channel FET. WLR...word line for reading, WL...word line for writing, BL...bit line, a-e...each node of the equivalent circuit. Applicant's agent Sato −O〇 −〇 Q ++7 ++″＋
8 Figure 4 Figure 5 Blank Figure 7 Figure 8

Claims (1)

[Scope of Claims] 1. A cell capacitor formed on a semiconductor base layer, a bipolar transistor having one electrode of the cell capacitor as a base and the semiconductor base layer as a collector, and a source or a base of the bipolar transistor. a field effect transistor to which one of the drains is connected, the other electrode of the cell capacitor is connected to a word line, the emitter of the bipolar transistor is connected to a bit line, and the field effect transistor A dynamic memory cell characterized in that the other of the source or drain of the dynamic memory cell is connected to the bit line. 2. The dynamic memory cell according to claim 1, wherein the semiconductor base layer has a well structure formed on a semiconductor substrate of opposite conductivity type. 3. The dynamic memory cell according to claim 1 or 2, wherein the semiconductor base layer has a trench and the cell capacitor has a trench structure formed also on the inner surface of the trench. 4. The dynamic memory cell according to any one of claims 1 to 3, wherein the cell capacitor is formed outside the semiconductor base layer.