JPH0512951U - Memory parity check method - Google Patents

Abstract

(57) [Abstract] [Purpose] A circuit system that does not generate a parity error signal while the built-in parity generation circuit is utilized when a CPU with an even parity generation circuit reads an unmounted memory space. To do. According to the present invention, a CPU 101 having an even parity generation circuit 102 built therein and a bidirectional data buffer 103 are provided.
A bidirectional buffer 104 for parity data, a pull-up resistor 105 for data, a pull-down resistor 106 for parity data, a memory element 107, a CPU data bus 108, a CPU parity data bus 109, Memory data bus 110 and memory parity data bus 11
It is composed of 1.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a parity check method for a memory circuit in a personal computer or the like.

[0002]

[Prior art]

 FIG. 3 is a block diagram showing an example of the configuration of a memory parity check circuit in a conventional system in which a memory parity error is not generated at the time of a memory unmounted space read. It is composed of a CPU 301, 32 bidirectional buffers 303, an odd parity generation circuit 304, 32 data pull-up resistors 305, 4 parity pull-up resistors 306, and a memory device (not mounted) 307. There is. The CPU 301 includes a built-in even parity generation circuit 302, which is not used in this circuit example.

The CPU 301, the bidirectional buffer 303, and the odd parity generation circuit 304 are connected by a 32-bit CPU data bus 308, and the bidirectional buffer 303, the data pull-up resistor 305, the memory element 307, and the odd parity. The generation circuit 304 is connected by a 32-bit memory data bus 310, and the odd parity generation circuit 304, the parity pull-up resistor 306, and the memory element 307 are connected by a 4-bit memory parity data bus 311 and a bidirectional buffer. The read / write signal 312 output from the CPU is connected to the 303 and the odd number parity generation circuit 304, and the odd number parity generation circuit 304 outputs the parity error signal 313.

Next, an operation when the CPU 301 reads a memory unmounted space will be described. When the CPU 301 reads the memory element (not mounted) 307, the memory data bus 310 and the memory parity data bus 311 are all pulled up, so that they are all at "H (high)" level. The CPU sets the read / write signal 312 to the "L (low)" level so that the bidirectional buffer 303 transmits data from the memory data bus 310 to the CPU data bus 308, and the CPU data bus 308 is all "". When the H level is reached, the CPU 301 reads all the "H" levels.

The odd parity generation circuit 304 divides the 32-bit memory bus 310 into 4 bytes in 8-bit units, and the 8-bit unit of the memory parity data bus 311 corresponds to the 8-bit units of the memory data bus 310. The number of "H" level bits of 9 bits in total is counted. If the number is an even number, a parity error signal 313 is output because a parity error has occurred, and if the number is an odd number, the parity error signal 313 is not output. In this case, since the memory data bus 310 and the memory parity data bus 311 are all at "H" level, the number of "H" level per byte becomes an odd number of 9 and no parity error occurs and no parity error signal is generated. Does not appear.

[0006]

[Problems to be solved by the device]

 However, in the example of the conventional memory parity check circuit described above, since the memory parity data bus is pulled up, it is connected to the CPU through the bidirectional buffer as it is, and the even parity generation circuit built in the CPU is connected. Since it cannot be used, there was a problem that an odd parity generation circuit had to be provided separately. By the way, in order to use the even parity generation circuit built in the CPU, in order to check the mounting space of the memory when the personal computer or the like is started up, specific data is sequentially written from the memory at the lower address. Read and compare, if the read data is the same, it is judged that the memory space is mounted, but at that time, it is necessary to try to read and write in the unmounted space, and the system is not stopped by parity error. For that, technology is required.

The present invention has been made in view of the above points, and an object thereof is to provide a memory parity check circuit utilizing an even parity generation circuit incorporated in the CPU in order to eliminate the above problems. To do.

[0008]

In order to solve the above-mentioned problems, the present invention is a system using a CPU having an even parity generation circuit built therein, and the invention of claim 1 has a memory data bus as shown in FIG. This is done by pulling up the memory parity data bus and connecting it to the CPU via the bidirectional buffer and the newly provided CPU parity data bus.

In addition, the invention of claim 2 pulls up the memory data bus as shown in FIG. 2, pulls up the memory parity data bus to provide an inversion type bidirectional buffer and a newly provided CPU parity data bus. It is connected to the CPU via the CPU.

[0010]

[Action]

 When the CPU reads the unmounted memory area, the invention of claim 1 pulls up the memory data bus to "H" level, and pulls down the memory parity data bus to "L" level. And By doing so, the number of "H" level bits per byte becomes an even number of 8, and the even parity generation circuit built in the CPU can be used.

According to the second aspect of the invention, the memory parity data bus is pulled up, but since it is connected to the CPU through the inverting type bidirectional buffer, the CPU of the first aspect has the same structure. It is the same as invented.

[0012]

【Example】

 An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention according to claim 1, which is a CPU 101, 32 bidirectional buffers 103 for data, 4 bidirectional buffers 103 for parity data, and 4 bidirectional buffers 103 for parity data. It is composed of a bidirectional buffer 104 for parity data, 32 data pull-up resistors 105, 4 parity pull-down resistors 106, and a memory element (not mounted) 107. The parity generation circuit 102 is incorporated.

The CPU 101 and the data bidirectional buffer 103 are connected by a 32-bit CPU data bus 108, and the data bidirectional buffer 103, the data pull-up resistor 105, and the memory element (not mounted). ) 107 is connected by a 32-bit memory data bus 110. The CPU 101 and the bidirectional buffer for parity data 104 are connected by a 4-bit CPU parity data bus 109, and the bidirectional buffer for parity data 104, the pull-down resistor for parity 106, and the memory element 107 are 4-bit memory parity data. -Connected by Tabus 111. A read / write signal 112 output from the CPU is connected to the data bidirectional buffer 103 and the parity data bidirectional buffer 104. The built-in even parity generation circuit 102 outputs the parity error signal 113.

Next, the operation when the CPU 101 reads the memory unmounted space will be described. When the CPU reads the memory device (not mounted) 107, the memory data bus 110 is pulled up, so that all are at "H" level, and the memory parity data bus 111 is pulled down, so that all is "L". It becomes a level. The CPU 101 sets the read / write signal 112 to "L" level so that the data bus bidirectional buffer 103 transmits data from the memory data bus 110 toward the CPU data bus 108 for parity data bus use. The bidirectional buffer 104 transmits data from the memory parity data 111 to the CPU parity data bus 109.

Therefore, all of the CPU parity buses 108 become "H" level, and the CPU 101 reads all the bits "H" level. Further, all the CPU parity data buses 109 are set to the "L" level, and all the "L" levels are input to the built-in even parity generation circuit 102. The built-in even parity generation circuit 102 divides the 32-bit CPU data bus 108 into 4 bytes in 8-bit units, and the 8-bit unit of the CPU data bus 108 corresponds to the 8-bit unit of the CPU parity data bus 109. The total number of 9-bit "H" level bits is counted. If the number is an odd number, a parity error 113 signal is output because a parity error has occurred, and if the number is an even number, the parity error signal 113 is not output. In this case, since the CPU data bus 108 is all "H" level and the CPU parity data bus 109 is all "L" level, the number of "H" level per byte is 8 and it is an even number, and no parity error occurs. Therefore, the parity error signal 113 is not output.

FIG. 2 is a block diagram showing an embodiment of the invention of claim 2. CPU 201, 32 data bidirectional buffers 203, 4 parity data inverting bidirectional buffers 204, 32 data pull-up resistors 205, and 4 parity It is composed of a pull-up resistor 206 and a memory element (not mounted) 207, and the CPU has an even parity generation circuit 202 built therein. The CPU 201 and the data bidirectional buffer 203 are connected by a 32-bit CPU data bus 208, and the data bidirectional buffer 203, the data pull-up resistor 205, and the memory element 2007 are 32-bit memory data. -Connected by Tabus 210. The CPU 201 and the inversion type bidirectional buffer 204 for parity data are connected by the 4-bit CPU parity data bus 209, and the inversion type bidirectional buffer 204 for parity data, the pull-up resistor 206 for parity and the memory element 207 are connected. They are connected by a 4-bit memory parity bus 211. A read / write signal 212 output from the CPU is connected to the data bidirectional buffer 203 and the parity data inverting type bidirectional buffer 204. The built-in even parity generation circuit 202 outputs a parity error signal 213.

Next, the operation when the CPU 201 reads the memory unmounted space will be described. When the CPU 201 reads the memory device (not mounted) 207, the memory data bus 210 and the memory parity data bus 211 are pulled up, so that all of them become "H" level. The CPU 201 sets the read / write signal 212 to the "L" level so that the data bus bidirectional buffer 203 transmits the data from the memory bus 210 toward the CPU data bus 208, and the parity data bus inversion type both. The buffer 204 transmits data from the memory parity data bus 211 to the CPU parity data bus 209. Therefore, the CPU data buses 208 are all set to "H" level, and the CPU 201 reads all "H" level. Further, the CPU parity data bus 209 is all at "L" level because the memory data bus 211 is inverted, and all bits "L" level are input to the built-in even parity generation circuit 202.

The built-in even parity generation circuit 202 divides the 32-bit CPU data bus 208 into 4-byte units of 8-bit units, and the 8-bit unit of the CPU data bus 208 corresponds to the 8-bit unit of the CPU parity data bus 209. The number of 1-bit "H" level bits of 9 bits in total is counted. If the number is an odd number, the parity error signal 213 is output because a parity error has occurred, and if the number is an even number, the parity error signal 213 is not output. In this case, the CPU data bus 208 is all at the "H" level, and the CPU parity data bus 209 is all at the "L" level. Is not generated and the parity error signal 213 is not output.

[0019]

[Effect of the device]

 As described in detail above, according to the present invention, the following effects are expected. According to the first aspect of the invention, the memory data bus is pulled up and the memory parity data bus is pulled down to connect to the CPU. Further, according to the second aspect of the invention, the CPU parity data bus and the memory parity data bus are connected. Since an inversion type bidirectional buffer is connected between the CPU and the CPU, the even parity generation circuit built into the CPU is not used to generate a memory parity error at the time of a memory unmounted space read, so the number of parts is small. A cheap and highly reliable system can be constructed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a memory parity check circuit according to the present invention as set forth in claim 1;

FIG. 2 is a block diagram showing a configuration example of a memory parity check circuit according to the present invention as defined in claim 2;

FIG. 3 is a block diagram of a conventional memory parity check circuit.

[Explanation of symbols]

 101 CPU 102 Even parity generating circuit with built-in CPU 103 Bidirectional buffer for data 104 Bidirectional buffer for parity data 105 Pullup resistor for data 106 Pulldown resistor for parity data 107 Memory element (not mounted) 108 CPU data -Data bus 109 CPU parity data bus 110 Memory data bus 111 Memory parity data bus 112 Read / write signal 113 Parity error signal

Claims (2)

[Scope of utility model registration request] 1. A CPU incorporating an even parity generation circuit
In a system that does not generate a memory parity error when reading an unimplemented memory space, the memory data bus is pulled up to create a bidirectional buffer and CP.
A U parity bus is connected to the CPU, a memory parity data bus is pulled down, a bidirectional bus and a CPU parity data bus are connected to the CPU, and an even parity generation circuit built in the CPU is connected. A memory parity check method characterized in that no parity error is output when reading or writing to an unimplemented memory space. 2. A CPU incorporating an even parity generation circuit
In a system that does not generate a memory parity error when reading an unimplemented memory space, the memory data bus is pulled up to create a bidirectional buffer and CP.
Connected to the CPU via the U data bus, pulling up the memory parity data bus and connected to the CPU via the inversion type bidirectional buffer and CPU parity data bus, and generating even parity built in the CPU. A memory parity check method that prevents the output of a parity error when reading and writing to an unimplemented memory space using a circuit.