KR930007367Y1 - Parrity check system - Google Patents

Abstract

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Description

Parity check system

1 is a configuration diagram of a parity check system of a conventional system memory.

2 is a parity check system configuration diagram of the system memory of the present invention.

* Explanation of symbols for main parts of the drawings

1-8: first parity generating unit 9: second parity generating unit

10: parity check ram 11: parity error generating unit

The present invention relates to a parity check for detecting error data on the system memory. Especially, the parity check is eliminated by using 8-bit unit and parity check is performed by 64-, 32-, 16-, or 8-bit unit. The present invention relates to a parity check system for reducing and checking the data in system memory more efficiently.

The parity check system for detecting that the data is read / written on the system memory of a conventional computer writes the input data D ₀ -D ₁₅ and writes the data to each bit as shown in FIG. A parity generating unit (1) (2) for generating parity with respect to the parity, a parity check (3) (4) for checking parity output from the parity generating unit (1) (2) in units of 8 bits, respectively; Parity bit of the parity check (3) (4) and the memory read signal (MEMR) inverted and input from the outside through the inverter gate (I ₁ ) and the combination and write to each of the parity generating unit (1) (2) the aND gate (aND ₁₎ (aND _2), and a parity generating unit (1) and (2) OR a raemsel signal (RAMSEL) inputted from the parity and the external aND gate (aND ₂₎ for generating a parity-check error in the ( ₄ as aND), NOR gate (NOR ₁₎ and the flip-flop (FF ₁₎ to the parity error generation unit 5 There is sex.

In the conventional parity check system configured as described above, the 8-bit data (D ₀ -D ₇ ) (D ₈ -D ₁₅ ) are recorded in the parity generating unit (1) (2). It is the input data _{(D 0 -D 7) (D} 8 - 15) to generate the flute T for each bit "1" or " "Is inputted into the parity check ram (3) (4), and the parity check ram (3) (4) checks and records the" 1 "number output from the parity generating part (1) (2).

In addition, the parity generating unit (1) (2) and the gate (AND ₁ ) of the parity bit of the parity check (3) (4) by an external memory read signal (MEMR) inverted through the inverter gate (I ₁ ). (AND ₂ ) and is combined with the 8-bit data read through the AND gate (AND ₁ ) (AND ₂ ) to determine whether the number is even or odd.

If the parity check ram (3) (4) is designed to be an even number, it becomes "1" when an error occurs, but always "0" when no parity error occurs.

However, such a conventional parity check system requires one parity check bit for each read or write of 8 bits of data, compared with the case where there is one parity check bit per 8 byte (64 bit) or 4 byte data unit. There was an unnecessary problem to use 8 times or 4 times parity check.

In view of such a conventional problem, the present invention checks the parity check in 64-bit, 32-bit, 16-bit, and 8-bit units to reduce waste of the parity check ram and to check the data in system memory more efficiently. When the system is devised, the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of a parity check system of the present invention. As shown in FIG. 2, a first parity generating unit 1-8 for recording data D ₁ -D ₆₃ and generating parity for each bit is provided. The second parity generating unit 9 generates parity for each of the bytes output from the parity generating unit 1-8, and the parity outputted from the second parity generating unit 9 is 64 bits. The parity check ram 1 checks in units of 32, 16, and 8 bits, and the external memory read signal MEMR is inverted through the parity of the parity check ram 10 and the inverter gate I ₁ . The AND gate AND ₁ inputted to the second parity generator 9 in combination with the parity of the second parity generator 9 and the external ram cell signal RAMSEL generates a parity check error. The parity error generation unit 11 includes a gate AND ₂ and a flip-flop FF ₁ .

Referring to the operation, effects of the present invention configured as described above in detail.

First, when 8-bit data D ₀ -D ₆₃ are recorded in the first parity generating unit 1-8 as shown in FIG. 2, the first parity generating unit 1-8 receives the input data D ₀ −. D ₆₃ ) primary parity for each bit frame is generated and recorded in the second parity generating unit 9, and the second parity generating unit 9 receives bytes inputted from the first parity generating unit 1-8. "1" or "" in the parity check 10 to generate secondary parity for each byte). Therefore, the parity check ram 10 checks and records the number of " 1 " output from the second parity generator 9, and the second parity generator 9 is an inverter. If evenly the parity check 10 is designed by the external memory read signal MEMR inverted through the gate I ₁ , 8 bytes (or 4 bytes, 2 bytes, 1 byte), which is the maximum checkable data. In the case of an error data, the output of the second parity generating unit 9 becomes "1" and is ANDed at the AND gate AND ₂ of the parity error generating unit 11 together with the external ram cell signal RANSEL, and flip-flop again. At (FF ₁ ), a parity check error is generated in synchronization with the memory read signal MEMR.

As described in detail above, the present invention eliminates the parity check in 8-bit units and checks the parity in 64, 32, 16, and 8-bit units, thereby reducing waste of the parity check system. The effect is that the data in memory can be checked more efficiently.

Claims (1)

A first parity generating unit (1-8) which writes data in units of 8 bits each and generates parity for each bit, and secondly generates parity for each byte of the parity generating unit (1-8). A second parity generator 9, a parity checker 10 that checks the parity of the second parity generator 9 in units of 8, 4, 2, 1 bytes, and the second parity generator ( And a parity error generating unit (11) which generates a parity check error by logically combining the parity of (9) with an external ram cell signal (RAMSEL).