JPH06250935A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate the extension of a storage capacity and to improve a memory capacity/cost rate by using an information error detection/correction data storage part as an information storage part. CONSTITUTION:An error control part 11 inputting information DATA and error detection/correction data ECC and outputting data obtained by detecting/ correcting the error of information DATA and error detection/correction data ECC, an information storage part 12 storing data and error detection/correction data ECC, both of which are outputted from the error control part 11, and a memory switching part 13 selecting either information DATA or error detection/correction data ECC based on an external control signal SC and supplying information DAT or error detection/correction data ECC to the information storage part 12 are provided. When the external control signal SC is in a first state, data and error detection/correction data ECC are stored in the information storage part 12 and information DATA is stored in the error detection/correction data storage part 12B of the information storage part 12 in a second state.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIG. 6) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Action Example (1) Description of First Example (FIGS. 2 to 4) (2) Description of the second embodiment (FIG. 5) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to improvement of a memory device having an information storage part and an information error detection / correction data storage part in a semiconductor memory part. Is.

In recent years, the processing capacity of personal computers and workstations has been remarkably improved.
AD / CAM (Computer Aided Design / Computer Aid
ed Manufacturing) and image processing fields. In these application systems, the processing speed of an external storage device such as a magnetic disk device limits the performance of the system, and it is strongly desired to increase the processing speed.

By the way, in a magnetic disk or the like as a rotating medium for reading / writing serial data, error correction is performed by a Reed-Solomon method. Further, there is provided a semiconductor memory device having a very short waiting time for data access as compared with a magnetic disk device and having high-speed access and high-speed data transfer. Note that the Hamming ECC method is used for error correction in a semiconductor memory that reads / writes data in parallel.

However, when a semiconductor memory device having an information storage unit and an information error detection / correction data storage unit is used as a frame memory, it is possible to store n-bit information in the information storage unit. However, it is difficult to store n-bit information in the information error detection / correction data storage unit.

Therefore, there is a demand for an apparatus that can easily increase the storage capacity and improve the memory capacity / price ratio by using the information error detection / correction data storage section as the information storage section.

[0007]

2. Description of the Related Art FIG. 6 is an explanatory view of a semiconductor memory device according to a conventional example, and FIG.
It is a conceptual diagram of CSI. Further, FIG. 6B shows a configuration diagram of the semiconductor memory device.

For example, 9 data lines and 9 control lines
S to be incorporated into one signal cable and process various data
In the CSI (Small Computer System Interface) method, in FIG. 6A, a small microcomputer 1, a frame memory 2, a numerical data memory 3 and other electronic equipment 4 are connected to the signal cable 5.

The frame memory 2 is composed of a RAM (writable / readable memory at any time), and stores information obtained by digitizing images and sounds processed by the small microcomputer 1. Further, the numerical data memory 3 which requires higher accuracy than the frame memory 2 is composed of a semiconductor memory device and stores numerical data processed by the small microcomputer 1.

In FIG. 6B, the semiconductor memory device comprises an error control unit 6 and an information storage unit 7. The information storage unit 7 comprises an information storage unit 7A and an information error detection / correction data storage unit 7B. Become.

It should be noted that the total memory capacity of the information storage unit 7 (storage capacity that can be used from the host device) is 1 bit error correction / capacity of the information storage unit 7A for storing information = 1.
In the case of detecting a 2-bit error, the data width is about 1.63 times at 8 bits, about 1.38 times at 16 bits, and about 1.22 times at 32 bits.

The function of the device is that, for example, when the numerical data processed by the small microcomputer 1 is accumulated, the error control unit 6 first generates error detection / correction data ECC for the numerical data. The numerical data is stored in the information storage unit 7A. Further, the error detection / correction data ECC provided for error detection / correction is stored in the information error detection / correction data storage unit 7B. After that, when reading the numerical data, first, the information storage unit 7A
When the address is designated, the numerical data is read from the information storage unit 7A, and the numerical data is error-detected / corrected by the error control unit 6 based on the error detection / correction data ECC.

Thus, at the time of reading information, it is possible to check the bit loss of the information storage unit (semiconductor memory) 7A due to the α ray failure or the like, and the reliability of the read information (numerical data) can be improved.

[0014]

By the way, the conventional S
According to the CSI method, information obtained by digitizing images, sounds and the like is stored in the frame memory 2 including a RAM, and numerical data that requires higher accuracy than the digital information is a numerical data memory 3 including a semiconductor memory device. It is stored exclusively in.

For this reason, in the image and sound processing performed by the small-sized microcomputer 1, a method is adopted in which the numerical data memory 3 is used as a frame memory when a memory capacity increase request is suddenly made. This is because when the amount of information such as image and sound increases, the data capacity is compressed at the time of storing the information and is restored (expanded) at the time of extraction (compression / expansion), thereby reducing the disk capacity. This is for effective use.

In this method, the restored data is distorted (noise-compressed) in order to improve the compression rate. But 10
0 [%] Although not restored to the original data, the one close to the original data is obtained. That is, while the numerical data is required to be accurate to the unit of 1 bit, it can be ignored that the information such as image and sound has a 1-bit error before and after the extraction. This eliminates the need to consider a 1-bit error in the memory of the semiconductor memory device.

However, the storage capacity seen from the host device is
In the case of 1-bit error correction / 2-bit error detection, the data width is about 1.63 times at 8 bits, about 1.38 times at 16 bits, and about 1.22 times at 32 bits. Nevertheless, only the information storage unit (capacity = 1) 7A of the numerical data memory 3 can be used as a frame memory.

For example, a semiconductor memory device having a 32 [bit] × 256 [LW] information storage section 7A and a 7 [bit] × 256 [LW] information error detection / correction data storage section 7B is used as a frame memory. When there is a request to use, 32 [bit] x 256 [LW] in the information storage unit 7A
Information can be stored, but the information error detection /
32 [bit] information cannot be stored as it is in the correction data storage section 7B.

As a result, the memory area related to the information error detection / correction data storage section 7B becomes idle, and there is a problem that the memory capacity / price ratio deteriorates. The present invention has been made in view of the problems of the conventional example, and by using the information error detection / correction data storage unit as the information storage unit, it is possible to easily increase the storage capacity and to increase the memory capacity / price. An object of the present invention is to provide a semiconductor memory device capable of improving the ratio.

[0020]

FIG. 1 is a principle diagram of a semiconductor memory device according to the present invention. As shown in FIG. 1, the first semiconductor memory device of the present invention inputs information DATA and error detection / correction data ECC, and performs error detection / correction data of the information DATA and error detection / correction data. E
Error control unit 11 for outputting CC and the error control unit 1
1. Data output from 1 and error detection / correction data E
An information storage unit 12 for storing CC and one of the information DATA and the error detection / correction data ECC are selected based on an external control signal SC, and the information DATA or the error detection / correction data ECC is stored as information. And a memory switching unit 13 for supplying to the unit 12, and when the external control signal SC is in the first state, stores data and error detection / correction data ECC in the information storage unit 12, In the state,
Error detection / correction data storage unit 12 of the information storage unit 12
It is characterized in that the information DATA is stored in B.

Further, in the first semiconductor memory device of the present invention, the external control signal SC is given by a mode select command sent from a host device.

Further, the second semiconductor memory device of the present invention is characterized in that, in FIG. 1, the external control signal SC is given by the operation of the switching circuit 14 provided in the device, and achieves the above object. .

[0023]

[Operation] According to the first semiconductor memory device of the present invention,
As shown in FIG. 1, the error control unit 11 and the information storage unit 12
And a memory switching unit 13, and the external control signal S
Based on C, the information DATA is stored in the error detection / correction data storage unit 12B set in the information storage unit 12 in advance.

For example, an error control / correction data storage unit 12B is sent from the host device to the device as an external control signal SC.
When a mode select command "to store information DATA in" is supplied, the memory switching unit 13 directly outputs the information D
The route input by the ATA is selected, and the information DATA is stored in the error detection / correction data storage unit 12B of the information storage unit 12.

As a result, the first route for storing the information DATA in the information storage unit 12A after passing through the error control unit 11 and the information DATA in the error detection / correction data storage unit 12B via the memory switching unit 13. A second route to be stored can be constructed, and can function as a memory device without error checking.

When a higher-level device supplies a mode select command to the device as an external control signal SC "stores error detection / correction data ECC in the error detection / correction data storage section 12B", The memory switching unit 13 selects a route for inputting the error detection / correction data ECC.

As a result, similarly to the conventional example, the information DATA which is error-detected / corrected by the error control unit 11 is stored in the information storage unit.
The error detection / correction data ECC stored in 12A and provided for the error detection / correction is the error detection / correction data storage unit 12
It is stored in B and can function as a memory device with an error check.

Therefore, in the case where a memory capacity is suddenly requested to be increased in the image and voice processing performed by the host device, the "information D is stored in the error detection / correction data storage section 12B".
By supplying the mode select command "to store ATA", it is possible to immediately change the function from the current numerical data memory function to the frame memory function. Therefore, by adding the function of switching the error control unit 11, the error detection / correction data storage unit 12B can be used as an information storage unit according to the intended use.

As a result, it is possible to easily increase the storage capacity viewed from the host device, and it is possible to improve the memory capacity / price ratio. Further, according to the second semiconductor memory device of the present invention, in FIG. 1, the external control signal SC is provided in the switching circuit 1 provided in the device.
Given by the operation of 4.

For example, the external control signal S is selected by adopting an operation selection for semi-fixedly connecting to the ground line GND with respect to the switching circuit 14 composed of the two-circuit one-selection changeover switch.
The “L” level as C is supplied to the memory switching unit 13. As a result, the memory switching unit 13 selects a route for inputting the error detection / correction data ECC,
Similar to the conventional example, the information DATA detected / corrected by the error control unit 11 is stored in the information storage unit 12A, and the error detection / correction data ECC used for the error detection / correction is the error detection / correction data. It becomes possible to function as a memory device with an error check stored in the storage unit 12B.

Further, the switching circuit 14 adopts an operation selection for semi-fixedly connecting to the power supply line VCC, so that the "H" level is supplied to the memory switching section 13 as the external control signal SC. Further, the memory switching unit 13 directly selects the route to which the information DATA is input and stores the information DATA in the error detection / correction data storage unit 12B of the information storage unit 12.

As a result, the first route for storing the information DATA in the information storage unit 12A after passing through the error control unit 11 and the information DATA in the error detection / correction data storage unit 12B via the memory switching unit 13. It becomes possible to function as a memory device having a second route for storing and without error checking.

Therefore, when a small microcomputer and a plurality of such devices are combined to form a SCSI system, the switching circuit 14 is switched in response to a user's request for use, whereby a memory for numerical data or a frame memory. It becomes possible to easily select functions such as. This greatly contributes to the versatility of the semiconductor memory device.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, each embodiment of the present invention will be described with reference to the drawings. 2 to 5 are diagrams illustrating a semiconductor memory device according to an embodiment of the present invention.

(1) Description of First Embodiment FIG. 2 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 (A) is an overall configuration diagram thereof.
FIG. 2B is an internal configuration diagram of the memory switching unit. 3 is an operation explanatory diagram when the memory expansion is selected in the semiconductor memory device according to the first embodiment of the present invention, and FIG.
ECC of the semiconductor memory device according to the first embodiment of the present invention
The respective operation explanatory views at the time of selection are shown.

For example, SCSI (Small Computer Syste
The optimum semiconductor memory device for m Interface) is shown in Fig. 2 (A).
In, the error control unit 11, the information storage unit 12, the memory switching unit 13, the SPC (Stored Program Contro)
l) 15, an MPU 16 and an address generation circuit 17.

That is, the error control unit 11 uses the information DATA
This is a circuit for detecting / correcting the error. For example, the error control unit 11 has a 1-bit error correction / 2-bit error detection function, and detects an error via the memory switching unit 13.
The correction data ECC is stored in the error detection / correction data storage unit 12B.
Transfer to.

The information storage unit 12 stores information DATA and error detection /
The correction data ECC is stored. For example, the information storage unit 12 includes an information storage unit 12A and an error detection / correction data storage unit 12B. The information storage unit 12A has a data width of 3
It has a memory capacity of 32 [bits] × 256 [LW] with 2 bits. The error detection / correction data storage unit 12B has 8
It has a memory capacity of [bit] × 256 [LW].

The memory switching section 13 to select on the basis of one of the information DATA or error detection / correction data ECC to an external control signal SC, the switching of address Add _D at address Add _E and memory expansion during ECC selection It is a circuit to do. For example, the memory switching unit 13 is composed of an address generation circuit 13A, an inverter 13B and switching elements SW1 to SW4 in FIG. 2B.

The address generation circuit 13A is activated when the information DATA is stored in the error detection / correction data storage section 12B, and has a function of generating an address four times with respect to the 32-bit string information DATA. For example, the address generation circuit 13A
Is a counter circuit or a sequencer, and in the case of an 8-bit string of the error detection / correction data storage unit 12B, the upper 6 bits are fixed based on the write / read permission signal R / W, and the lower 2 bits address "0,0". , "0, 1", "1,
Switching between "0", "1, 1" ...

The inverter 13B is an element for inverting the external control signal SC, and the switching elements SW1 to SW4 are, for example, n-type field effect transistors. The function of the switching element SW1 is that the external control signal SC =
When the "L" level is received, the inverted signal is received and the operation is turned on to transfer the error detection / correction data E CC to the error detection / correction data storage unit 12B. The external control signal SC
= "H" level, an OFF signal is received in response to the inverted signal, and transfer of the error detection / correction data ECC is rejected.

The function of the switching element SW2 is as follows.
When the external control signal SC = “L” level, the OFF operation is performed and the transfer of the information DATA is rejected. In addition, the external control signal SC = "H" level turns ON operation, and the information DATA
Are transferred to the error detection / correction data storage unit 12B.

The function of the switching element SW3 is to turn on by receiving the inverted signal of the external control signal SC = “L” level, and the address Add _E of the error detection / correction data ECC is stored in the error detection / correction data. Supply to section 12B. In addition, depending on the external control signal SC = “H” level,
When the inverted signal is received, the operation becomes OFF, and the supply of the error detection / correction data ECC is rejected.

The function of the switching element SW4 is as follows.
Becomes OFF operation by an external control signal SC = "L" level, rejecting the supply of addresses Add _D information DATA. Incidentally, supplied by an external control signal SC = "H" level becomes ON operation, the address Add _D information DATA to the error detection / correction data storage unit 12B.

The SPC 15 controls the storage program and supplies, for example, a read / write enable signal R / W to the address generation circuit 17 and the address generation circuit 13B. The MPU 16 includes an error control unit 11 and an information storage unit 1.
2. The input / output of the memory switching unit 13 and the SPC 15 is controlled. In addition, in the first embodiment of the present invention,
The external control signal SC is given by a mode select command sent from the host device.

The address generation circuit 17 includes the address Add of the data in which the information DATA is error-detected / corrected based on the read / write enable signal R / W and the error detection / correction data ECC used for the error detection / correction of the information DATA. Address Add _E
Is generated. Incidentally, supplies address Add in the information storage unit 12A during ECC selection, supplies address Add _E to the memory switching section 13.

In this way, according to the semiconductor memory device of the first embodiment of the present invention, as shown in FIGS. 2A and 2B, the error control unit 11, the information storage unit 12, the memory The switching unit 13, the SPC 15 and the MPU 16 are provided, and the information DATA is stored in the error detection / correction data storage unit 12B set in the information storage unit 12 in advance based on the mode select command.

For example, in order to select the memory expansion, the SC = “H” level “to store the information DATA in the error detection / correction data storage unit 12B” is supplied from the host device to the device as a mode select command. Then, Fig. 3 (A)
At the switching element S of the memory switching unit 13,
The route to which the information DATA is input is directly selected by the W1, SW3 = OFF operation and the SW2, SW4 = ON operation, and the information DATA is stored in the error detection / correction data storage section 12B of the information storage section 12. At this time, in order to store the 32-bit information DATA as shown in FIG. 3B in the memory area of 8 [bit] × 256 [LW] as shown in FIG. 32-bit string information D
Address Add _D is generated 4 times for ATA.

As a result, the first route for storing the information DATA in the information storage unit 12A after passing through the error control unit 11 and the information DATA in the error detection / correction data storage unit 12B via the memory switching unit 13. A second route for storing can be constructed and the device can function as a memory device without error checking.

In order to select the ECC function, SC = "to store the error detection / correction data ECC in the error detection / correction data storage unit 12B" as a mode select command from the upper device to the device. When the "L" level is supplied, the switching elements SW1, SW3 = ON operation, SW2, S in the memory switching unit 13 in FIG. 4A.
The route for inputting the error detection / correction data Ecc is selected by the W4 = OFF operation.

As a result, similarly to the conventional example, the data DATA error-detected / corrected by the error control unit 11 is stored in the information storage unit 12A, and the error-detection / correction data ECC used for the error detection / correction is stored. Data storage for error detection / correction
It is stored in 12B. At this time, 7-bit error detection / correction data _E CC is added to the 32-bit information DATA as shown in FIG.
The data ECC is stored in the memory area of 7 [bit] × 256 [LW] as shown in FIG. The device can be made to function as a memory device with an error check.

Therefore, in the case where a memory capacity is suddenly requested to be increased in the image and sound processing performed by the host device, the "information D is stored in the error detection / correction data storage section 12B".
By supplying the mode select command "to store ATA", it is possible to immediately change the function from the current numerical data memory function to the frame memory function.

Therefore, when the amount of information such as image and sound increases, the disk is generally adopted by a method (compression / expansion) of compressing the data at the time of storing the information and restoring (expanding) at the time of extraction. It is possible to use the capacity effectively. As a result, the information storage unit 12A and the information error detection / correction data storage unit 12B can be used as a frame memory, and the numerical data memory (capacity ratio =
Compared to the case of 1), in the case of 1-bit error correction / 2-bit error detection, the data width is about 1.63 times at 8 bits, about 1.38 times at 16 bits, and 32 bits. Thus, it becomes possible to use the memory capacity of about 1.22 times in the host device.

For example, a semiconductor memory device having a 32 [bit] × 256 [LW] information storage section 12A and an 8 [bit] × 256 [LW] information error detection / correction data storage section 12B is used as a frame memory. If there is a request to use, 32 [bit] x 256 [LW] in the information storage unit 12A
32 [bits] × 256 [LW] × in the information error detection / correction data storage unit 12B.
It is possible to store 1/4 information as it is.

As a result, the memory area related to the information error detection / correction data storage section 12B can be fully used, and the memory capacity / price ratio can be improved. (2) Description of Second Embodiment FIG. 5 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention. The second embodiment is different from the first embodiment.
In this embodiment, the external control signal SC is given by the operation of the switching circuit 14 provided in the device.

That is, the switching circuit 14 is composed of two circuits and one selection changeover switch, and its neutral point c is MP.
It is connected to U16 and the memory switching unit 13. The connection point a of the circuit 14 is connected to the ground line GND, and the other connection point b is connected to the power supply line Vcc. The function of the switching circuit 14 is such that when the contact a is selected, the external control signal SC
= “L” level is supplied to the MPU 16 and the memory switching unit 13, and when the contact b is selected, the external control signal SC =
The “H” level is supplied to the MPU 16 and the memory switching unit 13.

Thus, according to the semiconductor memory device of the second embodiment of the present invention, in FIG. 5, the external control signal SC is applied to the switching circuit 1 provided in the device.
Given by the operation of 4.

For example, as in the case of the first embodiment, when the ECC function is selected, by selecting the contact a side in the switching circuit 14, the "L" level as the external control signal SC is switched to the memory. It is supplied to the section 13. As a result, the memory switching unit 13 selects the route for inputting the error detection / correction data ECC, and the information DATA error-detected / corrected by the error control unit 11 is stored in the information storage unit 12A as in the conventional example. Then, the error detection / correction data ECC provided for the error detection / correction can be stored in the error detection / correction data storage unit 12B to function as a memory device with an error check.

Further, when the memory expansion function is selected in the switching circuit 14, by selecting the contact b side, the "H" level as the external control signal SC is supplied to the memory switching section 13. As a result, the memory switching unit 13 directly selects the route to which the information DATA is input, and the information DATA is stored in the error detection / correction data storage unit 12B of the information storage unit 12. This allows
Information DAT is passed to the information storage unit 12A through the error control unit 11.
The first route for storing A and the information DATA through the memory switching unit 13 for the error detection / correction data storage unit 12B
It is possible to function as a memory device having a second route to be stored in the memory without error checking.

For this reason, when a plurality of small microcomputers and the device are combined to form the SCSI system, the switching circuit 14 is switched in response to a user's request for use, whereby a memory for numerical data or a frame memory. It becomes possible to easily select functions such as. This greatly contributes to the versatility of the semiconductor memory device.

[0061]

As described above, according to the first semiconductor memory device of the present invention, the error control section, the information storage section and the memory switching section are provided, and the information storage is performed in advance based on the external control signal. Information is stored in the error detection / correction data storage section set in the section.

For this reason, even if there is a sudden request for an increase in the memory capacity in the image processing, the audio processing, etc. performed by the higher-level device, the message "information is stored in the error detection / correction data storage section" is displayed. By supplying the mode select command, it becomes possible to immediately change the function from the memory function with error check to the memory function without error check.

Further, according to the second semiconductor memory device of the present invention, the external control signal is given by the operation of the switching circuit provided in the device. Therefore, when a small microcomputer and a plurality of such devices are combined to form a SCSI system, by switching the switching circuit in response to a user's use request, a function for selecting a memory for numerical data or a frame memory can be selected. Can be easily performed. Therefore, by adding the function of switching the error control unit, the error detection / correction data storage unit can be used as the information storage unit according to the intended use.

As a result, it is possible to easily increase the storage capacity viewed from the host device, and it is possible to improve the memory capacity / price ratio. In addition, it greatly contributes to the provision of a highly reliable semiconductor memory device which is highly versatile.

[Brief description of drawings]

FIG. 1 is a principle diagram of a semiconductor memory device according to the present invention.

FIG. 2 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 3 is an operation explanatory diagram when a memory expansion is selected according to the first embodiment of the present invention.

FIG. 4 is an operation explanatory diagram when ECC is selected according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a semiconductor memory device according to a conventional example.

[Explanation of symbols]

 11 ... Error control section, 12 ... Information storage section, 13 ... Memory switching section, 14 ... Switching circuit, 12A ... Information storage section, 12B ... Error detection / correction data storage section, DATA ... Information, ECC ... Error detection / correction Data, SC ... External control signal.

Claims (3)

[Claims] 1. Data (ECC) for inputting information (DATA) and error detection / correction data, and error detection / correction of the information (DATA) and error detection / correction data (EC).
C), an error control section (11), an information storage section (12) for storing data output from the error control section (11) and error detection / correction data (ECC), and the information (DATA). ), Error detection / correction data (ECC) is selected based on the external control signal (SC), and the information (DATA) or error detection / correction data (ECC) is selected.
A memory switching unit (13) for supplying CC) to the information storage unit (12), and when the external control signal (SC) is in the first state, the information storage unit (12) stores data and error. The detection / correction data (ECC) is stored, and in the second state, the information (DATA) is stored in the error detection / correction data storage unit (12B) of the information storage unit (12). And a semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the external control signal (SC) is given by a mode select command sent from a host device. 3. The semiconductor memory device according to claim 1, wherein the external control signal (SC) is given by operating a switching circuit (14) provided in the device.