JPH05129280A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05129280A JPH05129280A JP28526991A JP28526991A JPH05129280A JP H05129280 A JPH05129280 A JP H05129280A JP 28526991 A JP28526991 A JP 28526991A JP 28526991 A JP28526991 A JP 28526991A JP H05129280 A JPH05129280 A JP H05129280A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- thermal oxide
- oxide film
- film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、所謂Ｏ3 ＴＥＯＳ法により形成される
平坦化絶縁膜の形成を良好に行なう方法に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for favorably forming a planarization insulating film formed by the so-called O 3 TEOS method.
【０００２】[0002]
【従来の技術】近年、デバイスの高密度化に伴って配線
技術は微細化、多層化の方向に進んでいる。しかし、高
集積化は信頼性を低下させる結果となっている。2. Description of the Related Art In recent years, wiring technology has become finer and more multilayered as devices become higher in density. However, higher integration results in lower reliability.
【０００３】これは、配線の微細化と多層化の進展によ
って層間絶縁膜の段差は大きくかつ、急峻となりその上
に形成される配線の加工精度信頼性を低下させる為であ
る。この為Ａｌ配線の段差被覆性の大幅な改善ができな
い現在層間平坦化の平坦性を向上させる必要がある。こ
れまでに、各種の絶縁膜の形成技術及び平坦化技術が開
発されてきたが、微細化、多層化した配線層に適用した
場合配線間隔が広い場合の平坦化の不足や配線間隙にお
ける層間膜での鬆の発生により配線間における接続不良
等が重大な問題になっている。This is because the step of the interlayer insulating film becomes large and steep due to the miniaturization of wiring and the progress of multi-layering, and the processing accuracy reliability of the wiring formed thereon is lowered. For this reason, it is necessary to improve the flatness of interlayer flattening at present, where the step coverage of Al wiring cannot be greatly improved. Until now, various insulating film forming techniques and flattening techniques have been developed. However, when applied to miniaturized and multi-layered wiring layers, lack of flattening in the case of wide wiring intervals and interlayer film in the wiring gaps. Due to the generation of voids, defective connection between wirings has become a serious problem.
【０００４】絶縁膜の平坦化技術に要求される特性とし
ては、 （１）微細な配線間隔を空洞なく埋める能力が十分であ
ること （２）良好な平坦性が得られること がある。この能力は、所謂ステップカバレージ（段差被
覆性）に依存する。このステップカバレージが良好で、
よって上記（１），（２）の要求を満たし、かつ膜質の
良好な平坦化絶縁膜が得られる技術として、近年、常圧
及び中圧Ｏ3 ＴＥＯＳ技術、即ち常圧または中圧下で
オゾンとテトラエトキシシランとを反応させる技術が注
目されている。この種の技術としては、例えば、ｊｕｎ
ｅ１２−１３，１９９０ ＶＭＩＣ Ｃｏｎｆｅｒｅｎ
ｃｅ（ＩＥＥＥ）の１８７〜１９２頁に記載がある。The characteristics required for the flattening technique of the insulating film are (1) sufficient ability to fill fine wiring intervals without voids (2) good flatness. This capability depends on so-called step coverage. This step coverage is good,
Therefore, as a technique for satisfying the above requirements (1) and (2) and obtaining a flattening insulating film having a good film quality, in recent years, atmospheric pressure and medium pressure O 3 TEOS technique, that is, ozone under normal pressure or medium pressure is used. A technique for reacting with tetraethoxysilane has received attention. Examples of this type of technology include jun
e12-13, 1990 VMIC Conference
ce (IEEE) pages 187-192.
【０００５】[0005]
【発明が解決しようとする課題】しかし、常圧及び中圧
Ｏ3 ＴＥＯＳ技術は表面反応を利用しているため、下
地層との親和性が異なると、生成する膜質や、成長速度
が異なることが知られている。特にノンドープ、即ち不
純物を含有しないＯ3 ＴＥＯＳ膜を熱酸化膜上に形成
する場合に、下地依存性が大きい。下地の溝を埋め込ん
で平坦化を行なうときは、拡散層等へのオートドーピン
グを低減するために、ノンドープの二酸化シリコン膜を
形成することが望ましいが、Ｏ3 ＴＥＯＳ技術により
かかるノンドープの二酸化シリコン膜を得る場合に、上
記の下地依存性の問題が大きい。However, since the atmospheric pressure and medium pressure O 3 TEOS technology utilizes the surface reaction, if the affinity with the underlayer is different, the quality of the formed film and the growth rate are different. It has been known. Particularly, when an undoped, that is, an O 3 TEOS film containing no impurities is formed on the thermal oxide film, the dependency on the base is large. It is desirable to form a non-doped silicon dioxide film in order to reduce the auto-doping to the diffusion layer or the like when the underlying groove is buried and planarized, but such a non-doped silicon dioxide film is formed by the O 3 TEOS technique. When obtaining the above, the problem of the above-mentioned background dependency is large.
【０００６】ＴＥＯＳに限らず、その他の有機シリコン
系化合物とオゾンとにより絶縁膜を形成する場合にも同
様な問題が生じる。The same problem arises not only when using TEOS but also when forming an insulating film with other organic silicon compounds and ozone.
【０００７】この点に鑑みて本発明は者は、Ｎ系ガスで
プラズマ処理する方法を提案した。これによって熱酸化
膜表面の親水性を低減することで下地依存性の無い良質
なかつ安定な平坦化絶縁膜の形成が可能となった。In view of this point, the present inventor has proposed a method of performing plasma treatment with an N-based gas. As a result, by reducing the hydrophilicity of the surface of the thermal oxide film, it becomes possible to form a high-quality and stable flattening insulating film that does not depend on the underlying layer.
【０００８】しかし、この方法は効果があるもののプラ
ズマ処理による改質に頼っているために表面の処理効果
の時間依存性があり、安定な処理層を形成できるとは言
いがたい。従って長時間にわたって安定な処理層を形成
する技術が切望されている。However, although this method is effective, it cannot be said that a stable treatment layer can be formed because the treatment effect on the surface depends on time because it depends on modification by plasma treatment. Therefore, a technique for forming a stable treatment layer over a long period of time has been earnestly desired.
【０００９】本発明は上記問題点に鑑みてなされたもの
で、本発明の目的は、有機シリコン系化合物とオゾンと
の反応により絶縁膜を形成する場合も下地依存性が小さ
く、良質で安定な平坦化絶縁膜の成膜を実現できる半導
体装置の製造方法を提供することにある。The present invention has been made in view of the above problems, and an object of the present invention is to provide a high quality and stable surface resistance even when an insulating film is formed by a reaction between an organosilicon compound and ozone. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of realizing the formation of a planarization insulating film.
【００１０】[0010]
【課題を解決するための手段及び作用】本発明者は、上
述の目的を達成する為に鋭意検討を行なう過程で、下地
依存性を低減する方法を見いだした。段差を有する基体
上に熱酸化膜を形成する熱酸化膜形成工程と、熱酸化膜
の表面に疎水性で付与するイオン注入処理をする工程
と、有機シリコン系化合物とオゾンとの反応により基体
上に平坦化絶縁膜を形成する平坦化絶縁膜形成工程とを
含むことを特徴とする半導体装置の製造方法であって、
この構成により上記目的を達成したものである。Means and Actions for Solving the Problems The inventors of the present invention have found a method of reducing the dependency on the groundwork in the course of earnestly studying to achieve the above object. A thermal oxide film forming step of forming a thermal oxide film on a substrate having a step, a step of performing an ion implantation process for imparting hydrophobicity to the surface of the thermal oxide film, and a step of reacting an organosilicon compound with ozone on the substrate A method of manufacturing a semiconductor device, comprising: a flattening insulating film forming step of forming a flattening insulating film on
This configuration achieves the above object.
【００１１】本発明は、例えば常圧及び中圧Ｏ3 ＴＥ
ＯＳ成長技術等の有機シリコン系化合物とオゾンとの反
応により絶縁膜を得る平坦化絶縁膜の形成において、成
膜前にＳｉ，Ｎ，Ｐ，Ｂ，Ａｓ等のイオンを基体の熱酸
化膜表面にイオン注入を行なう構成で実施できる。The present invention is applicable, for example, to normal and medium pressure O 3 TE.
In forming a flattening insulating film for obtaining an insulating film by reacting an organic silicon compound with ozone such as OS growth technology, before forming a film, ions of Si, N, P, B, As, etc. are added to the surface of the thermal oxide film of the substrate. It can be implemented in a configuration in which ion implantation is performed.
【００１２】[0012]
【実施例】以下に、本発明に係わる各発明の実施例につ
いて、図面を参照して説明する。但し当然の事である
が、各発明は以下に述べる実施例により限定されるもの
ではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of each invention relating to the present invention will be described below with reference to the drawings. However, as a matter of course, each invention is not limited to the examples described below.
【００１３】（実施例−１）この実施例は、半導体集積
回路製造の際に、段差を有する基体であるシリコン半導
体ウエハ上に平坦化絶縁膜を形成して、半導体装置を得
る場合に本発明を適用したものである。(Embodiment 1) In this embodiment, a semiconductor device is obtained by forming a flattening insulating film on a silicon semiconductor wafer which is a substrate having a step during the manufacture of a semiconductor integrated circuit. Is applied.
【００１４】本実施例においては、溝（トレンチ）２１
が形成されていることにより段差２を有する下地となっ
ている半導体基板としてのシリコン基板１上に熱酸化膜
３を形成して図１（Ａ）の構造とし（熱酸化膜形成工
程）、次いで図１（Ａ）の構造の状態で熱酸化膜３の表
面にＳｉをイオン注入を行ない、Ｓｉ含有率の高い図１
（Ｂ）の熱酸化膜層を形成する（イオン注入処理）。次
いで、有機シリコン系化合物（ここではＴＥＯＳを使
用）とオゾンとの反応によりシリコン基板１上に平坦化
絶縁膜４を形成して図１（Ｃ）の構造にする（平坦化絶
縁膜形成工程）。この実施例では、Ｏ3 ＴＥＯＳ膜は
シリコン基板１の全面（絶縁膜を要する部分付近の全
面）に形成した。かつ、本実施例は溝２１の埋め込みに
この発明を適用したので、平坦化絶縁膜４の溝２１以外
の余分な部分を除去して、図１（Ｃ）に示す埋め込み平
坦化構造を得た。In this embodiment, the groove 21 is formed.
The thermal oxide film 3 is formed on the silicon substrate 1 as a semiconductor substrate which is a base having the step 2 due to the formation of the thermal oxide film to form the structure of FIG. 1A (thermal oxide film forming step), and Si is ion-implanted on the surface of the thermal oxide film 3 in the state of the structure of FIG.
The thermal oxide film layer of (B) is formed (ion implantation process). Then, the planarizing insulating film 4 is formed on the silicon substrate 1 by the reaction between the organosilicon compound (TEOS is used here) and ozone to form the structure of FIG. 1C (planarizing insulating film forming step). .. In this example, the O 3 TEOS film was formed on the entire surface of the silicon substrate 1 (the entire surface in the vicinity of the portion requiring the insulating film). In addition, since the present invention is applied to the filling of the groove 21 in the present embodiment, the excess portion of the flattening insulating film 4 other than the groove 21 is removed to obtain the buried flattening structure shown in FIG. 1C. ..
【００１５】更に詳しくは、本実施例は次のように具体
的に実施した。まずシリコン基板１に、溝２１を形成す
る。これは常用の加工手段、代表的にはレジストプロセ
ス等のフォトリソグラフィー技術を採用できる。これに
よりシリコントレンチパターンを形成する。More specifically, this embodiment was carried out concretely as follows. First, the groove 21 is formed in the silicon substrate 1. This can employ a conventional processing means, typically a photolithography technique such as a resist process. Thereby, a silicon trench pattern is formed.
【００１６】次いで、内壁を酸化して、熱酸化膜３を有
する図１（Ａ）の構造を得る。これが熱酸化膜形成工程
である。Then, the inner wall is oxidized to obtain the structure of FIG. 1A having the thermal oxide film 3. This is the thermal oxide film forming step.
【００１７】次に、本実施例では、Ｓｉを用いて、イオ
ン注入を行なった。このときのＳｉのイオン注入条件
は、下記の通りとした。Next, in this embodiment, ion implantation was performed using Si. The Si ion implantation conditions at this time were as follows.
【００１８】 イオン注入条件 ソースガス ＳｉＦ4 加速電圧 １０ ［ｋｅｖ］ ドーズ量 １×１０18［ｃｍ-3］ これがイオン注入処理工程である。これにより表面のＳ
ｉ／Ｏ比が上がり、親水性が落ちると考えられる。Ion implantation conditions Source gas SiF 4 acceleration voltage 10 [kev] Dose amount 1 × 10 18 [cm −3 ] This is the ion implantation treatment step. This allows the surface S
It is considered that the i / O ratio increases and the hydrophilicity decreases.
【００１９】次に、中圧Ｏ3−ＴＥＯＳ層を形成し、Ｓ
ｉＯ2を主成分とする平坦化絶縁膜４を形成した。形成
条件は下記のとおりとした。これが平坦化絶縁膜形成の
工程である。これにより図１（Ｂ）の構造を得た。Next, a medium pressure O 3 -TEOS layer is formed and S
The planarization insulating film 4 containing iO 2 as a main component was formed. The formation conditions were as follows. This is the step of forming the planarization insulating film. As a result, the structure shown in FIG. 1 (B) was obtained.
【００２０】この平坦化絶縁膜の形成条件は、下記の通
りである。The conditions for forming this flattening insulating film are as follows.
【００２１】 平行平板ＣＶＤ装置 ＴＥＯＳガス流量 ：３０００ｓｃｃｍ（Ｈｅバブリ
ング） Ｏ3ガス流量 ：３０００ｓｃｃｍ（８％ｉｎ
Ｏ2） 圧力 ：７９８００［Ｐａ］（６００
［Ｔｏｒｒ］） 温度 ：３９０℃ 次いで、本実施例では、レジストプロセス等を併用し埋
め込み平坦化を行なうためにＯ3−ＴＥＯＳ技術により
形成された平坦化絶縁膜４のうちの余分なＳｉＯ2を除
去し、埋込み部４１のみを残した図１（Ｃ）の埋め込み
構造を得た。Parallel plate CVD apparatus TEOS gas flow rate: 3000 sccm (He bubbling) O 3 gas flow rate: 3000 sccm (8% in)
O 2 ) Pressure: 79800 [Pa] (600
[Torr]) Temperature: 390 ° C. Then, in the present embodiment, the excess SiO 2 of the O 3 -TEOS planarization insulating film formed by a technique 4 to perform a combination embedded planarize the resist process and the like A buried structure shown in FIG. 1C was obtained, in which only the buried portion 41 was left after the removal.
【００２２】本実施例では、この発明をトレンチ埋め込
みプロセスに応用したがその他例えば下地依存性の発生
する層間平坦化にも応用できる。尚本発明は本実施例条
件に限ることなく本発明の構成の要旨に反しない限り適
宜変更可能なことはいうまでもない。In this embodiment, the present invention is applied to the trench burying process, but it can also be applied to other interlayer flattening where, for example, an underlayer dependency occurs. Needless to say, the present invention is not limited to the conditions of this embodiment, and can be changed as appropriate without departing from the spirit of the constitution of the present invention.
【００２３】（実施例−２）本実施例では、実施例−１
と異なるイオン種について具体化して実施したものであ
る。Example-2 In this example, Example-1 is used.
It was carried out by embodying different ion species.
【００２４】本実施例は、溝（トレンチ）２１が形成さ
れていることにより段差２を有する下地となっている。
シリコン基板１上に熱酸化膜３を形成して図２（Ａ）に
示す構造とした（熱酸化膜形成工程）。次いで、熱酸化
膜表面にリン（Ｐ）イオン注入処理を行ない、図２
（Ｂ）に示す構造とした。（ここではリンイオンソース
としてＰＦ3を使用、ドープしたい不純物に応じその他
ＢＦ3などの各種ソースガスを適宜用いて良い。）次
に、有機シリコン系化合物（ここではＴＥＯＳを使用）
とオゾンの反応によりシリコン基板１上にここでは所要
部分付近全面に平坦化絶縁膜５を形成して図２（Ｃ）の
構造を得る（平坦化絶縁膜形成工程）。In this embodiment, since the groove (trench) 21 is formed, the base has the step 2.
A thermal oxide film 3 was formed on the silicon substrate 1 to form the structure shown in FIG. 2A (thermal oxide film forming step). Then, a phosphorus (P) ion implantation process is performed on the surface of the thermal oxide film, as shown in FIG.
The structure shown in FIG. (Here, PF 3 is used as the phosphorus ion source, and various source gases such as BF 3 may be appropriately used depending on the impurities to be doped.) Next, an organosilicon compound (TEOS is used here)
By the reaction of ozone with ozone, the flattening insulating film 5 is formed on the entire surface of the silicon substrate 1 in the vicinity of a required portion here, and the structure of FIG. 2C is obtained (flattening insulating film forming step).
【００２５】本実施例においても、平坦化絶縁膜５の溝
２１以外の部分は除去して溝２１の埋め込み部４１のみ
残すようにした。更に詳しくは本実施例は次の具体的に
実施した。Also in this embodiment, the flattening insulating film 5 except for the groove 21 is removed so that only the embedded portion 41 of the groove 21 is left. More specifically, this example was carried out specifically as follows.
【００２６】まず、シリコン基板１に溝２１を形成す
る。これは常用の加工手段、代表的にはレジストプロセ
スのフォトリソグラフィー技術を採用できる。これによ
りシリコントレンチパターンを形成する。次いで内壁を
酸化して熱酸化膜３を有する図２（Ａ）に示す構造を得
る。これが熱酸化膜形成工程である。First, the groove 21 is formed in the silicon substrate 1. This can employ a conventional processing means, typically a photolithography technique of a resist process. Thereby, a silicon trench pattern is formed. Then, the inner wall is oxidized to obtain the structure shown in FIG. 2A having the thermal oxide film 3. This is the thermal oxide film forming step.
【００２７】次に図２（Ｂ）に示したようにＰＳＧ，Ｂ
ＰＳＧ等のドープトＳｉＯ2膜をイオン注入法により形
成する。この実施例では形成条件は次の通りとした。Next, as shown in FIG. 2B, PSG, B
A doped SiO 2 film such as PSG is formed by an ion implantation method. In this example, the forming conditions were as follows.
【００２８】 イオン注入条件 ソースガス ＰＦ3 加速電圧 １０ ［ｋｅｖ］ ドーズ量 １×１０18［ｃｍ-3］ 注入層厚は、５〜１００ｎｍと内壁酸化膜厚により適宜
変更した。これがイオン注入処理における表面の疎水化
処理工程である。これにより、表面のＰ含有率が増加し
親水性が落ちると考えられる。次いで、本実施例では中
圧Ｏ3−ＴＥＯＳ絶縁膜を形成する。これが、平坦化絶
縁膜形成工程である。これにより図２（Ｃ）の構造を得
た。Ion implantation conditions Source gas PF 3 Acceleration voltage 10 [kev] Dose amount 1 × 10 18 [cm −3 ] The implantation layer thickness was appropriately changed to 5 to 100 nm and the inner wall oxide film thickness. This is the surface hydrophobizing process in the ion implantation process. This is considered to increase the P content on the surface and reduce the hydrophilicity. Next, in this embodiment, a medium pressure O 3 -TEOS insulating film is formed. This is the planarization insulating film forming step. As a result, the structure of FIG. 2 (C) was obtained.
【００２９】層間絶縁膜の形成条件は、下記の通りであ
る 平行平板ＣＶＤ装置 ＴＥＯＳガス流量：３０００ｓｃｃｍ（Ｈｅバブリン
グ） Ｏ3ガス流量 ：３０００ｓｃｃｍ（８％ｉｎ
Ｏ2） 圧力 ：７９８００［Ｐａ］（６００［Ｔｏ
ｒｒ］） 温度 ：３９０℃ 本実施例では表面濃度を出来るだけ上げるためにインプ
ラ後のアニールは行なわなかった。必要が有れば平坦化
絶縁膜５を形成した後に９００℃３０分程度のＮ2雰囲
気で熱処理を行えばよい。次いで本実施例では、レジス
トプロセス等を併用し埋め込み平坦化を行なうためにＯ
3−ＴＥＯＳ技術により形成された平坦化絶縁膜５のう
ち余分なＳｉＯ2を除去し、埋め込み部５１のみを残し
た図２（Ｄ）の埋め込み構造を得た。The conditions for forming the interlayer insulating film are as follows: parallel plate CVD apparatus TEOS gas flow rate: 3000 sccm (He bubbling) O 3 gas flow rate: 3000 sccm (8% in
O 2 ) Pressure: 79800 [Pa] (600 [To
rr]) Temperature: 390 ° C. In this example, annealing after implantation was not performed in order to increase the surface concentration as much as possible. If necessary, heat treatment may be performed in the N 2 atmosphere at 900 ° C. for about 30 minutes after forming the planarization insulating film 5. Next, in this embodiment, in order to carry out buried planarization using a resist process and the like,
Excessive SiO 2 was removed from the planarization insulating film 5 formed by the 3- TEOS technique, and a buried structure of FIG. 2D was obtained in which only the buried portion 51 was left.
【００３０】本実施例では、この発明をトレンチ埋め込
みプロセスに応用したがその他例えば下地依存性の発生
する層間平坦化にも応用できる。尚本発明は本実施例条
件に限ることなく本発明の主旨に反しない限り適宜変更
可能な事は言うまでもない。In the present embodiment, the present invention is applied to the trench filling process, but it can also be applied to other interlayer flattening in which, for example, the underlying dependency occurs. Needless to say, the present invention is not limited to the conditions of this embodiment, and can be changed as appropriate without departing from the spirit of the present invention.
【００３１】[0031]
【発明の効果】以上の説明から明らかなように、本発明
は、基体の熱酸化膜の表面に疎水性を付与するイオン注
入処理を行なうことで、表面が改質され、成膜の下地依
存性が低減される。本発明により、有機シリコン系化合
物とオゾンとの反応により絶縁膜を形成する場合も下地
依存性のない良質なかつ安定な平坦化絶縁膜の形成が可
能となる。As is apparent from the above description, according to the present invention, the surface of the thermal oxide film of the substrate is subjected to the ion implantation treatment for imparting hydrophobicity, so that the surface is modified and the film formation depends on the substrate. Sex is reduced. According to the present invention, even when an insulating film is formed by the reaction of an organosilicon compound and ozone, it is possible to form a high-quality and stable flattening insulating film that does not depend on the underlying layer.
【図１】本発明の実施例−１の工程を示す断面図。FIG. 1 is a sectional view showing a process of a first embodiment of the present invention.
【図２】実施例−２の工程を示す断面図。FIG. 2 is a cross-sectional view showing a process of Example-2.
１…シリコン基板、２…段差、３…熱酸化膜、４…平坦
化絶縁膜、２１…溝、４１…埋込み部。1 ... Silicon substrate, 2 ... Step, 3 ... Thermal oxide film, 4 ... Flattening insulating film, 21 ... Groove, 41 ... Embedded part.
Claims (2)
する工程と、 前記熱酸化膜にイオン注入を施し、該熱酸化膜表面を改
質する工程と、 有機シリコン化合物とオゾンとの反応により基板上に平
坦化絶縁膜を形成する工程と、を備えたことを特徴とす
る半導体装置の製造方法。1. A step of forming a thermal oxide film on a surface of a substrate having a step, a step of implanting ions into the thermal oxide film to modify the surface of the thermal oxide film, and a reaction between an organosilicon compound and ozone. And a step of forming a planarization insulating film on the substrate by using the method described above.
化するイオンを用いる請求項１記載の半導体装置の製造
方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the ion implantation uses ions that make the surface of the thermal oxide film hydrophobic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28526991A JPH05129280A (en) | 1991-10-31 | 1991-10-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28526991A JPH05129280A (en) | 1991-10-31 | 1991-10-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129280A true JPH05129280A (en) | 1993-05-25 |
Family
ID=17689318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28526991A Pending JPH05129280A (en) | 1991-10-31 | 1991-10-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129280A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766131A (en) * | 1993-08-24 | 1995-03-10 | Canon Sales Co Inc | Film deposition method |
| JPH09205146A (en) * | 1995-12-29 | 1997-08-05 | Hyundai Electron Ind Co Ltd | Method for forming metal wiring protective film of semiconductor element |
| US6797605B2 (en) * | 2001-07-26 | 2004-09-28 | Chartered Semiconductor Manufacturing Ltd. | Method to improve adhesion of dielectric films in damascene interconnects |
| KR100561301B1 (en) * | 2004-11-04 | 2006-03-15 | 동부아남반도체 주식회사 | Method for producing semiconductor |
| KR20140048385A (en) * | 2012-10-11 | 2014-04-24 | 세메스 주식회사 | Apparatus and method fdr treating substrates |
| CN111599869A (en) * | 2020-05-27 | 2020-08-28 | Tcl华星光电技术有限公司 | Thin film transistor and thin film transistor preparation method |
-
1991
- 1991-10-31 JP JP28526991A patent/JPH05129280A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766131A (en) * | 1993-08-24 | 1995-03-10 | Canon Sales Co Inc | Film deposition method |
| JP2500130B2 (en) * | 1993-08-24 | 1996-05-29 | キヤノン販売株式会社 | Film formation method |
| JPH09205146A (en) * | 1995-12-29 | 1997-08-05 | Hyundai Electron Ind Co Ltd | Method for forming metal wiring protective film of semiconductor element |
| US6797605B2 (en) * | 2001-07-26 | 2004-09-28 | Chartered Semiconductor Manufacturing Ltd. | Method to improve adhesion of dielectric films in damascene interconnects |
| KR100561301B1 (en) * | 2004-11-04 | 2006-03-15 | 동부아남반도체 주식회사 | Method for producing semiconductor |
| KR20140048385A (en) * | 2012-10-11 | 2014-04-24 | 세메스 주식회사 | Apparatus and method fdr treating substrates |
| CN111599869A (en) * | 2020-05-27 | 2020-08-28 | Tcl华星光电技术有限公司 | Thin film transistor and thin film transistor preparation method |
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