KR100611115B1 - Spin-on glass composition and method of forming a silicon oxide layer in semiconductor manufacturing process using the same - Google Patents

Abstract

According to the spin-on-glass composition having excellent flattening of the stepped portion and the void-free spin-on-glass composition and the silicon oxide film forming method using the same, the structural formula is-(SiH ₂ NH) _n- ( _wherein , n is a positive integer) and a spin on glass composition comprising polysilazane having a weight average molecular weight of 3,300 to 3,700 is applied to form a flat spin on glass film. The spin-on-glass film is cured and converted into a flat silicon oxide film.

Description

SPON-ON GLASS COMPOSITION AND METHOD OF FORMING A SILICON OXIDE LAYER IN SEMICONDUCTOR MANUFACTURING PROCESS USING THE SAME}

1 is a cross-sectional view of an oxide film formed on an inner wall of a trench when the spin-on glass film is baked by one heat treatment step.

2 is a graph for explaining the relationship between the viscosity and the shear rate of the spin-on glass composition of the present invention.

3A to 3K are cross-sectional views illustrating a method of forming a silicon oxide film in a semiconductor device according to an embodiment of the present invention.

4 is an FT-IR chart showing light absorbance measured after prebaking a spin-on glass film.

Fig. 5 is an FT-IR chart showing the light absorption of the silicon oxide film measured after the main baking of the spin-on glass film.

6A to 6G are graphs illustrating etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film by a conventional CVD method.

7A to 7G are cross-sectional views illustrating a shallow trench device isolation method according to still another embodiment of the present invention.

8 is a bar graph showing the standard intensity of light absorbance obtained by performing FT-IR analysis on silicon oxide formed in the active region of the substrate according to the present invention.

9 is a graph showing the etching rate of the silicon oxide film formed according to the present invention according to the type of etching solution.

10 is a graph showing polishing uniformity after polishing a silicon oxide film formed according to a second embodiment of the present invention and a silicon oxide film formed by a high density plasma chemical vapor deposition method by a chemical mechanical polishing method.

11 is a flowchart illustrating a method of forming an oxide film using the spin-on glass composition according to an embodiment of the present invention.

12 is a graph showing the FT-IR results according to the main baking temperature having a water vapor concentration of 80% according to an embodiment of the present invention

13 is a graph showing the FT-IR results according to the main baking temperature having a water vapor concentration of 10% or less according to an embodiment of the present invention.

14 is a graph showing the FT-IR results according to the atmosphere of the main baking according to an embodiment of the present invention.

15 is a graph showing the molecular weight distribution of the spin on glass composition according to the weight average molecular weight (Mw) according to an embodiment of the present invention.

Figure 16 is a graph showing the viscosity of the spin-on glass composition according to the weight average molecular weight (Mw) according to an embodiment of the present invention.

17 is a graph showing the concentration of the spin-on-glass solids content (% by weight) according to the middle average molecular weight (Mw) according to an embodiment of the present invention.

18A to 18K are cross-sectional views illustrating a method of forming a silicon oxide film of a semiconductor device according to another embodiment of the present invention.

19 is a graph showing the number of particles (pieces / cc) according to a weight average molecular weight (Mw) according to an embodiment of the present invention.

20 is a graph showing light absorption (au) according to wave number (cm ⁻¹ : wave number) after preliminary baking according to an embodiment of the present invention.

21 is a graph showing the light absorbance (au) according to the weight average molecular weight (Mw) and wave number (cm ⁻¹ ) after the main baking according to an embodiment of the present invention.

22 is a graph showing the thickness and shrinkage rate according to the weight average molecular weight after pre-baking and main baking according to an embodiment of the present invention.

FIG. 23 is a graph illustrating Within Wafer Non-Uniformity (WIWNU) according to a weight average molecular weight according to an embodiment of the present invention. FIG.

24 is a graph showing the number of standard particles and scratches according to the weight average molecular weight according to one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100, 200: semiconductor substrate 12, 118, 210: trench

13: first spin-on-glass film 13a: first silicon oxide film

14, 130, 214, 216: silicon oxide film 16: gate oxide film

20: n-type semiconductor region 22: photoresist pattern

24Ga, 24Gb, 24Gc, 24GWL: gate electrode 25: p-type impurity region

24a: polysilicon pattern 24b: tungsten silicide pattern

24c: tungsten pattern 24d: silicon nitride pattern

26, 27: n-type impurity region 30: p-type well

32 silicon nitride film 32a spacer

40: n-type well 42, 44: impurity region

50: second spin-on-glass film 50a: second silicon oxide film

52 metal layer patterns 54 third spin-on-glass film

54a: Third silicon oxide film 112, 202: Pad oxide film pattern

114: nitride film pattern 116: high temperature oxide film pattern

120, 212: trench inner wall oxide film 201: pad oxide film

203: polishing stopper film 204: polishing stopper film pattern

205: hard mask layer 206: hard mask pattern

213: spin on glass film

The present invention relates to a spin on glass (SOG) composition for forming a silicon oxide film in a semiconductor manufacturing process and a method for forming a silicon oxide film using the same. More specifically, the present invention relates to a spin-on-glass composition comprising polysilazane and a method of forming a silicon oxide film of a semiconductor device using the same.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In particular, in terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to these demands, semiconductor technologies have been developed in the direction of improving the degree of integration, reliability and response speed.

In general, integrated circuits are manufactured by forming many active elements on a single substrate. After each device is formed and insulated, certain devices are electrically connected to one another during the manufacturing process to achieve the desired circuit functionality. For example, MOS, bipolar VLSI and ULSI devices have a multilevel interconnection structure in which a large number of devices are electrically connected to each other. In such an interconnect structure, the topography of the top layer becomes more curved as the number of films increases.

For example, a method of manufacturing a semiconductor wafer in which two or more metal layers are formed is as follows. A plurality of oxide films, polycrystalline silicon conductive films and first metal wiring films are formed on the semiconductor wafer. A first insulating film is then formed on the semiconductor product. Via holes are formed in the first insulating film to provide a circuit path to the second metal wiring film. At this time, since the films under the first insulating film are not flat, the surface of the first insulating film is not flat either. When the second metal wiring film is directly formed on the first insulating film, cracks occur in the second metal wiring film due to the protrusions or cracks in the first insulating film. Moreover, if the deposition rate of the metal film becomes poor, the production yield of the semiconductor element will decrease. Therefore, in general, in a multilevel metal interconnection, the insulating film is planarized before the via or the second metal wiring layer is formed.

Various methods for planarizing the insulating film have been developed. These methods include using a BPSG (Borophosphorous Silicate Glass) film or spin-on glass (SOG) film having excellent reflow characteristics, or a chemical mechanical polishing (CMP) method. In general, a method using BPSG has been widely used as an insulating film for filling gaps between metal lines. However, the process of depositing BPSG has the problem of first relying on setting specific deposition parameters for the equipment used. In addition, the gases used in the process are not only expensive but also highly toxic.

Moreover, as the degree of integration increases and the design rule decreases, when the interlayer insulating film is formed by using BPSG to fill the gap between wirings to manufacture VLSIs of 256 mega DRAM or more, due to the formation of bridges by void generation, Yield may be degraded or the etch stop layer used in subsequent processes may be damaged. Therefore, to solve this problem, it is necessary to perform additional reflow process and expensive CMP process.

On the other hand, the process of forming an insulating film using an SOG film is widely known as a process which can form a flat insulating film by simple coating. For example, US Pat. No. 5,310,720 (issued to Shin et al) discloses a method of forming a polysilazane layer and then converting the polysilazane layer into a silicon oxide film by firing it under an oxygen atmosphere. In addition, US Patent No. 5,976,618 (issued to Shunichi Fukuyama et al.) Discloses a method of depositing an inorganic SOG and then converting it into a silicon oxide film through a two-step heat treatment process.

The polysilazane-based SOG composition has a basic skeleton composed of Si-N, Si-H, and N-H bonds. Baking in an atmosphere containing oxygen and water replaces the Si—N bond with a Si—O bond. The method of converting the silicon oxide film using the SOG composition can be performed by a simple spin coating method and a curing process, which has the advantage of reducing the cost.

However, it is known that not all Si-N bonds are substituted with Si-O bonds (see Japanese Patent Laid-Open No. 11-145286). Therefore, since the silicon oxide film has insulation and electrical characteristics different from that of a pure silicon oxide film formed using a BPSG film or a TEOS film, there is a problem in using the silicon oxide film as an insulating film. Furthermore, since the SOG film is formed by spin coating, the thickness of the formed silicon oxide film is not sufficient, so that it is impossible to completely cover the conductive layers such as the gate electrode and the metal wiring film.

In order to solve this problem, the present inventors can fill the gap between VLSI-class metal wirings having a high aspect ratio, fill the gap of the substrate without going through the mechanical planarization process, and smoothly uneven the surface of the substrate. To develop a spin-on-glass composition comprising perhydropolysilazane capable of producing an oxide film having substantially the same characteristics as the oxide film by chemical vapor deposition, and was incorporated in US Patent Application No. 09 / 686,624 (corresponds to Korean Patent Application No. 2000-59635, which is a priority claim of Korean Patent Application No. 2000-23448) There is a bar.

According to the method disclosed, the structural formula is-(SiH ₂ NH ₂ ) _n- (wherein n is a positive integer) on a substrate having a stepped portion, the weight average molecular weight is 4000 to 8000, and the molecular weight distribution is By applying and curing the SOG solution containing polysilazane of 3.0 to 4.0, a silicon oxide film having a flat surface can be formed.

Examples of the silicon oxide film include an isolation layer of an STI structure formed on a semiconductor substrate having grooves and step portions formed by protrusions for forming an isolation structure having a shallow trench isolation (STI) structure.

The curing step consists of a prebaking step and a main baking step. The prebaking is carried out at a temperature of about 100 to 500 ° C., preferably at about 100 to 400 ° C. for about 1 to 5 minutes, preferably about 2 to 3 minutes, and the main baking is performed at a temperature of about 900 to 1,050 ° C. .

Here, the formed silicon oxide film has excellent gap-filling characteristics for the STI structure including a gap of 0.1 to 1 mu m. However, according to the wet etching rate test, the etching rate decreases as the temperature of the main baking increases, and there is a problem that the silicon oxide film is formed on the silicon substrate surface portion and the active region.

1 is a cross-sectional view of an oxide film formed on a trench inner surface. The semiconductor device shown in FIG. 1 is manufactured by the following method. A pad oxide film is formed on the silicon substrate 100, and a nitride film and a high temperature oxide film are sequentially formed on the pad oxide film. The nitride film serves as an etch stop layer in a subsequent CMP process, and the high temperature oxide film serves as a hard mask layer.

Subsequently, by forming silicon nitride oxide (SiON) on the high temperature oxide film, an antireflection film (not shown) is formed, and a high temperature oxide film pattern 116 for defining an active pattern is formed by performing a photolithography process.

The nitride layer pattern and the pad oxide layer are sequentially etched using the high temperature oxide layer pattern 116 as an etching mask to form the nitride layer pattern 114 and the pad oxide layer pattern 112. The trench 118 is formed by etching the upper portion of the substrate adjacent to the nitride layer pattern.

Subsequently, in order to cure damage to silicon due to high energy ion implantation during the trench etching process, the exposed portion of the trench 118 is heat treated in an oxygen atmosphere. At this time, the trench inner wall oxide film 120 is formed in the trench including the bottom and side surfaces of the trench by an oxidation reaction between the oxidant and the exposed silicon.

While the trench 118 is filled with the SOG composition proposed by the applicant, the SOG composition is deposited on the semiconductor substrate 100 to form an SOG film. Next, the SOG film is baked. The prebaking is carried out at a temperature of about 100 to 500 ° C., preferably about 100 to 400 ° C. for about 1 to 5 minutes, preferably about 2 to 3 minutes. The main baking is performed at a temperature of about 900 to 1,050 캜 to form a silicon oxide film. As a result, as shown in FIG. 1, an oxide layer 130 filling the trench is formed. The oxide film 130 is formed from an SOG film. At this time, as shown by the circle in FIG. 1, it can be confirmed that the oxide film on the sidewall portion of the trench inner wall oxide film 120 is thicker than the oxide film on the bottom portion. The oxide forming the oxide film is estimated to be formed by the oxidation reaction of silicon in the semiconductor substrate 100 and oxygen contained in the oxidizing gas when the SOG film is cured at an oxidizing atmosphere at 1000 ° C. or higher.

The formation of such oxides may cause morphological defects in the trenches such as grooves after the CMP process, or may change the size of the active region.

In addition, the present applicant can fill the gap between the metal wiring of the VLSI having a high aspect ratio, fill the gap of the substrate without going through the mechanical planarization process, and smooth the irregularities of the surface of the substrate to chemical vapor deposition A spin-on-glass composition comprising perhydropolysilazane capable of producing an oxide film having substantially the same characteristics as the oxide film by the present invention was developed and disclosed in US Patent Application No. 09 / 985,615 to October 24, 2002 (METHOD OF FORMING SILICON OXIDE LAYER IN SEMICONDUCTOR MANUFACTURING PROCESS USING SPIN-ON GLASS COMPOSITION AND ISOLATION METHOD USING THE SAME METHOD (corresponding to Korean Patent Application No. 2001-31633). .

Accordingly, an object of the present invention is to provide a spin-on-glass composition which has a high degree of integration and is capable of filling gaps between metal wirings which are arranged very closely in a semiconductor device having a high aspect ratio.

Another object of the present invention is to provide a composition capable of smoothing unevenness of the substrate surface and filling gaps without a mechanical planarization process.

It is still another object of the present invention to provide a spin-on glass composition having substantially the same characteristics as an oxide film of a semiconductor device produced by a chemical vapor deposition method.

Still another object of the present invention is to provide a method of forming an oxide film in a semiconductor manufacturing process using the spin-on glass composition described above.

In order to achieve the above object of the present invention, a preferred embodiment of the present invention is a structural formula-(SiH ₂ NH) _n- (where n is a positive integer), the weight average molecular weight is about 3,000 to 6,000 And 10 to 30% by weight of polysilazane and about 70 to 90% by weight of a solvent.

In order to achieve the another object of the present invention described above, according to the oxide film forming method according to a preferred embodiment of the present invention, the structural formula on the semiconductor substrate having a stepped portion on the upper surface is-(SiH ₂ NH) _n- , n is a positive integer), spin-on-glass by applying a spin-on-glass composition comprising a weight average molecular weight of about 3,000 to 6,000, 10 to 30% by weight of polysilazane and about 70 to 90% by weight of solvent To form a film. The spin-on-glass film is cured to form a silicon oxide film.

According to various embodiments of the present invention, there is substantially no void using a spin-on glass composition having an aspect ratio of about 5: 1 to 10: 1 or a conductive film having a high surface discontinuity. A uniform silicon oxide film can be formed.

Hereinafter, a spin-on-glass composition and a method of forming an oxide film in a semiconductor device using the same according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is not limited.

When a material or film or structure is referred to herein as being deposited or formed on another material or film or layer, this may also mean that another layer, material or structure is formed therebetween.

The spin-on glass composition of the present invention is disclosed in U.S. Patent Application Serial No. 09 / 686,624, preferably the structural formula is-(SiH ₂ NH ₂ ) _n- (wherein n is a positive integer) and weight Polysilazanes having an average molecular weight of 4,000 to 8,000 and a molecular weight distribution of 3.0 to 4.0. In the description of the present invention, the molecular weight distribution diagram means the ratio of the weight average molecular weight and the number average molecular weight.

Processes for producing polysilazane are known. In a typical method, polysilazane is prepared by reacting a complex compound resulting from the reaction of a halosilane and a Lewis base with ammonia.

Or a method of synthesizing polysilazane by reacting a silicon halide such as SiCl ₄ or SiH ₂ Cl ₂ with an amine, a method of converting silazane to polysilazane using an alkali metal halide catalyst, a transition metal complex compound (transition Polysilazane may be prepared by dehydrogenation of a silane compound with an amine compound using a complex metal compound.

US Pat. No. 5,494,978 issued to Yasuo Shinizu et al. Discloses a process for preparing defoamed polysilazanes using inorganic polysilazanes having a number average molecular weight of 100 to 100,000. In addition, US Pat. No. 5,905,130 (issued to Hirohiko Nakahara et al.) Discloses a reaction between a polyaminosilane compound and a polyhydrogenated nitrogen-containing compound under a base catalyst, or a polyhydrogenated silicon compound. A method for producing polysilazane is disclosed by reacting a polyhydrogenated silicone compound with a polyhydrogenated nitrogen-containing compound in the presence of a basic solid oxide catalyst.

In addition, US Pat. No. 5,436,398 (issued to Yasuo Shimizu et al.) Discloses the preparation of perhydro polysilazane having a number average molecular weight of 1,120, US Pat. No. 4,937,304 (issued to Ayama et al.) And No. 4,950,381 (issued to Takeuchi et al.) Discloses a process for preparing polysilazanes with the desired molecular weight.

There is no particular limitation on the method for producing the polysilazane used in the present invention. By the method mentioned above, polysilazane can be manufactured easily. Perhydro polysilazane prepared by the above-mentioned known method is classified and used by fractionation according to molecular weight so that it can be used in the present invention.

When the weight average molecular weight of the polysilazane used in the present invention is less than 4,000, outgassing increases, and the small hydrophobic molecular weight rapidly converts the perhydro polysilazane into silicon oxide, causing cracking. On the contrary, when the weight average molecular weight exceeds 8,000, the viscosity of the SOG composition solution increases, thereby decreasing the uniformity of the spin-on-glass film produced during coating. Therefore, the weight average molecular weight of the perhydro polysilazane used in the present invention is 4,000 to 8,000. More specifically, when the SOG film filling the trench is formed, the weight average molecular weight of the perhydro polysilazane is preferably 6,000 to 8,000, more preferably 6,500 to 7,000.

In another embodiment, if the perhydro polysilazane used in the present invention has a weight average molecular weight of less than 3,000, outgassing increases and the degassed SiH ₄ reacts with oxygen gas to produce particles such as SiO _2. This is formed to contaminate the reaction chamber. The particles contaminate the wafer in a subsequent process. On the other hand, if the weight average molecular weight exceeds about 6,000, the uniformity of the resulting spin-on-glass film is reduced by increasing the viscosity of the SOG solution. Therefore, the molecular weight of the perhydro polysilazane used in the present invention is about 3,000 to 6,000, more preferably about 3,300 to 3,700.

In addition, when the molecular weight distribution degree, which is the ratio of the weight average molecular weight and the number average molecular weight of the polysilazane is less than about 3.0, the efficiency in classifying the polysilazane is lowered and the production yield of the polysilazane becomes too low. In contrast, when the molecular weight distribution exceeds about 4, the converted silicon oxide film becomes nonuniform. Therefore, the molecular weight distribution of the polysilazane used in the present invention is preferably about 3.0 to 4.0. However, even polysilazane having a molecular weight distribution out of the above-described molecular weight distribution range may be used if necessary.

Perhydro polysilazane used in another embodiment of the present invention has a molecular weight distribution of about 2.5 to 3.5, more preferably 2.8 to 3.2. When the weight average molecular weight of the perhydro polysilazane is about 3,000 to 6,000, the molecular weight distribution of the perhydro polysilazane is about 2.5 to 3.5. If the molecular weight distribution is less than about 2.5, the efficiency in sorting the perhydro polysilazane will be lowered, resulting in too low a production yield of the perhydro polysilazane. On the other hand, when the molecular weight distribution of the perhydro polysilazane exceeds about 3.5, the converted silicon oxide film becomes nonuniform.

The SOG composition is preferably an SOG solution prepared by dissolving the polysilazane described above in a solvent, preferably an organic solvent. Various other organic solvents or other solvents may be used without limitation in the present invention. Preferably, an aromatic solvent such as xylene or other solvent such as dibutyl ether may be usefully used as the solvent. If the concentration of polysilazane in the SOG solution is greater than about 30% by weight, the polysilazane becomes unstable and the lifetime of the SOG solution is reduced, causing cracks in the SOG film. If the concentration of polysilazane in the SOG solution is less than about 10% by weight, it is not easy to adjust the thickness of the SOG film. Therefore, the concentration of the polysilazane in the SOG solution is preferably about 10 to 30% by weight, 18 to 25% by weight. In addition, the concentration of the solvent in the SOG solution is preferably about 70 to 90% by weight, more preferably about 75 to 82% by weight.

The SOG composition comprising the polysilazane preferably has a contact angle of about 4 ° or less with respect to an underlying film, for example, a silicon nitride film. If the contact angle is larger than 4 °, the adhesive force between the SOG composition and the underlying film becomes poor.

As mentioned above, the SOG composition, preferably the SOG solution, is prepared by dissolving the perhydro polysilazane in a solvent such as an organic solvent. Various other organic or other solvents may be used without limitation in the present invention. The solvent that can be used preferably includes an aromatic solvent such as xylene or another solvent such as dibutyl ether. If the concentration of perhydro polysilazane in the SOG solution is greater than about 30% by weight, the perhydropolysilazane becomes unstable, shortens the life of the SOG solution, and causes cracks in the SOG film. If the concentration of perhydro polysilazane is less than about 10% by weight, it is not easy to control the thickness of the SOG film. Thus, according to another embodiment of the present invention, the concentration of the perhydro polysilazane in the SOG solution is preferably about 10 to 30% by weight, more preferably about 20 to 23% by weight. The SOG composition comprising the polysilazane preferably has a contact angle of about 4 ° or less with respect to an underlying film, for example, a silicon nitride film. If the contact angle is larger than 4 °, the adhesive force between the SOG composition and the underlying film becomes poor.

In order to make the surface of the SOG film uniform during the application process and the curing process, the SOG solution preferably has a viscosity of about 1 to 10 mPa · s, more preferably about 1 to 8 mPa · s under a predetermined shear rate.

2 is a graph for explaining the relationship between the viscosity and the shear rate of the SOG solution. In Fig. 2, the ordinate represents the viscosity (mPa · s) and the abscissa represents the shear rate (1 / s). As shown in FIG. 2, the SOG solution according to the invention preferably has a viscosity of about 1 to 10 mPa · s at a shear rate of about 54 to 420 (1 / s). It can also be seen from FIG. 2 that the viscosity of the SOG composition at a shear rate of about 10 to 1,000 (1 / s) is in the range of about 1 to 10 mPa.

The viscosity of the SOG composition determines the flatness of the oxide film by affecting the flowability of the SOG composition. As the weight average molecular weight of the perhydro polysilazane increases, the viscosity of the SOG composition also increases. When the weight average molecular weight of the perhydro polysilazane is about 3,000 to 6,000, the viscosity of the SOG composition is about 1.54 to 1.70 mPa · s (cP).

The SOG composition may include at least one impurity including boron, fluorine, phosphorus, arsenic, carbon, oxygen, or a mixture thereof as necessary. When at least one element selected from boron, fluorine, phosphorus, or arsenic among these impurities is added to the SOG solution, the silicon oxide film generated from the SOG composition contains impurities, similar to the conventional BSG film, BPSG film, PSG film, and the like. Will have characteristics. In addition, when an element such as carbon or oxygen is added to the SOG solution as an impurity, the speed of converting the SOG film into the silicon oxide film can be accelerated.

The SOG composition described above is preferably applied on a substrate having a non-uniform surface, for example, a semiconductor substrate having a conductive wiring pattern, by a spin coating method. In particular, the spin coating method is useful for forming flat SOG films.

Uneven surface of the substrate may result from conductive patterns. For example, conductive metal wiring patterns such as gate electrode patterns and bit lines form stepped portions on the surface of the substrate. The distance between the two conductive layer patterns is not limited. However, when the said distance is longer than 1 micrometer, it is suitable to use the conventional BPSG as a method of forming an oxide film. On the other hand, when the distance is shorter than 0.04 μm, the use of the SOG solution of the present invention increases the likelihood that voids are formed in the SOG film. Thus, the method of the present invention is applied to a semiconductor substrate having a gap on the order of 0.04 to 1 μm.

In addition, the method according to various embodiments of the present invention may be applied to a conductive pattern gap having a low aspect ratio, which is a ratio of depth to width. However, the methods of the present invention are preferably applied to a conductive layer pattern having an aspect ratio of about 5: 1 to 10: 1.

In general, conductive patterns are densely formed in finely spaced gaps, such as a cell array region comprising gate electrodes. Such gaps may be formed on a semiconductor substrate. In addition, the conductive patterns are densely formed in a global stepped portion, such as a peripheral circuit area, or in a densely independent gap. Such a global step may also be formed on the semiconductor substrate. The method of the present invention can be applied to a semiconductor substrate having a finely spaced gap having an aspect ratio of about 5: 1 to 10: 1 and a global step having an aspect ratio of about 1: 1 or less.

In addition, the stepped portions may be formed by protrusions / depressions of the semiconductor substrate. Specifically, an oxide film can be formed on the protrusion of the semiconductor substrate having the groove and the protrusion by the method of the present invention. Forming the oxide film by this method is useful when forming an isolation structure having a shallow trench isolation (STI) structure. In addition, the stepped portion may be formed by metal lines formed on the insulating layer. That is, the silicon oxide film formed by the method of the present invention can be used as an interlayer insulating film for insulating metal wires formed on the insulating film.

Hereinafter, the curing method of the applied SOG film will be described in detail.

The SOG film formed by the method described above is cured and converted into a silicon oxide film having a flat surface. The curing step is carried out by a preliminary baking step and a main baking step. Based on the disclosure herein, those skilled in the art can cure the SOG film to convert it into a silicon oxide film having a flat surface.

The prebaking is preferably performed for about 1 to 5 minutes at a temperature of about 100 to 500 ℃. If prebaking is performed at about 100 ° C. or lower, there is a possibility that organic solvent remains in the film. If prebaking is performed at a temperature above about 500 ° C., the polysilazane located below the predetermined depth will not be completely converted to silicon oxide in the subsequent main baking process, and the surface will rapidly convert to silicon oxide to cause cracking. As a result, the final silicon oxide film is uneven.

If the time for performing the prebaking is about 1 minute or less, the organic solvent remains in the film and is not completely removed. On the contrary, if the prebaking time exceeds about 5 minutes, the organic solvent is completely removed, but partial conversion to silicon oxide at the surface of the SOG film containing perhydro polysilazane is caused, resulting in partial cracking. Thus, the prebaking is carried out at a temperature of about 100 to 500 ° C., preferably about 100 to 400 ° C. for about 1 to 5 minutes, preferably about 2 to 3 minutes.

The main baking step is carried out for a long time at a high temperature compared to the prebaking. The polysilazane-based SOG has a basic skeleton structure containing Si—N bonds. Baking in an atmosphere containing oxygen and water will replace the Si—N bonds with Si—O bonds. According to the conventional method using the SOG composition described above, not all Si-N bonds are replaced with Si-O bonds, so that some Si-N bonds remain in the silicon oxide film even after the SOG solution is coated and baked. However, according to the method of the present invention, after the SOG solution containing polysilazane is coated to form an SOG film, even after the curing process, Si-N bonds do not remain in the SOG film. therefore. The silicon oxide film formed by various embodiments of the present invention has substantially the same characteristics as the pure silicon oxide film formed by the conventional CVD method.

In order to convert polysilazane to silicon oxide, the main baking is preferably carried out at a temperature of about 400 to 1,200 ° C. In the case where the temperature of the main baking is about 400 ° C. or less, the curing is not sufficient and the Si-N bonds remain to lower the characteristics of the oxide film. When the temperature of the main baking is higher than about 1200 ° C., the flatness of the resulting silicon oxide film may decrease or cracks may occur. Thus, the main baking is carried out at a temperature of about 400 to 1200 ° C, preferably about 400 to 1,000 ° C.

In particular, the time of the main baking process is preferably performed for about 10 minutes to 180 minutes. If the main baking process time is shorter than about 10 minutes, the SOG film is not completely converted to the silicon oxide film. On the contrary, when the main baking process time exceeds about 180 minutes, the stress in the resulting silicon oxide film increases. Therefore, the time of the main baking process is preferably performed for about 10 minutes to 180 minutes, more preferably about 30 minutes to 120 minutes.

The main baking process is carried out in an oxidizing atmosphere or an inert atmosphere, which is an atmosphere suitable for converting Si-N bonds to Si-O bonds. For example, an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of oxygen and steam, a nitrogen atmosphere, or a mixed atmosphere of oxygen, steam and nitrogen is useful for the main baking process. In particular, it is preferable to carry out in a steam atmosphere. The steam atmosphere preferably contains 1.2 to 86% by weight of water.

 The temperature of the main baking is determined taking into account the effect on the substructure. For example, when the lower structure includes a trench formed by partially etching the upper portion of the semiconductor substrate and an SOG film filling the trench, the temperature of the main baking in the curing step is preferably about 900 to 1,200 ° C. When the lower structure includes a plurality of gate electrodes formed on the semiconductor substrate and an SOG film completely covering the gate electrodes, the temperature of the main baking is preferably about 600 to 900 ° C. When the lower structure includes a plurality of metal wiring patterns formed on an insulating film on a semiconductor substrate and an SOG film completely covering the metal wiring patterns, the temperature of the main baking is preferably about 400 to 450 ° C. Those skilled in the art will be able to determine the suitable temperature of the main baking with reference to the present invention and the invention is not limited to the specific temperature ranges described above.

The SOG composition is coated only once by the method according to the invention to form a silicon oxide film having a thickness of about 4,000 to 6,500 kPa. In addition, before applying the SOG composition, a silicon nitride film may be formed on the top and side surfaces of the conductive patterns to a thickness of about 200 to 600 mm 3 as an etch stop film.

The SOG composition may be used to planarize the gate electrode and / or the gold pattern or fill the trench during fabrication of the semiconductor device. Alternatively, the SOG composition according to the present invention may be used to fill trenches and planarize the gate electrode and / or metal pattern using conventional SOG compositions or other methods. That is, the SOG composition of the present invention may be applied to fill trenches or planarize gate electrodes and / or metal patterns, but need not necessarily apply to all of them, but may apply only to any of them.

According to another embodiment of the invention, the main baking process is carried out in a two step heat treatment process. When the heat treatment process is performed in one step, as described with reference to FIG. 1, the silicon oxide is formed on the sidewalls of the trench through the reaction of oxygen included in the oxidative atmosphere with a silicon source supplied from the semiconductor substrate, thereby measuring the size of the active region. Will change. Therefore, when the SOG film is formed by curing the SOG composition including polysilazane on the semiconductor substrate supplied with the silicon source, the SOG film can be converted into the silicon oxide film by performing heat treatment in two steps.

First, a first heat treatment process is performed on the SOG film to convert polysilazane into an oxide. In this case, the first heat treatment process is performed at an temperature of about 500 to 1,000 ° C., preferably about 600 to 900 ° C., in an oxidizing atmosphere such as an oxygen atmosphere, a steam atmosphere, or a mixed atmosphere of oxygen and steam. More preferably, the first heat treatment process is performed for about 10 to 120 minutes at a temperature of about 800 to 900 ℃.

Subsequently, a second heat treatment process is performed on the oxide obtained through the first heat treatment process in an oxidizing atmosphere, an inert gas atmosphere, a mixed atmosphere of the oxidizing atmosphere and the inert gas atmosphere, or a vacuum atmosphere to densify the structure of the oxide. In particular, the second heat treatment process is performed in an inert gas atmosphere containing nitrogen. In addition, the second heat treatment process is performed for about 10 to 120 minutes at a temperature of about 600 to 1,200 ℃, preferably about 900 to 1,100 ℃.

Specifically, when the SOG composition is formed to fill the trench formed by partially etching the upper portion of the semiconductor substrate, it is preferable that the second heat treatment process of the main baking is performed at a temperature of about 900 to 1,000 ° C.

The present invention will be described in more detail with reference to the following Examples, Experimental Examples and Comparative Examples, but the present invention is not limited thereto.

Example 1

Preparation of SOG Composition

Commercially available perhydro polysilazane was fractionated to obtain a perhydro polysilazane having a weight average molecular weight of about 4,500 to 7,000 and a molecular weight distribution of about 3.0 to 4.0. Fractionated perhydro polysilazane was dissolved in xylene to prepare an SOG composition having a perhydro polysilazane at a concentration of about 22-25 wt% relative to the total weight of the composition. As a result of measuring the contact angle with respect to the silicon nitride film | membrane which is a base film, an SOG composition showed the contact angle of 4 degrees or less.

The viscosity of the SOG composition was measured according to the shear rate. Viscosity characteristics are shown in FIG. 2. 2 is a graph showing a change in viscosity with a change in shear rate of SOG solution. In FIG. 2, the vertical axis represents viscosity (mPa · s) and the horizontal axis represents shear rate (1 / s). As can be seen in Figure 2, the SOG solution has a uniformity of about 1 to 10 mPa.s when the shear rate is about 10 to 1,000 (1 / s), preferably about 54 to 420 (1 / s) Has one viscosity.

Formation of oxide film

3A to 3K are cross-sectional views illustrating a method of forming a silicon oxide film in a semiconductor manufacturing process according to an embodiment of the present invention.

Referring to FIG. 3A, a p-type substrate 10 made of a semiconductor material such as silicon (Si) is provided. The trench 12 is formed by etching the device isolation region on the substrate 10. At this time, the trench 12 had a depth of 4,600 mm 3 and a width of 1,250 mm 3. The SOG solution containing perhydro polysilazane having a weight average molecular weight of about 6,000 to 8,000 on the substrate 10 on which the trench 12 is formed is applied to a thickness of about 6,000 to 7,000 kPa to form the first SOG film 13. Formed.

Referring to FIG. 3B, after performing the preliminary baking process on the first SOG film 13 at a temperature of about 100 to 500 ° C. for about 1 minute to 5 minutes, the main baking is performed at about 900 to 1,000 ° C. for about 30 minutes. The process was performed to convert the first SOG film into the first silicon oxide film 13a. At this time, the baking process was carried out in a steam atmosphere containing about 86% by weight of moisture.

Referring to FIG. 3C, the first silicon oxide layer 13a is polished by the chemical mechanical polishing method CMP until the upper surface of the semiconductor substrate 10 is exposed, so that the inside of the trench 12 may be silicon oxide ( A device isolation region buried in 14) was formed.

Referring to FIG. 3D, n-type impurities such as phosphorus (P) are ion-implanted into the semiconductor substrate 10 in the region where the memory cell is formed to form the n-type semiconductor region 20. P-type impurities, for example, boron (B), are ion-implanted into a portion of the cell array region and the peripheral circuit region to form the p-type well 30. An n-type impurity, for example, phosphorus (P) is ion-implanted into the remaining part of the peripheral circuit region to form an n-type well 40.

Next, impurities for adjusting the threshold voltage, such as BF ₂ (boron fluoride), were ion-implanted into the p-type well 30 and the n-type well 40. Subsequently, each surface portion of the p-type well 30 and the n-type well 40 was washed with a hydrofluoric acid-based cleaning liquid. The semiconductor substrate 10 was wet oxidized to form a gate oxide film 16 on each surface of the p-type well 30 and the n-type well 40. At this time, the substrate portion in the trench 12 was also partially oxidized, so that the gate oxide film 16 was formed continuously. At this time, the thickness of the gate oxide film 16 was about 40 to 200 kPa.

Referring to FIG. 3E, a polysilicon film is formed on the substrate 10 having the silicon oxide 14 and the gate oxide film 16 filling the trench 12 as field oxide. The polysilicon film had a thickness of about 500 to 4,000 kPa, and was formed by depositing a polycrystalline silicon film doped with n-type impurities such as phosphorus (P) by low pressure chemical vapor deposition (LPCVD). Next, tungsten silicide and tungsten were deposited on the polysilicon film by the sputtering method to form a tungsten silicide film having a thickness of about 1,000 mm 3 and a tungsten film having a thickness of 2,000 mm 3. A silicon nitride film was laminated on the tungsten film. The silicon nitride film was formed to have a thickness of about 500 to 2,000 Pa using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

After the photoresist film was formed on the silicon nitride film, the photoresist film was selectively exposed using a mask. Next, the photoresist film was developed to form a photoresist pattern 22 for forming a gate electrode. Using the photoresist pattern 22 as an etching mask, the silicon nitride film, tungsten film, tungsten nitride film and polysilicon film are sequentially etched to form a polysilicon pattern 24a, a tungsten silicide pattern 24b, a tungsten pattern 24c and Gate electrodes 24Ga, 24Gb, 24Gc, and 24WL formed of the silicon nitride film pattern 24d were formed. Then, gate electrodes 24Ga and word lines 24WL are formed in the cell array region, and gate electrodes 24Gb and 24Gc are formed in the peripheral circuit region, respectively.

The gap between the gate electrodes 24Ga and 24WL formed in the cell array region was about 0.4 to 1 m. In order to form dense steps in the gap, the aspect ratio, which is the ratio of the height to the width of the gap of the gate electrodes 24Ga and 24WL, was about 5: 1 to 10: 1. On the other hand, in order to form the global stepped portion in the gap, the aspect ratio, which is the ratio of the height to the gap of the gate electrodes 24Gb and 24Gc formed in the peripheral circuit region, was 1: 1 or less.

Referring to FIG. 3F, the photoresist pattern 22 is removed. In FIG. 3F, p-type impurities such as boron (B) are ion-implanted into the n-type well 40 to form the p-type impurity region 25 in the n-type well 40 on both sides of the gate electrode 24Gc. Formed. In addition, n-type impurities such as phosphorus (P) are ion-implanted into the p-type well 30 to form n-type impurity regions 27 in the p-type wells 30 on both sides of the gate electrode 24Gb. An n-type impurity region 26 is formed in the p-type wells 20 on both sides of the gate electrode 24Ga.

Referring to FIG. 3G, silicon nitride is deposited on the semiconductor substrate 10 by chemical vapor deposition (CVD) to form a silicon nitride film 32 having a thickness of about 200 to 600 microns. Next, the silicon nitride film 32 on the cell array region is covered with a photoresist film, and the silicon nitride film 20 on the peripheral circuit is anisotropically etched to form spacers 32a on the sidewalls of the gate electrodes 24Gb and 24Gc of the peripheral circuit. It was.

Next, p-type impurities, for example boron, were ion-implanted into the n-type well 40 of the peripheral circuit to form a p + type impurity region (source, drain region) 42. In addition, n-type impurities such as arsenic (As) were ion-implanted into the p-type well 30 of the peripheral circuit to form n + -type impurity regions (source and drain regions) 44.

Referring to FIG. 3H, a second SOG film 50 is formed by applying an SOG solution on the semiconductor substrate 10. The second SOG film 50 was also coated by a spin coating method. At this time, the rotation speed was about 500 to 2,500 rpm. The weight average molecular weight of the perhydro polysilazane included in the SOG solution was about 4,000 to 6,000. The second SOG film 50 has a thickness of about 7,500 to 8,200 Å, so as to completely cover the gate electrodes 24Ga, 24Gb, 24Gc, and 24GWL. Next, the second SOG film 50 was prebaked at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, and then main baked at a temperature of about 600 to 900 ° C. for about 10 to 180 minutes. At this time, the baking process was performed in an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of steam and oxygen, a nitrogen atmosphere, or a mixed atmosphere thereof. If the baking process was carried out in a steam atmosphere, the moisture content of the steam atmosphere was adjusted to be about 1.2 to 86% by weight.

During the curing process, the Si—N bond of the second SOG film 50 was replaced with a Si—O bond, and the second SOG film was converted into the second silicon oxide film 50a. As a result, as shown in FIG. 3I, a second silicon oxide film 50a having a thickness shrinking about 19 to 20% of the thickness of the second SOG film was obtained.

Referring to FIG. 3J, a metal such as aluminum and tungsten is deposited on the second silicon oxide film 50a by a conventional sputtering method to form a metal film having a thickness of about 5,000 kPa. The metal layer was patterned by a photolithography process to form metal layer patterns 52 having a width of 6,600 mm 3 and a gap of 8,400 mm 3. Next, the SOG solution was spin-coated to form a third SOG film 54 having a thickness of about 3,800 to 4,500 도록 so as to completely cover the metal layer patterns 52. In this case, the weight average molecular weight of the perhydro polysilazane included in the third SOG film 54 was about 4,500 to 7,500.

Referring to FIG. 3K, after the first SOG film 54 is prebaked at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, the main baking is performed at about 400 to 450 ° C. for about 10 to 180 minutes. Was done. The main baking process was carried out in a steam atmosphere. The Si-N bond of the third SOG film 54 is replaced with the Si-O bond through the curing process, thereby converting the third SOG film 54 into the third silicon oxide film 54a having a flat surface.

Then, the semiconductor device was manufactured through the normal semiconductor manufacturing process. Those skilled in the art will be able to manufacture the semiconductor device through the SOG composition according to the present invention and the method according to various embodiments of the present invention.

Light Absorption of Silicon Oxide

An oxide film was formed on the semiconductor substrate according to the method described with reference to FIGS. 3A to 3K. The oxide film had a plurality of wiring layers having an aspect ratio of about 5: 1 to 10: 1, and was formed on a substrate having a gap of about 0.04 to 1 μm between the wiring layers. A silicon nitride film having a thickness of about 400 GPa was formed covering the plurality of metal wiring layers and the semiconductor substrate.

An SOG solution containing polysilazane was spin coated onto a semiconductor substrate to form a second SOG film having a thickness of about 7,582 kPa. At this time, the rotation speed was about 1,000 rpm.

After the second SOG film was prebaked at 150 ° C. for 3 minutes, the absorbance of the SOG film was measured using the Fourier Transform InfraRed method.

4 is an FT-IR chart showing light absorbance measured after prebaking the SOG film. As shown in FIG. 4, after prebaking, the peaks of the light absorbance appeared in several waveguide regions indicating the bonding of NH, Si-H, Si-N, Si-H, and the like. At this time, the stress measured with the stress gauge was about 3.63 × 10 ⁸ (dyne / cm ² ).

In addition, the SOG film was prebaked, and then main baked at a temperature of 700 ° C. for 30 minutes to convert the silicon oxide film. FIG. 5 is an FT-IR chart showing light absorption of silicon oxide film according to wave number and weight average molecular weight, measured after main baking of SOG film. Referring to FIG. 5, only the peaks of the Si-O bond and the corresponding waveguide regions remained after the main baking. At this time, the stress was -1.22 × 10 ⁸ (dyne / cm ² ). From FIG. 5, it can be seen that the Si—N bonds of all the SOG films were substituted with the Si—O bonds, thereby confirming that the spin-on glass film was completely converted to the silicon oxide film.

Further, no voids were found in the silicon oxide film formed on the surface of the semiconductor substrate having an aspect ratio of about 5: 1 to 10: 1 and having a plurality of wiring patterns having a gap of about 0.04 to 1 μm.

Etch Rate Measurement of Silicon Oxide

A. Formation of Silicon Oxide Film Using SOG Composition

The SOG solution was applied onto a bare wafer to form an SOG film. The SOG solution was applied by a spin coating method, the rotation speed was 1,000rpm. The SOG film was formed to have a thickness of about 7,500 to 8,200 Å. Next, the SOG film was prebaked at a temperature of about 150 ° C. for 3 minutes, and then main baked at a temperature of about 700 ° C. for about 30 minutes. At this time the main baking was carried out in a steam atmosphere having a moisture content of about 1.2 to 86% by weight. Through the curing process, the Si—N bond of the SOG film is replaced with a Si—O bond, and the SOG film is converted into a silicon oxide film. The silicon oxide film formed at this time was about 6,400 kPa.

B. Formation of Oxide Film by CVD Method

A high density plasma CVD-oxide film was formed on the bare wafer using silane gas and oxygen as the source gas and argon gas as the carrier gas. The thickness of the CVD oxide film formed at this time was about 6,000 Pa.

C. Wet Etch Rate Measurement

The silicon oxide film formed according to the present invention and the CVD oxide film according to the CVD method were etched, respectively. Each wet etching process was performed using the same etchant for a certain time, and the etching rate was examined at regular time intervals. The results are shown in Figures 6a to 6f.

Figure 6a is a graph showing the results of measuring the etching rate of the oxide film formed according to the present invention and the oxide film according to the CVD method at 1 minute intervals. Wet etching was performed at room temperature (25 ° C.) using a solution obtained by diluting a buffer etching solution containing ammonium fluoride in distilled water (NH ₄ F and HF diluted in distilled water).

6B is a graph showing the results of measuring the etching rate of the oxide film formed according to the present invention and the oxide film according to the CVD method at 1 minute intervals. Wet etching was performed at room temperature (25 ° C.) using an aqueous solution of dilute hydrofluoric acid (distilled water: hydrofluoric acid (HF) = 100: 1).

6C is a graph showing the results of irradiating the etch rate of the oxide film formed according to the present invention and the oxide film according to the CVD method at 10 minute intervals. Wet etching was performed at a temperature of 70 ° C. using an etching solution in which ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) were mixed at a ratio of 0.25: 1: 5.

Figure 6d is a graph showing the results of irradiating the etching rate of the oxide film formed according to the present invention and the oxide film according to the CVD method every 10 minutes. Wet etching was performed at 165 ° C. using phosphoric acid.

Figure 6e is a graph showing the results of irradiating the etching rate of the oxide film formed according to the present invention and the oxide film according to the CVD method every 10 minutes. The wet etching was performed at a temperature of 130 ° C. using an etching solution in which sulfuric acid and hydrogen peroxide were mixed at a ratio of about 6: 1.

Figure 6f is a graph showing the results of irradiating the etching rate of the oxide film formed according to the present invention and the oxide film according to the CVD method every 10 minutes. Wet etching was performed at a temperature of 50 ° C. using an etching solution in which ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) were mixed at a ratio of 0.25: 1: 5.

D. Dry Etch Rate Survey

The oxide film formed according to the present invention and the oxide film formed according to the CVD method were introduced into the same chamber, and the etching rate was repeatedly examined using the same etching gas. The pressure in the chamber was adjusted to 30 mTorr and the output voltage to 1,700 W. In addition, the etching gas is octafluoropentene (C ₅ F ₈ ), octafulurobutene (C ₄ F ₈ ), oxygen (O ₂₎ and argon (Ar) flow rate of 8sccm, 4sccm, 6sccm and 500sccm, respectively It was used as a result of the investigation of the etching rate is shown in Figure 6g as a graph.

6A to 6G, it can be seen that the wet etching rate and the dry etching rate of the silicon oxide film formed according to the present invention are very similar to the wet etching rate and the dry etching rate of the silicon oxide film formed by a conventional CVD method. Therefore, the interlayer insulating film or planarized film formed using the SOG film according to the present invention has characteristics similar to those of the conventional CVD-oxide film.

Through repeated experiments by the present inventors, the void-free oxide film using the SOG composition according to the present invention on a semiconductor layer having an aspect ratio of about 5: 1 to 10: 1 and a gap of about 0.04 to 1 μm. Could form. According to the present invention, the SOG composition can be used to form a void-free silicon oxide film having the flatness required for 256M DRAM.

Example 2

Preparation of SOG Composition

Perhydro polysilazane having a weight average molecular weight of about 6,000 to 8,000 and a molecular weight distribution of about 3.0 to 4.0 was prepared using the same method as in Example 1. The SOG composition was prepared by dissolving the perhydro polysilazane in xylene at a concentration of about 22-25 wt%.

Shallow Trench Isolation

In the case of forming the field oxide film shown in FIG. 3 according to Embodiment 1 to fill the trench of the highly integrated semiconductor device, a thick oxide film is formed on the inner wall of the trench as shown in FIG. 1.

7A to 7G are cross-sectional views illustrating a method of separating a trench trench device according to another exemplary embodiment of the present invention.

Referring to FIG. 7A, a pad oxide layer 201 having a thickness of about 100 to about 200 kPa was formed by performing a thermal oxidation process on a semiconductor substrate including silicon. Subsequently, a nitride having a thickness of about 100 to 1,000 mW was deposited on the pad oxide film 201 using a low pressure chemical vapor deposition (LPCVD) method to form an abrasive stop film 203. The polishing blocking film 203 was formed to prevent polishing in the subsequent CMP process.

Next, a high temperature oxide (HTO) having a thickness of about 500 to 1,000 GPa was deposited on the polishing stopper film 203 using the LPCVD method to form a hard mask film 205. Silicon nitride oxide (SiON) was deposited on the hard mask film 205 with a thickness of about 200 to 800 Å by the LPCVD method to form an antireflection film (not shown). The anti-reflection film prevented scattered light when performing a photolithography process and was removed in a subsequent process of forming a trench.

Referring to FIG. 7B, a hard mask pattern 206 for forming an active pattern is formed by dry etching the anti-reflection film and the hard mask film 205 by a photolithography process. Subsequently, the abrasive stop layer 203 and the pad oxide layer 201 were etched using the hard mask pattern 206 as an etch mask to form the etch stop layer pattern 204 and the pad oxide layer pattern 202.

Referring to FIG. 7C, the trench 210 is formed by etching the exposed portion of the substrate 200 to a depth of about 2,000 to 5,000 microns using the hard mask pattern 206. The trench 210 preferably has a depth of 4,600Å and a width of 1,250Å. At this time, the anti-reflection film was removed, and the hard mask pattern 206 was etched to have a predetermined thickness.

Referring to FIG. 7D, an exposed portion of the trench 210 is heat-treated in an oxidizing atmosphere in order to cure silicon damage generated on the semiconductor substrate 200 by high energy ion implantation during the trench etching process. Subsequently, a trench inner wall oxide film 212 having a thickness of about 20 to about 300 kW was formed on the inner wall of the trench 210 including the bottom and side surfaces of the trench 210 through an oxidation reaction between the exposed silicon and the oxidant.

After forming the trench inner wall oxide film 212 as described above, the trench 210 was buried in an SOG composition to form an SOG film 213 having a thickness of about 6,000 to 7,000 kPa.

Referring to FIG. 7E, the SOG film 213 is prebaked at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, and then about 10 to about 10 ° C. in an oxidizing atmosphere of about 800 to 900 ° C., preferably about 850 ° C. The SOG film 213 was converted into a silicon oxide film by performing a first heat treatment process again for 120 minutes, preferably about 60 minutes. At this time, the first heat treatment step was carried out in a steam atmosphere containing water of 86 mid-range.

Subsequently, a second heat treatment process was performed to convert the converted silicon oxide into a silicon oxide film 214 by densifying the converted silicon oxide. The second heat treatment process is carried out in an oxidizing atmosphere, an inert gas atmosphere or a mixed atmosphere thereof, preferably in an inert gas atmosphere such as a nitrogen gas atmosphere. In addition, the second heat treatment process was performed for about 10 to 120 minutes, preferably about 30 minutes at a temperature of about 900 to 1,100 ℃, preferably about 1,000 ℃.

Referring to FIG. 7F, by the CMP process, the silicon oxide film 214 is polished until the polishing stopper film 204 on the semiconductor substrate 200 is exposed, so that the inside of the trench 210 is silicon oxide 216. ).

Referring to FIG. 7G, a strip process using phosphoric acid was performed to remove the polishing stopper pattern 204, thereby completing device isolation as shown in FIG. 7G.

Substrate Oxide Formation Investigation

Experimental Example 1

After the SOG film was formed on the blanket wafer in the same manner as in Example 1, a preliminary baking process and a main baking process were performed.

Experimental Example 2

After the SOG film was formed on the blanket wafer in the same manner as in Example 2, a pre-baking process, a first heat treatment process for 1 hour in a steam atmosphere at 850 ° C., and a second heat treatment process for 30 minutes in an oxygen atmosphere at 1,000 ° C. were performed. To form a silicon oxide film.

Experimental Example 3

A silicon oxide film was formed in the same manner as in Experiment 2 except that the second heat treatment process was performed in a nitrogen gas atmosphere.

Experimental Example 4

A silicon oxide film was formed in the same manner as in Experiment 2, except that the second heat treatment process was performed at 1,050 ° C.

Experimental Example 5

A silicon oxide film was formed in the same manner as Experimental Example 2, except that the first heat treatment process was performed at 900 ° C.

Investigate the oxidation state of the substrate surface

In the wafers subjected to the baking process according to Experimental Examples 1 to 5, FT-IR analysis of stretching peaks of Si—O bonds on the substrate surface was performed.

8 is a bar graph showing the intensity of normalized light absorbance obtained by performing FT-IR analysis on silicon oxide formed in the active region of the substrate according to the present invention. From FIG. 8, the silicon oxide film obtained by performing the two-step heat treatment process as in Experimental Examples 2 to 5 contains more oxides than the silicon oxide film obtained through the one-step heat treatment process as in Experimental Example 1 It can be confirmed. In addition, it can also be confirmed that the amount of the oxide formed by Experimental Example 3 is smallest among the oxides formed from the substrates of Experimental Examples 2 to 5.

Investigation of wet etching rate and etching uniformity

According to Experimental Examples 2 to 4, the etching rates of the silicon oxide film formed by converting the SOG composition and the silicon oxide film formed by the high density plasma chemical vapor deposition method (HDP-CVD) were examined. Wet etching was performed for a certain time using the same etching solution, the etching rate was investigated at regular time intervals. SC-1 solution (a mixture of ammonia, hydrogen peroxide and deionized water), LAL solution (mixture of ammonium fluoride and hydrogen fluoride) and phosphoric acid solution were used as the etching solution. The results are shown graphically in FIG. 9, in which the vertical axis represents the etching rate, and the horizontal axis represents the etching solution and the type of oxide etched.

9, it can be seen that the silicon oxide film formed from Experimental Examples 2 to 5 has an etching rate similar to that of the silicon oxide film produced from Experimental Example 1. FIG.

Polishing test

A semiconductor having the same pattern as described in Example 2 using a silicon oxide film formed by a high density plasma chemical vapor deposition method and a silicon oxide film formed by Example 2 (the baking process was performed as described in Experimental Example 3). After the trench of the substrate was buried, a chemical mechanical polishing process was performed. The polishing process was performed until the polishing stopper was exposed, and the profile of the oxide film was examined to investigate the uniformity of the polishing. The result is shown in FIG.

In Fig. 10, the graphs show the results after polishing the silicon oxide film formed by the high density plasma chemical vapor deposition method and the silicon oxide film formed by the experimental example 3, respectively. During polishing, the same silicon dioxide was used as for slurry preparation. In FIG. 10, the vertical axis shows the degree of polishing after polishing (unit: kPa). At this time, the polishing process was performed for about 180 to 200 seconds for the silicon oxide film formed by the high density plasma chemical vapor deposition method, and about 100 seconds for the silicon oxide film formed by Experimental Example 3. As shown in FIG. 10, the polishing amount of the silicon oxide film formed by the high density plasma chemical vapor deposition method was about 300 to 500 kPa, while the polishing amount of the silicon oxide film formed by Experimental Example 3 was about 100 to 200 kPa.

10, the polishing uniformity of the silicon oxide film formed by Example 2 is about twice as good as the polishing uniformity of the silicon oxide film formed by the conventional high density plasma chemical vapor deposition method, and the silicon formed by Example 2 It can be seen that the polishing time of the oxide film is about half of the polishing time of the silicon oxide film formed by the conventional high density plasma chemical vapor deposition method.

In addition, the silicon oxide film formed by Example 2 had no voids and had excellent gap filling characteristics, whereas the oxide film formed by the high density plasma chemical vapor deposition method had many voids in the trench portion. In addition, silicon in the active region was not oxidized, and an oxide film was densely formed at the bottom of the trench, and thus had excellent oxide film characteristics.

11 is a flowchart illustrating a method of forming an oxide film using an SOG composition according to an embodiment of the present invention. Referring to FIG. 11, in step S100, an SOG film is formed by applying an SOG composition on a substrate, and then an oxide film may be formed by curing the SOG film in steps S210 and S220.

In step S100, by applying the SOG composition on the semiconductor substrate having the stepped portion, an SOG film having a flat surface can be formed on the substrate. The stepped portion may be formed by at least two conductive patterns formed on the substrate. For example, the conductive pattern may include a metal conductive wiring pattern such as a gate electrode pattern and / or a bit line pattern.

In steps S210 and S220, the SOG film is cured to convert the SOG film into a flat silicon oxide film. The curing process may be performed by an evi baking process and a main baking process. The preliminary baking process (step S210) may be performed at a temperature of about 100 to 500 ° C, while the main baking process (step S220) may be performed at a temperature of about 400 to 1,200 ° C.

If the preliminary baking process (step S210) is performed at a temperature lower than about 100 ° C., an organic solvent may remain in the silicon oxide film. When performed at temperatures above about 500 ° C., the perhydropolysilazane may not be fully converted to silicon oxide in the subsequent main baking process, and the surface portion of the SOG film is rapidly converted to silicon oxide, resulting in cracking Unevenness of the silicon oxide film may be caused.

If the pre-baking process (S210) is performed within 1 minute, the organic solvent may remain in the film, and if it is performed for more than 5 minutes, even if the organic solvent is completely removed, the surface of the SOG film containing perhydro polysilazane Conversion to silicon oxide may occur, resulting in partial cracking. Thus, the preliminary baking process is carried out at a temperature of about 100 to 500 ° C., preferably about 100 to 400 ° C. for about 1 to 5 minutes, preferably about 2 to 3 minutes.

The preliminary baking process (step S210) may be performed in an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a vacuum atmosphere, preferably in a steam atmosphere.

The main baking process (step S220) is preferably performed for a long time at a high temperature as compared to the preliminary baking process (step S210). The SOG of the perhydro polysilazane-based basic skeleton contains Si-N bonds, and these Si-N bonds are substituted with Si-O bonds when baked in an atmosphere containing oxygen and water. According to conventional methods using SOG compositions, not all Si-N bonds are generally substituted with Si-O bonds. However, when the SOG film is formed by coating with an SOG solution containing perhydro polysilazane according to an embodiment of the present invention, and then performing a curing process, no Si—N bond remains.

Preferably, the main baking process (step S220) is carried out at a temperature of about 400 to 1,200 ℃. If the temperature of the main baking is less than about 400 ° C., some Si—N bonds may remain and adversely affect the characteristics of the oxide film, which is not preferable. If the temperature of the main baking is higher than about 1,200 ° C., The flatness of the silicon oxide film is lowered or cracks are not preferable. Therefore, the main baking (step S220) is carried out at a temperature of about 400 to 1,200 ℃, preferably about 400 to 1,000 ℃.

In addition, the main baking process (step S220) is performed for about 10 to 180 minutes, preferably about 30 to 120 minutes. If the execution time of the main baking process (step S220) is shorter than about 10 minutes, the conversion of the SOG film to the silicon oxide film is insufficient, and if it exceeds about 180 minutes, the stress of the resulting silicon oxide film is increased. Not desirable

The main baking process (step S220) is carried out in an oxidizing atmosphere and / or an inert atmosphere, which is an atmosphere suitable for converting Si-N bonds to Si-O bonds. For example, the main baking process (step S220) may be performed in an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of oxygen and steam, a nitrogen atmosphere, or a vacuum atmosphere. In particular, it is preferable to carry out in a steam atmosphere, in which the moisture content is preferably maintained at about 1.2 to 86% by weight.

By the method according to the present invention, a silicon oxide film having a thickness of about 1,000 to 10,000 Å is formed in one step using the SOG composition. When the silicon oxide film has a thickness within the above range, the silicon oxide film can economically cover a conductive layer such as a gate electrode or a metal pattern, which is an underlying structure. In addition, a silicon nitride film having a thickness of about 200 to 600 kPa may be formed on the upper and side surfaces of the conductive layer pattern before applying the SOG composition.

12 is a graph showing the FT-IR results according to the temperature of the main baking process (when the water content is 80% by weight) according to an embodiment of the present invention. As shown in FIG. 12, it can be seen that all the bonds of the perhydro polysilazane are effectively substituted with Si—O bonds.

13 is a graph showing the FT-IR results according to the temperature of the main baking process (when the water content is 10% by weight or less) according to an embodiment of the present invention. As shown in FIG. 13, when the main baking process is performed in an atmosphere containing water having a moisture content of 10 wt% or less, it may be confirmed that the Si—O bond is more effectively substituted as the temperature of the main baking increases. The main baking process can be carried out in a mixed atmosphere of oxygen and water vapor present in an inert atmosphere such as nitrogen. Si-N bond, Si-H bond, and N-H bond are all substituted by Si-O bond in a steam atmosphere. The moisture content in the steam atmosphere is about 1.2 to 86% by weight, and the lower the temperature of the main baking, the more moisture is required.

14 is a graph showing the FT-IR results according to the main baking according to an embodiment of the present invention. As shown in FIG. 14, when the main baking process is performed in a steam atmosphere, it can be seen that the Si-N bond, the Si-H bond, and the NH bond are more effectively substituted with the Si-O bond than in the case of the nitrogen atmosphere. .

Example 3

Preparation of Spin-on Glass Composition

Commercially available perhydro polysilazane was fractionated to obtain a perhydro polysilazane having a weight average molecular weight of about 3,000 to 6,000. The molecular weight distribution of the perhydro polysilazane was about 2.5 to 3.5. The SOG composition was prepared by dissolving the prepared perhydro polysilazane in xylene at a concentration of about 20 to 30% by weight. The SOG composition showed a contact angle of 4 degrees or less as a result of measuring the contact angle with respect to the silicon nitride film which is an underlayer.

The viscosity of the prepared SOG composition was measured at various shear rates. In this case, the SOG composition showed a constant viscosity within the range of about 1.54-1.70 cP.

Example 4

Preparation of SOG Composition

Fractionation gave a perhydro polysilazane having a weight average molecular weight of 3,000. The molecular weight distribution of the obtained perhydro polysilazane was 2.8. This is summarized in Table 1 below and FIG. 15. The SOG composition was prepared by dissolving the prepared perhydro polysilazane in a concentration of 22.6 wt% in dibutyl ether. The viscosity and solids concentration of the prepared SOG composition are shown in Table 1, Figure 15, Figure 16 and Figure 17.

15 is a graph showing the molecular weight distribution of the SOG composition according to the weight average molecular weight (Mw) according to an embodiment of the present invention. 16 is a graph showing the viscosity of the SOG composition according to the weight average molecular weight (Mw) according to an embodiment of the present invention. 17 is a graph showing the concentration (wt%) of the solid content of the SOG composition according to the middle average molecular weight (Mw) according to an embodiment of the present invention. Moreover, the obtained SOG composition showed the contact angle of 4 degrees or less with respect to the silicon nitride film | membrane which is a base film.

Examples 5-7

Preparation of SOG Composition

The SOG composition was prepared in the same manner as in Example 4 except for changing the weight average molecular weight. According to each example, perhydro polysilazane having a weight average molecular weight of 3500 (Example 5), 4500 (Example 6) and 5500 (Example 7) is used. The viscosity and solid content concentration of the SOG composition according to each example are shown in Tables 1, 15, 16, and 17 below.

Comparative Example 1

Preparation of SOG Composition

The SOG composition was prepared in the same manner as in Example 4, except using perhydro polysilazane having a weight average molecular weight of 8,000. The viscosity of the SOG composition according to Comparative Example 1 and the concentrations of solids are shown in Tables 1, 15, 16, and 17 below.

Example 4 Example 5 Example 6 Example 7 Comparative Example 1 Molecular weight distribution 2.8 2.92 3.17 3.38 3.92 Viscosity (mPa.s) 1.54 1.55 1.59 1.66 1.78 Solid content (% by weight) 22.6 22.6 21.6 21.8 21.1

Example 8

Formation of oxide film

18A to 18K are cross-sectional views illustrating a method of forming an oxide film in a semiconductor manufacturing process according to another exemplary embodiment of the present invention. Referring to FIG. 18A, a p-type substrate 10 made of a semiconductor material such as silicon (Si) is prepared. The trench 12 is formed by etching the device isolation region on the substrate 10. At this time, the trench 12 had a depth of 4600 mm and a width of 1250 mm. The SOG solution containing perhydro polysilazane having a weight average molecular weight of about 3,000 to 6,000 (for example, 3,000) on the substrate 10 having the trench 12 is about 6,000 to 7,000 (for example, 6,000 Å). Was applied to form a first SOG film 13.

Referring to FIG. 18B, after performing the preliminary baking process on the first SOG film 13 at about 100 to 500 ° C. (for example, 300 ° C.) for 1 to 5 minutes on a hot plate, about 900 to 1,000 ° C. (Example For example, a main baking process was performed at a temperature of about 950 ° C. for 30 minutes to convert the first silicon oxide film 13a. At this time, the baking process was carried out in a steam atmosphere containing about 86% by weight of moisture.

Referring to FIG. 18C, the obtained first silicon oxide film 13a is polished until the upper surface of the semiconductor substrate 10 is exposed by the chemical mechanical polishing method (CMP), and as shown, the trench 12 ) To form an isolation region in which silicon oxide 14 is embedded.

Referring to FIG. 18D, an n-type impurity, for example, phosphorus (P) is implanted into a semiconductor substrate 10 in a region (cell array region) in which a memory cell is to be formed, thereby forming an n-type semiconductor region 20, and P-type impurities, such as boron (B), are ion-implanted into the array region and a portion of the peripheral circuit region to form the p-type well 30, and n-type impurities, such as phosphorus (P) in the remaining portion of the peripheral circuit region. P) was injected to form an n-type well 40.

Next, impurities for adjusting the threshold voltage, such as boron fluoride (BF ₂ ), were ion-implanted into the p-type well 30 and the n-type well 40. Subsequently, each surface portion of the p-type well 30 and the n-type well 40 is cleaned using a hydrofluoric acid-based cleaning solution, and then the semiconductor substrate 10 is wet oxidized to form the p-type well 30 and the n-type well ( A gate oxide film 16 was formed on each surface portion of 40). At this time, a part of the substrate of the inner surface portion of the trench 12 was also partially oxidized to form the gate oxide film 16 continuously. At this time, the gate oxide film 16 had a thickness of about 40 to 120 kV (for example, 120 kPa).

Referring to FIG. 18E, doped with n-type impurities such as phosphorus (P), for example, on the substrate 10 on which the silicon oxide 14 embedded in the trench 12 and the gate oxide film 16 are formed as the field oxide film. The polycrystalline silicon film was deposited by low pressure chemical vapor deposition (LPCVD) to form a polysilicon film having a thickness of about 500 to 4,000 kPa (for example, 2,300 kPa). Subsequently, a tungsten silicide film and a tungsten film were formed on the polysilicon film so as to have a thickness of about 1,000 to 2,000 kPa each by a sputtering method, and then a silicon nitride film was formed on the tungsten film. The silicon well film was formed to have a thickness of about 500 to 2,000 mW (for example, 1,000 mW) using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

After the photoresist film was formed on the silicon nitride film, the photoresist film was selectively exposed using a mask. Next, the photoresist film was developed to form a photoresist pattern 22 for forming a gate electrode. Using the photoresist pattern 22 as an etching mask, the silicon nitride film, tungsten film, tungsten nitride film, and polysilicon film are etched in sequence to form a polysilicon pattern 24a, a tungsten silicide pattern 24b, a tungsten pattern 24Gc, and Gate electrodes 24Ga, 24Gb, 24Gc, and 24WL formed of the silicon nitride film pattern 24d were formed. Then, as shown, it can be seen that the gate electrodes 24Ga and the word line 24WL are formed in the cell array region, and the gate electrodes 24Gb and 24Gc are formed in the peripheral circuit region, respectively.

The gap between the gate electrodes 24Ga and 24WL formed in the cell array region was about 0.4 to 1 m. In order to form a dense stepped portion, the aspect ratio, which is the ratio of the depth to the gap of the gate electrodes 24Ga and 24WL, was about 5: 1 to 10: 1. In order to form the global stepped portion, the gate electrodes 24Gb and 24Gc formed in the peripheral circuit region had an aspect ratio of 1: 1 or less.

Referring to FIG. 18F, the photoresist pattern 22 is removed. In FIG. 18, p-type impurities, such as boron (B), are ion-implanted into the n-type well 20 to form the p-type impurity region 25 in the n-type well 40 on both sides of the gate electrode 24Gc. It was. In addition, n-type impurities such as phosphorus (P) are ion-implanted into the p-type well 30 to form the n-type impurity region 27 in the p-type well 30 on both sides of the gate electrode 24Gb. An n-type impurity region 26 is formed in the p-type well 20 on both sides of the electrode 24Ga.

Referring to FIG. 18G, silicon nitride is deposited on the semiconductor substrate 10 by chemical vapor deposition to form a silicon nitride film 32 having a thickness of about 200 to 600 microns. Next, the silicon nitride film 32 in the cell array region is covered with a photoresist film, and the silicon nitride film 32 in the peripheral circuit region is anisotropically etched to form spacers 32a on the sidewalls of the gate electrodes 24Gb and 24Gc of the peripheral circuit. Formed.

Next, p-type impurities, such as boron, were ion-implanted into the n-type well 40 of the peripheral circuit to form p + -type impurity regions (source and drain regions). Further, n-type impurities such as arsenic (As) were ion-implanted into the p-type well 30 of the peripheral circuit to form n + -type impurity regions (source and drain regions).

Referring to FIG. 18H, the SOG composition is applied on the semiconductor substrate 10 to form a second SOG film 50. The second SOG film 50 is also coated by a spin coating method. At this time, the rotation speed was about 500 to 2,500 rpm (for example, 1,000 rpm). The weight average molecular weight of the perhydro polysilazane included in the SOG solution was about 3,000 to 6,000 (for example, 3,000), and the second SOG film 50 was about 7,500 to 8,200 kPa (for example, 7,900 kPa). It was formed to completely cover the gate electrodes 24Ga, 24Gb, 24Gc, 24GWL while having a thickness of.

Next, the second SOG film 50 is prebaked in air at a temperature of about 100 to 500 ° C. (eg 150 ° C.), and then at a temperature of about 600 to 900 ° C. (eg 700 ° C.). Main baking was performed for about 10 to 180 minutes (eg 30 minutes) in a steam atmosphere. At this time, the pre-baking and the main baking could be performed in any one of an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a mixed atmosphere of oxygen, water vapor and nitrogen. If the baking process is carried out in a steam atmosphere, the moisture content is preferably maintained in the range of about 1.2 to 86% by weight (eg 86% by weight).

Through the above-mentioned hardening process, the Si-N bond of the 2nd SOG film 50 was substituted by the Si-O bond, and was converted into the silicon oxide film. As a result, as shown in Fig. 18I, a second silicon oxide film 50a having a thickness shrunk by about 19 to 23% (for example, 22.1%) with respect to the thickness of the second SOG film was obtained.

Referring to FIG. 18J, a metal layer, such as aluminum and tungsten, was deposited on the second silicon oxide film 50a by a conventional sputtering method to form a metal layer having a thickness of 5,000 kPa. The metal layer was patterned by a photolithography process to form metal layer patterns 52 having a width of 6,600 mm 3 and a gap of 8,400 mm 3.

Next, the SOG solution was spin-coated to form a third SOG film 54 having a thickness of about 3,800 to 4,500 kPa (for example, 4,200 kPa) to completely cover the metal layer patterns 52. In this case, the weight average molecular weight of the perhydro polysilazane included in the third SOG film 54 was about 3,000 to 6,000 (for example, 3,000).

Referring to FIG. 18K, after the third SOG film 54 is prebaked for about 1 to 5 minutes (for example, 3 minutes) in air at a temperature of about 100 to 500 kPa (for example, 150 kPa), Main bake for about 10 to 180 minutes (eg 30 minutes) at a temperature of 400 to 450 ° C. (eg 400 ° C.). At this time, the main baking is carried out in a steam atmosphere. Then, the Si—N bond of the third SOG film 54 is replaced with the Si—O bond through the curing process, and is converted to the third silicon oxide film 54a having a flat surface.

Then, the semiconductor element was completed through the normal semiconductor manufacturing process. Those skilled in the art will be able to manufacture semiconductor devices using the SOG compositions through methods in accordance with various embodiments of the present invention.

Examples 9-11

Preparation of SOG Composition

A silicon oxide film and a semiconductor device were manufactured using the SOG composition prepared in Example 4 and another SOG composition. More specifically, in Examples 9 to 11, silicon oxide films and semiconductor devices were manufactured using the SOG compositions prepared in Examples 5 to 7, respectively.

Comparative Example 2

Preparation of SOG Composition

Instead of the SOG composition prepared in Example 4, a silicon oxide film and a semiconductor device were manufactured according to the method of Example 8 using the SOG composition prepared in Comparative Example 1.

Formation investigation of substrate oxide

Experimental Example 6 (Number of Particles in SOG Composition)

The number of particles from 0.3 to 0.5 μm and more than 0.5 μm in 1 cc of the SOG composition prepared by Examples 4 to 7 and Comparative Example 1 was measured, and the results are shown in Table 2 and FIG. 19. 19 is a graph showing the number of particles (pieces / cc) according to a weight average molecular weight (Mw) according to an embodiment of the present invention. In this case, particle number was observed before curing the SOG composition. Similar numbers of liquid particles were present.

Example 4 Example 5 Example 6 Example 7 Comparative Example 1 Number of 0.5 μm liquid particles (pcs / cc) 0 0.1 0 0.1 0 Number of 0.3 ~ 0.5μm liquid particles (pcs / cc) 0.7 2 0.2 0.3 0.1

Experimental Example 7 (Light Absorption)

The light absorption of the second SOG film 50 and the second silicon oxide film 50a according to the eighth embodiment shown in FIG. 18I was measured by the FT-IR method. The light absorbency was measured after depositing the SOG composition and then performing a prebaking process at about 150 ° C. for 3 minutes. The general chemical composition of perhydro polysilazane is (SiH ₂ NH) _n . When the heat treatment is performed in an oxygen or steam atmosphere, the Si—N bonds, Si—H bonds, and NH bonds included in the SOG composition are separated to replace all the bonds with the Si—O bonds.

Changes in the FT-IR spectrum with curing temperature and molecular weight are shown in FIGS. 20 and 21. 20 is a graph showing light absorption (au) according to wave number (cm ⁻¹ ) measured after prebaking according to an embodiment of the present invention, and FIG. 21 is a main diagram according to an embodiment of the present invention. It is a graph showing the light absorption (au) according to the weight average molecular weight (Mw) and wave number (cm ^-1 ) measured after baking.

In FIG. 20, it can be seen that NH bonds, Si—H bonds, and Si—N bonds remain substantially even after prebaking. Referring to FIG. 20, absorption peaks representing NH bonds, Si—H bonds, and Si—N bonds in the wave range of 400 to 4000 cm ⁻¹ can be confirmed.

In addition, the prebaked SOG film was main baked again at a temperature of 700 ° C. for 30 minutes to convert the silicon oxide film, and then light absorption was measured by FT-IR. As shown in FIG. 21, in the main baking step, absorption peaks of N-H bonds, Si-H bonds, and Si-N bonds disappear, and only absorption peaks of Si-O bonds are shown. According to this, the Si-N bonds, Si-H bonds and N-H bonds included in the polysilazane-based SOG film may be confirmed that all of the Si-O bonds are substituted after the main baking process.

By the same experimental method, experiments were carried out for Examples 9 to 11 and Comparative Example 2 and the results are shown in FIGS. 20 and 21. According to this result, it confirmed that the characteristic as an excellent interlayer insulation film was shown irrespective of the weight average molecular weight of an experiment object.

Experimental Example 8 (thickness and shrinkage of the silicon oxide film)

The thickness of the oxide film after pre-baking and main baking was measured for the same SOG film and the same silicon oxide film as Experimental Example 7, and the shrinkage ratios thereof were calculated, and the results are shown in Table 3 and FIG. 22. 22 is a graph showing the thickness and shrinkage rate according to the weight average molecular weight after pre-baking and main baking according to an embodiment of the present invention.

The shrinkage rate is calculated by the following equation.

Shrinkage ratio = [thickness of SOG film after pre-baking-thickness of SOG film after pre-baking] / [thickness of SOG film after pre-baking] × 100

In the same manner, the same experiments were performed for Examples 9 to 11 and Comparative Example 2, and the results are shown in Table 3 and FIG. 22. As can be seen in Table 3 and FIG. 22, the thickness and shrinkage of the polysilazane-based SOG film showed the same behavior regardless of the weight average molecular weight.

Example 8 Example 9 Example 10 Example 11 Comparative Example 2 SOG film thickness after prebaking 7896 7781 7509 7784 7715 Thickness of SOG Film after Main Baking 6150 6010 5888 6042 5986 Shrinkage (%) 22.1 22.8 21.6 22.4 22.4

Experimental Example 9 (Unevenness in Wafer)

With the wafer non-uniformity (WIWNU) after pre-baking and main baking for the same SOG film and the same silicon oxide film as Experimental Example 8 was measured, the results are summarized in Table 4 and FIG. . The same experiment was conducted for Examples 9 to 11 and Comparative Example 2 in the same manner, and the results are shown in Table 4 and FIG. 23. FIG. 23 is a graph illustrating WIWNU according to a weight average molecular weight according to an embodiment of the present invention. FIG. After performing pre-baking and main baking as can be seen in Table 4 and FIG. 23 below, the WIWNU of the membrane showed a very good value of less than 2.5% regardless of the weight average molecular weight.

Example 8 Example 9 Example 10 Example 11 Comparative Example 2 WIWNU (%) after prebaking 1.0 1.99 0.8 0.81 0.82 WIWNU (%) after main baking 1.83 2.21 0.81 1.05 0.79

Experimental Example 10 (normalized particle number and scratch number of silicon oxide film)

For the same SOG composition and the same silicon oxide film as Experimental Example 8, the normalized particle number and scratch number of the silicon oxide film after prebaking and main baking were measured. The results are summarized in Table 5 below and FIG. 24. The same experiment was conducted for Examples 9 to 11 and Comparative Example 2 in the same manner, and the results are shown in Table 5 and FIG. 24. 24 is a graph showing the number of normalized particles and scratches according to the weight average molecular weight according to one embodiment of the present invention. At this time, the standard for particle number normalization was when the molecular weight was 4500.

As can be seen in Table 5 and FIG. 24, the smallest number of particles and scratches in the oxide film was measured when the molecular weight was 3,500 or 4,500. Compared with the fact that the particle number in the SOG composition measured in Experimental Example 6 was not significantly different depending on the weight average molecular weight, it was confirmed that the generation of particles was particularly suppressed under the oxide film forming conditions of the present invention.

Example 8 Example 9 Example 10 Example 11 Comparative Example 2 Number of particles after prebaking (a.u.) 2.61 1.16 1.0 1.86 1.16 Number of particles after main baking (a.u.) 2.39 1.06 1.0 1.54 1.15 Scratch count 13 0.8 0.6 3.6 16

In summary, the results of the above examples and comparative examples are excellent in terms of particle number, shrinkage ratio and WIWNU in spin-on glass, but considering the particle and scratch generation aspect, when the weight average molecular weight is about 3000 to 6000, As well as other properties, it was confirmed that the particle suppression properties are also excellent.

Even after the conventional SOG solution is cured by baking, many particles still remain in the silicon oxide film. Specifically, for example, in order to cure the SOG solution, in the process of annealing the SOG solution applied on the substrate, outgassing SiH ₄ reacts with an oxidizing atmosphere gas to form particles such as SiO ₂ to contaminate the reaction chamber. Will be.

These particles have a size of several tens of nm or more, and act as a contaminant in a subsequent wafer annealing process, causing damage to the semiconductor device. If the polysilazane coating film is formed thicker around the particles, and thus the thickness of the coating film after annealing is formed to be greater than or equal to the maximum crack free thickness of 15,000 μs or more, there is a problem inevitably causing cracks.

 By using the SOG composition according to the present invention, it is possible to form a void-free silicon oxide film while maintaining the flatness required in a 256 megabit semiconductor device. In addition, in order to suppress the oxidation of silicon in the active region, the SOG composition can be converted to silicon oxide by the first heat treatment process, and the converted silicon oxide can be densified to ensure the stability of numerical values.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (34)

The structural formula is-(SiH ₂ NH) _n- (where n is a positive integer), has a weight average molecular weight of 3,300 to 3,700, and 10 to 30% by weight of polysilazane relative to the total weight of the composition; And Spin-on-glass composition comprising 70 to 90% by weight of the solvent. delete delete The spin-on-glass composition of claim 1, wherein the polysilazane has a molecular weight distribution of 2.5 to 3.5. The spin on glass composition according to claim 1, wherein the polysilazane has a molecular weight distribution of 2.8 to 3.2. The spin-on-glass composition of claim 1, wherein the solvent is xylene or dibutyl ether. The spin-on glass composition of claim 1, wherein the composition has a viscosity of 1.54 to 1.70 cP. The spin-on-glass composition of claim 1, wherein a contact angle with respect to the lower layer to which the composition is applied is 4 ° or less. The spin-on-glass composition of claim 1, wherein the composition further comprises at least one impurity selected from the group consisting of boron, fluorine, phosphorus, arsenic, carbon, and oxygen. The structural formula is-(SiH ₂ NH) _n- (wherein n is a positive integer) on a semiconductor substrate having a stepped portion formed on the upper surface, and has a weight average molecular weight of 3,300 to 3,700, and 10 to about the total weight of the composition. Applying a spin on glass composition comprising 30 wt% polysilazane and 70 to 90 wt% solvent to form a spin on glass film; And Curing the spin-on-glass film to form a silicon oxide film. The method of claim 10, wherein the stepped portion is formed by at least two conductive patterns. The method of claim 11, wherein the distance between the two conductive patterns is 0.04 to 1 μm. 12. The method of claim 11, wherein the two conductive patterns are a gate electrode or a metal wiring pattern of a semiconductor device. The method of claim 10, wherein the aspect ratio of the stepped portion between the two conductive patterns is 5: 1 to 10: 1. The method of claim 10, wherein the stepped portion comprises a dense stepped portion having an aspect ratio of 5: 1 to 10: 1 and a global stepped portion having an aspect ratio of 1: 1 or less. The method of claim 10, wherein the composition 20 to 23 weight percent of the polysilazane; And A silicon oxide film forming method comprising 77 to 80% by weight of the solvent. delete The method of claim 10, wherein the molecular weight distribution of the polysilazane is 2.5 to 3.5. The method of claim 10, wherein the molecular weight distribution of the polysilazane is 2.8 to 3.2. The method of claim 10, wherein the composition has a viscosity of 1.54 to 1.70 cP. The method of claim 10, wherein curing the spin-on glass film comprises Prebaking the spin-on glass film at a temperature of 100 to 500 ° C .; And Main baking the spin-on glass film at a temperature of 400 to 1200 ℃. 22. The method of claim 21, wherein the prebaking is performed for 1 to 5 minutes in an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of oxygen and steam, a nitrogen atmosphere, or a mixed atmosphere of oxygen, steam, and nitrogen. 22. The method of claim 21, wherein the main baking is performed for 10 to 180 minutes in an oxygen atmosphere, a steam atmosphere, a mixed atmosphere of oxygen and steam, a nitrogen atmosphere, or a mixed atmosphere of oxygen, steam, and nitrogen. The method of claim 10, wherein the oxide film has a thickness of 1,000 to 10,000 kPa. The method of claim 10, wherein the stepped portion is formed by forming a plurality of gate electrodes on the semiconductor substrate, The spin on glass film is formed by coating the spin on glass composition on the substrate to cover the gate electrodes, Curing the spin-on glass film may include pre-baking the spin-on glass film at a temperature of 100 to 500 ° C., and main baking of the spin-on glass film at a temperature of 400 to 1200 ° C. Silicon oxide film formation method. The method of claim 10, wherein the stepped portion is formed by forming an insulating film on the substrate, and then forming a plurality of metal wiring patterns on the insulating film, The spin-on-glass film is formed by coating the spin-on-glass solution on a fraudulent substrate to cover the metal wiring pattern, Curing the spin-on glass film may include prebaking the spin-on glass film at a temperature of 100 to 500 ° C. and main baking of the spin-on glass film at a temperature of 400 to 1200 ° C. Silicon oxide film formation method. The method of claim 10, further comprising forming a silicon nitride film on the semiconductor substrate to a thickness of 200 to 600 kPa before applying the spin on glass composition. At least one flat film made of a spin-on-glass composition, The spin on glass composition The structural formula is-(SiH ₂ NH) _n- (wherein n is a positive integer), the weight average molecular weight is 3,300 to 3,700, and 10 to 30% by weight of polysilazane, based on the total composition; And A semiconductor device comprising 70 to 90% by weight of the solvent. delete A semiconductor device according to claim 28, wherein said solvent is xylene or dibutyl ether. The method of claim 28, wherein the spin-on glass composition 20 to 23 weight percent of the polysilazane; And A semiconductor device comprising 77 to 80% by weight of the solvent. The semiconductor device according to claim 28, wherein the spin on glass composition has a viscosity of 1.54 to 1.70 cP. 29. The semiconductor device according to claim 28, wherein the spin on glass composition has a contact angle of 4 ° or less with respect to a film formed under the composition. 29. The semiconductor device of claim 28, wherein the spin-on-glass composition further comprises an impurity comprising at least one element selected from the group consisting of boron, fluorine, phosphorus, arsenic, carbon and oxygen.

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