CN111599869A - Thin film transistor and thin film transistor preparation method - Google Patents

Thin film transistor and thin film transistor preparation method Download PDF

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Publication number
CN111599869A
CN111599869A CN202010463760.1A CN202010463760A CN111599869A CN 111599869 A CN111599869 A CN 111599869A CN 202010463760 A CN202010463760 A CN 202010463760A CN 111599869 A CN111599869 A CN 111599869A
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layer
alloy film
barrier layer
alloy
barrier
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胡小波
谭敏力
彭钊
刘健
杨一峰
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TCL China Star Optoelectronics Technology Co Ltd
TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The thin film transistor provided by the embodiment of the invention comprises a substrate, an active layer positioned above the substrate, a gate insulating layer positioned on the active layer, a first barrier layer, a gate electrode, a second barrier layer and a first alloy film layer positioned on the second barrier layer, wherein the first barrier layer, the gate electrode and the second barrier layer are stacked on the gate insulating layer; the first alloy film layer is arranged on the second barrier layer, so that the bonding force between the three-layer metal structure and the light resistance layer is enhanced, and the light resistance layer is prevented from being peeled off in the preparation process.

Description

Thin film transistor and thin film transistor preparation method
Technical Field
The invention relates to the technical field of OLED display, in particular to a thin film transistor and a preparation method of the thin film transistor.
Background
The existing thin film transistor generally adopts a three-layer metal structure to prevent a dielectric layer from peeling off, the barrier layer on the uppermost layer of the three-layer metal structure has stronger hydrophilicity and weaker bonding force with a photoresist layer arranged on the barrier layer, so the technical problem that the photoresist layer is easy to peel off exists in the preparation process of the existing thin film transistor.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor preparation method and a thin film transistor, which can solve the technical problem that a photoresist layer is easy to peel off in the existing thin film transistor preparation process.
The present invention provides a thin film transistor, including:
the transistor comprises a substrate, an active layer positioned above the substrate, a gate insulating layer positioned on the active layer, a first blocking layer positioned on the gate insulating layer, a gate positioned on the first blocking layer and a second blocking layer positioned on the gate; and
a first alloy film layer on the second barrier layer; and
the interlayer insulating layer is positioned on the first alloy film layer, a source electrode and a drain electrode are arranged on the interlayer insulating layer, and passivation layers are arranged on the source electrode and the drain electrode;
the hydrophobicity of the first alloy film layer is greater than that of the second barrier layer, and the first alloy film layer is used for preventing the photoresist layer from being peeled off in the preparation process.
In the thin film transistor provided in the embodiment of the present invention, the upper surfaces of the source electrode and the drain electrode are provided with a fourth blocking layer, the lower surfaces of the source electrode and the drain electrode are provided with a third blocking layer, and the fourth blocking layer is provided with a second alloy film layer.
In the thin film transistor provided in the embodiment of the present invention, the material of the first alloy film layer is an alloy material formed by the material of the second barrier layer and ions of a material with good hydrophobicity, and the material of the second alloy film layer is an alloy material formed by the material of the fourth barrier layer and ions of a material with good hydrophobicity.
In the thin film transistor provided by the embodiment of the present invention, the material of the first alloy film layer or the second alloy film layer is an alloy of molybdenum, tantalum and carbon, and the mass of the carbon accounts for 0.1% to 10% of the mass of the alloy.
In the thin film transistor provided in the embodiment of the present invention, a thickness of the first alloy film layer or the second alloy film layer is any one of 10 angstroms to 200 angstroms.
The embodiment of the invention provides a preparation method of a thin film transistor, which is characterized by comprising the following steps:
providing a substrate;
sequentially forming a light shielding layer, a buffer layer and an active layer on the substrate;
forming a grid electrode insulating layer on the active layer, and sequentially forming a three-layer metal structure of a first barrier layer, a grid electrode and a second barrier layer on the grid electrode insulating layer;
processing the surface of the second barrier layer by using ion implantation of a hydrophobic material to form a first alloy film layer with hydrophobicity stronger than that of the second barrier layer, wherein the first alloy film layer is more tightly combined with the light resistance layer;
and sequentially forming an interlayer insulating layer, a source electrode, a drain electrode and a passivation layer on the first alloy film layer.
In the method for manufacturing a thin film transistor provided in the embodiment of the present invention, in the step of processing the surface of the second barrier layer using hydrophobic material ions:
and treating the surface of the second barrier layer by using carbon ion implantation, wherein the material for forming the first alloy film layer is an alloy of molybdenum, tantalum and carbon.
In the method for manufacturing a thin film transistor provided in the embodiment of the present invention, in the step of processing the surface of the second barrier layer using hydrophobic material ions:
and treating the surface of the second barrier layer by using copper ion implantation, wherein the material for forming the first alloy film layer is an alloy of molybdenum, tantalum and copper.
In the method for manufacturing a thin film transistor according to the embodiment of the present invention, in the step of sequentially forming an interlayer insulating layer, a source electrode, a drain electrode, and a passivation layer on the first alloy film layer:
and forming third barrier layers on the lower surfaces of the source electrode and the drain electrode, forming fourth barrier layers on the upper surfaces of the source electrode and the drain electrode, and forming a second alloy film layer on the upper surface of the fourth barrier layer.
In the method for manufacturing a thin film transistor according to the embodiment of the present invention, in the step of forming the second alloy film layer on the upper surface of the fourth barrier layer:
and treating the surface of the fourth barrier layer by using carbon ion implantation, wherein the second alloy film layer is formed by an alloy of molybdenum, tantalum and carbon.
Has the advantages that: the thin film transistor provided by the embodiment of the invention comprises a substrate, an active layer positioned above the substrate, a gate insulating layer positioned on the active layer, a first barrier layer, a gate electrode, a second barrier layer, a first alloy film layer positioned on the second barrier layer and an interlayer insulating layer positioned on the first alloy film layer, wherein the first barrier layer, the gate electrode and the second barrier layer are arranged on the gate insulating layer in a stacking manner; the first alloy film layer is arranged on the second barrier layer, so that the photoresist layer above the grid electrode can be prevented from peeling off, and the technical problem that the photoresist layer is easy to peel off in the existing thin film transistor preparation process is solved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic cross-sectional view of an OLED display panel according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the invention;
fig. 4 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
As shown in fig. 1 and fig. 2, a thin film transistor 2 according to an embodiment of the present invention includes a substrate 10, an active layer 203 located over the substrate 10, a gate insulating layer 204 located on the active layer 203, a first barrier layer 2051 located on the gate insulating layer 204, a gate electrode 2052 located on the first barrier layer 2051, a second barrier layer 2053 located on the gate electrode 2052, a first alloy film layer 2054 located on the second barrier layer 2053, and an interlayer insulating layer 206 located on the first alloy film layer 2054, wherein a source electrode 2071 and a drain electrode 2072 are disposed on the interlayer insulating layer 206, and a passivation layer 208 is disposed on the source electrode 2071 and the drain electrode 2072, wherein the hydrophobicity of the first alloy film layer 2054 is greater than that of the second barrier layer 2053 for preventing the photoresist layer from peeling off during a manufacturing process.
The thin film transistor 2 provided by the embodiment of the invention comprises a substrate 10, an active layer 203 located above the substrate 10, a gate insulating layer 204 located on the active layer 203, a first barrier layer 2051 located on the gate insulating layer 204, a gate electrode 2052 located on the first barrier layer 2051, a second barrier layer 2053 located on the gate electrode 2052, a first alloy film layer 2054 located on the second barrier layer 2053, and an interlayer insulating layer 206 located on the first alloy film layer 2054, wherein a source electrode 2071 and a drain electrode 2072 are arranged on the interlayer insulating layer 206, and passivation layers 208 are arranged on the source electrode 2071 and the drain electrode 2072, wherein the hydrophobicity of the first alloy film layer 2054 is greater than that of the second barrier layer 2053, so as to prevent the photoresist layer from peeling off in a preparation process; by arranging the first alloy film layer 2054 on the second barrier layer 2053, the photoresist layer above the gate electrode 2052 can be prevented from peeling off, and the technical problem that the photoresist layer is easy to peel off in the existing thin film transistor preparation process 2 is solved.
Fig. 2 is a schematic cross-sectional view of the OLED display panel 1, and fig. 2 and 3 are schematic cross-sectional views of the thin film transistor 2 provided in the present invention.
Wherein the source drain 207 layer includes a source 2071 and a drain 2072.
Wherein the active layer 203 includes a channel region, a source 2071 contact region and a drain 2072 contact region.
Wherein the source drain 207 layer includes a source 2071 and a drain 2072.
Wherein a passivation layer 208 is disposed on the source drain 207 layer.
Wherein, the color resistance layer and the flat layer 209 are arranged on the passivation layer 208.
The light emitting function layer is disposed on the flat layer 209, and the light emitting function layer sequentially includes, from bottom to top, a first electrode layer 401, a light emitting layer 402, and a second electrode layer 403.
Wherein the pixel defining layer 30 is disposed on the first electrode layer 401
Wherein the encapsulation layer 50 is disposed on the second electrode layer 403.
The Mo, MoTi, Ti, W, Ta and Mo Alloy are molybdenum, molybdenum titanium, tungsten, tantalum and molybdenum Alloy respectively.
Wherein the alloy of molybdenum tantalum and carbon is MoTa-C, and the alloy of molybdenum tantalum and copper is MoTa-Cu.
In one embodiment, the source and drain electrodes 2071 and 2072 are provided with a fourth barrier layer 2074 on the upper surface, and the source and drain electrodes 2071 and 2072 are provided with a third barrier layer 2073 on the lower surface, wherein a second alloy film layer 2075 is provided on the fourth barrier layer 2074.
In one embodiment, the material of the first alloy film layer 2054 is an alloy material formed by ions of a material with good hydrophobicity and the material of the second alloy film layer 2075 is an alloy material formed by ions of a material with good hydrophobicity and the material of the fourth barrier layer 2074.
In one embodiment, the fourth barrier layer 2074 is made of any one of Mo, MoTi, Ti, W, Ta, and Mo Alloy.
In one embodiment, the second alloy film layer 2075 is formed by C ion implantation.
When the preparation material of the fourth barrier layer 2074 is Mo, the material of the first alloy film layer 2054 is Mo — C;
when the fourth barrier layer 2074 is made of MoTi, the first alloy film layer 2054 is made of MoTi-C;
when the fourth barrier layer 2074 is made of Ti, the first alloy film layer 2054 is made of Ti-C;
when the fourth barrier layer 2074 is made of W, the first alloy film layer 2054 is made of W-C;
when the fourth barrier layer 2074 is made of Ta, the first alloy film layer 2054 is made of Ta-C;
when the fourth barrier layer 2074 is made of Mo Alloy, the first Alloy film layer 2054 is made of Mo Alloy-C.
In one embodiment, the second alloy film layer 2075 is formed by Cu ion implantation.
When the preparation material of the fourth barrier layer 2074 is Mo, the material of the first alloy film layer 2054 is Mo — Cu;
when the preparation material of the fourth barrier layer 2074 is MoTi, the material of the first alloy film layer 2054 is MoTi-Cu;
when the fourth barrier layer 2074 is made of Ti, the first alloy film layer 2054 is made of Ti — Cu;
when the fourth barrier layer 2074 is made of W, the first alloy film layer 2054 is made of W — Cu;
when the fourth barrier layer 2074 is made of Ta, the first alloy film layer 2054 is made of Ta — Cu;
when the fourth barrier layer 2074 is made of Mo Alloy, the first Alloy film layer 2054 is made of Mo Alloy-Cu.
In one embodiment, the material of the first alloy film layer or the second alloy film layer is an alloy of molybdenum, tantalum and carbon, and the mass of the carbon accounts for 0.1-10% of the mass of the alloy.
Wherein the proportion of C may be 0.1%.
Wherein the proportion of C may be 10%.
In one embodiment, the second barrier layer 2053 is made of any one of Mo, MoTi, Ti, W, Ta, and Mo Alloy.
In one embodiment, the first alloy film layer 2054 is formed by C ion implantation.
When the second barrier layer 2053 is made of Mo, the first alloy film layer 2054 is made of Mo — C;
when the second barrier layer 2053 is made of MoTi, the first alloy film layer 2054 is made of MoTi-C;
when the second barrier layer 2053 is made of Ti, the first alloy film layer 2054 is made of Ti-C;
when the second barrier layer 2053 is made of W, the first alloy film layer 2054 is made of W-C;
when the second barrier layer 2053 is made of Ta, the first alloy film layer 2054 is made of Ta — C;
when the second barrier layer 2053 is made of Mo Alloy, the first Alloy film layer 2054 is made of Mo Alloy-C.
In one embodiment, the first alloy film layer 2054 is formed by Cu ion implantation.
When the preparation material of the second barrier layer 2053 is Mo, the material of the first alloy film layer 2054 is Mo — Cu;
when the preparation material of the second barrier layer 2053 is MoTi, the material of the first alloy film layer 2054 is MoTi-Cu;
when the second barrier layer 2053 is made of Ti, the first alloy film layer 2054 is made of Ti — Cu;
when the second barrier layer 2053 is made of W, the first alloy film layer 2054 is made of W-Cu;
when the second barrier layer 2053 is made of Ta, the first alloy film layer 2054 is made of Ta — Cu;
when the second barrier layer 2053 is made of Mo Alloy, the first Alloy film layer 2054 is made of Mo Alloy-Cu.
In one embodiment, the thickness of the first alloy film layer 2054 and the second alloy film layer 2075 is any value from 10 angstroms to 200 angstroms.
In one embodiment, the liquid crystal display further comprises a color resistance layer arranged on the flat layer 209, wherein the material of the color resistance layer is a color resistance organic material.
In one embodiment, the planarization layer 209 is an organic material, and the planarization layer 209 is disposed on the color resist layer.
In one embodiment, the first electrode layer 401 may be an anode, and the material of the first electrode layer 401 is indium tin oxide, silver, or an indium tin oxide material, or other anode materials.
In one embodiment, the material of the pixel electrode layer is a hydrophobic material.
In one embodiment, the light-emitting layer 402 further comprises an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
In one embodiment, the encapsulation layer 50 includes a first inorganic layer, a first organic layer, and a second inorganic layer.
Wherein the first inorganic layer is disposed over the second electrode layer 403.
In one embodiment, the source 2071 has a vertical cross-sectional shape of any one of a triangle, a rectangle or an arc.
In one embodiment, the drain 2072 has a vertical cross-section in the shape of any one of a triangle, a rectangle or an arc.
In one embodiment, the material of the active layer 203 comprises indium.
In one embodiment, the material of the active layer 203 further comprises zinc.
In one embodiment, the longitudinal cross-sectional shape of the source 2071 and the drain 2072 comprises a trapezoid.
In one embodiment, as shown in fig. 3, the gate electrode 2052 is disposed below the active layer 203 in a bottom gate configuration.
A fourth barrier layer 2074 is disposed on the source and drain electrodes 2071 and 2072, a second alloy film layer 2075 is formed on the fourth barrier layer 2074, and the hydrophobicity of the second alloy film layer 2075 is greater than that of the fourth barrier layer 2074.
A second barrier layer 2053 is disposed on the gate electrode 2052, a first alloy film layer 2054 is disposed on the second barrier layer 2053, and the hydrophobicity of the first alloy film layer 2054 is greater than that of the second barrier layer 2053.
As shown in fig. 4, the method for manufacturing the thin film transistor 2 according to the embodiment of the present invention includes:
s1, providing a substrate 10;
s2, forming a light-shielding layer 201, a buffer layer 202, and an active layer 203 on the substrate 10 in sequence;
s3, forming a gate insulating layer 204 on the active layer 203, and sequentially forming a three-layer metal structure of a first barrier layer 2051, a gate 2052 and a second barrier layer 2053 on the gate insulating layer 204;
s4, processing the surface of the second barrier layer 2053 by using ion implantation of a hydrophobic material to form a first alloy film layer 2054 with hydrophobicity stronger than that of the second barrier layer 2053, wherein the first alloy film layer 2054 is more tightly combined with the photoresist layer;
s5, an interlayer insulating layer 206, a source and drain electrodes 2071 and 2072, and a passivation layer 208 are sequentially formed on the first alloy film 2054.
Since the photoresist layer is removed before the passivation layer is formed, the photoresist layer does not exist in the film structure shown in fig. 2, and the illustration is only used for convenience of description.
In one embodiment, in the step of treating the surface of the second barrier layer 2053 with hydrophobic material ions: the surface of the second barrier layer 2053 is treated by C ion implantation, and the material forming the first alloy film layer 2054 is an alloy of molybdenum, tantalum, and carbon.
The second barrier layer 2053 is made of MoTa.
In one embodiment, in the step of treating the surface of the second barrier layer 2053 with hydrophobic material ions: the surface of the second barrier layer 2053 is treated by Cu ion implantation, and the material forming the first alloy film layer 2054 is an alloy u of molybdenum, tantalum, and carbon.
The second barrier layer 2053 is made of MoTa.
In one embodiment, in the step of sequentially forming the interlayer insulating layer 206, the source and drain electrodes 2071 and 2072 and the passivation layer 208 on the first alloy film layer 2054: a third barrier layer 2073 is formed on the lower surfaces of the source and drain electrodes 2071 and 2072, a fourth barrier layer 2074 is formed on the upper surfaces of the source and drain electrodes 2071 and 2072, and a second alloy film layer 2075 is formed on the upper surface of the fourth barrier layer 2074.
In one embodiment, in the step of forming the second alloy film layer 2075 on the upper surface of the fourth barrier layer 2074: the surface of the fourth barrier layer 2074 is treated by C ion implantation, and the second alloy film 2075 is formed of an alloy of molybdenum, tantalum and carbon.
The fourth barrier layer 2074 is made of MoTa.
The thin film transistor provided by the embodiment of the invention comprises a substrate, an active layer positioned above the substrate, a gate insulating layer positioned on the active layer, a first barrier layer positioned on the gate insulating layer, a gate positioned on the first barrier layer, a second barrier layer positioned on the gate, a first alloy film layer positioned on the second barrier layer, and a light resistance layer positioned on the first alloy film layer, wherein an interlayer insulating layer is arranged on the light resistance layer, a source electrode and a drain electrode are arranged on the interlayer insulating layer, and passivation layers are arranged on the source electrode and the drain electrode, wherein the hydrophobicity of the first alloy film layer is greater than that of the second barrier layer, so that the light resistance layer is prevented from being peeled off in the preparation process; the first alloy film layer is arranged on the second barrier layer, so that the photoresist layer above the grid electrode can be prevented from peeling off, and the technical problem that the photoresist layer of the existing thin film transistor is easy to peel off is solved.
The foregoing detailed description is provided for one of the embodiments of the present invention, and the principle and the implementation of the present invention are explained herein by applying specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A thin film transistor, comprising:
the transistor comprises a substrate, an active layer positioned above the substrate, a gate insulating layer positioned on the active layer, a first blocking layer positioned on the gate insulating layer, a gate positioned on the first blocking layer and a second blocking layer positioned on the gate; and
a first alloy film layer on the second barrier layer; and
the interlayer insulating layer is positioned on the first alloy film layer, a source electrode and a drain electrode are arranged on the interlayer insulating layer, and passivation layers are arranged on the source electrode and the drain electrode;
the hydrophobicity of the first alloy film layer is greater than that of the second barrier layer, and the first alloy film layer is used for preventing the photoresist layer from being peeled off in the preparation process.
2. The thin film transistor according to claim 1, wherein a fourth barrier layer is disposed on the upper surface of the source electrode and the drain electrode, and a third barrier layer is disposed on the lower surface of the source electrode and the drain electrode, and wherein a second alloy film layer is disposed on the fourth barrier layer.
3. The thin film transistor according to claim 2, wherein the material of the first alloy film layer is an alloy material of a material of the second barrier layer and ions of a material with good hydrophobicity, and the material of the second alloy film layer is an alloy material of a material of the fourth barrier layer and ions of a material with good hydrophobicity.
4. The thin film transistor according to claim 3, wherein a material of the first alloy film layer or the second alloy film layer is an alloy of molybdenum tantalum and carbon, and a ratio of the mass of the carbon to the mass of the alloy is in a range of 0.1% to 10%.
5. The thin film transistor according to claim 2, wherein a thickness of the first alloy film layer or the second alloy film layer is any one of 10 to 200 angstroms.
6. A method for preparing a thin film transistor is characterized by comprising the following steps:
providing a substrate;
sequentially forming a light shielding layer, a buffer layer and an active layer on the substrate;
forming a grid electrode insulating layer on the active layer, and sequentially forming a three-layer metal structure of a first barrier layer, a grid electrode and a second barrier layer on the grid electrode insulating layer;
processing the surface of the second barrier layer by using ion implantation of a hydrophobic material to form a first alloy film layer with hydrophobicity stronger than that of the second barrier layer, wherein the first alloy film layer is more tightly combined with the light resistance layer;
and sequentially forming an interlayer insulating layer, a source electrode, a drain electrode and a passivation layer on the first alloy film layer.
7. The method for manufacturing a thin film transistor according to claim 6, wherein in the step of treating the surface of the second barrier layer with hydrophobic material ions:
and treating the surface of the second barrier layer by using carbon ion implantation, wherein the material for forming the first alloy film layer is an alloy of molybdenum, tantalum and carbon.
8. The method for manufacturing a thin film transistor according to claim 6, wherein in the step of treating the surface of the second barrier layer with hydrophobic material ions:
and treating the surface of the second barrier layer by using copper ion implantation, wherein the material for forming the first alloy film layer is an alloy of molybdenum, tantalum and copper.
9. The method for manufacturing a thin film transistor according to claim 6, wherein in the step of sequentially forming an interlayer insulating layer, a source electrode and a drain electrode, and a passivation layer on the first alloy film layer:
and forming third barrier layers on the lower surfaces of the source electrode and the drain electrode, forming fourth barrier layers on the upper surfaces of the source electrode and the drain electrode, and forming a second alloy film layer on the upper surface of the fourth barrier layer.
10. The method for manufacturing a thin film transistor according to claim 9, wherein in the step of forming the second alloy film layer on the upper surface of the fourth barrier layer:
and treating the surface of the fourth barrier layer by using carbon ion implantation, wherein the second alloy film layer is formed by an alloy of molybdenum, tantalum and carbon.
CN202010463760.1A 2020-05-27 2020-05-27 Thin film transistor and thin film transistor preparation method Pending CN111599869A (en)

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Application publication date: 20200828