JPH05128893A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve a yield rate in replacement by controlling a replacing signal from a redundant replacement circuit with a control signal and an address by a replacement control circuit and confirming the defect of a redundant storing circuit before a fuse is cut for replacement. CONSTITUTION:Zero is outputted always from the replacing signal SX from the redundant replacement circuit 1 by the control of the replacement control circuit 4 before the fuse is cut. At this time, when the control signal SC is made 1, the address signal ADD is not stopped by the replacing signal SX' but fetched into the storing circuit 3. When the signal SC is made zero, any of the signal SX' becomes zero by the signal ADD, and the signal ADD to the circuit 3 is stopped and simultaneously one of four areas of the redundant storing circuit 2 is operated. After the fuse of the circuit 1 is cut, since the signal SC is not connected with anywhere, but is fixed to the circuit 1 by a high resistor P, and the presence of the replacement is switched by the signal ADD. Thus, the normal/defective condition of the circuit 2 and any area in the case of the defect is confirmed and the yield rate in the replacement is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit which has a redundant memory circuit and can be read and written at any time.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional semiconductor integrated circuit with a redundant memory circuit, which can be read from and written to at any time, has a redundant replacement circuit 1 for receiving an address signal ADD and a replacement signal SX, and the replacement circuit. Input the signal SX. It has a redundant memory circuit 2 and a memory circuit 3. Further, the replacement signal SX
The NAND circuit 2 which receives as input is input to the memory circuit 3.

A redundant replacement circuit 1 in which a fuse is blown so that a replacement operation is performed for a specific address signal ADD.
When the address signal ADD to be replaced is input to the redundant replacement circuit 1, the redundant replacement circuit 1 outputs the replacement signal SX.

As a result, the memory circuit 3 does not operate,
The redundant memory circuit 2 operates.

For the other address signals ADD, the replacement circuit 1 does not operate and the replacement signal SX is not output, so that the storage circuit 3 normally selected by the address signal ADD operates instead of the redundant storage circuit 2.

A line for the data signal DATA is connected to the redundant memory circuit 2 and the memory circuit 3.

[0007]

In such a conventional semiconductor integrated circuit, in order to replace the defective memory circuit with the redundant memory circuit 2, the replacement address should be measured and then replaced by cutting the fuse. Since the replacement circuit 1 operates only for the address signal, replacement is performed while it is unknown whether or not the redundant memory circuit 2 has a defect, and when the redundant memory circuit 2 has a defect. Has a problem that the semiconductor integrated circuit becomes defective.

An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit in which when a defective redundant memory circuit has a defective portion, it is not necessary to use this portion.

[0009]

The structure of a semiconductor integrated circuit of the present invention comprises: a redundant replacement circuit for receiving an address signal and outputting a replacement signal; and a replacement control circuit for controlling the replacement signal.
A memory circuit and a redundant memory circuit are provided.

According to the present invention, by inputting and controlling the replacement signal to the replacement control circuit, the replacement signal can be output and the redundant memory circuit can be operated without cutting the fuse.

[0011]

1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

In FIG. 1, the circuit according to the present embodiment has a redundancy replacement circuit 1, a redundancy storage circuit 2 and a storage circuit 3, a NAND circuit O receiving a replacement signal SX ', and a replacement signal S.
X, and a replacement control circuit 4 which receives the control signal SC and outputs a replacement signal SX '.

The replacement control circuit 4 includes inverter circuits A and B, NAND circuits C, D, E and F, NOR circuits G, H, I, J, K, L, M and N, and a high resistance P. Have and.

In this embodiment, the case where the redundant memory circuit 2 is divided into four areas will be described. The replacement signal SX output from the redundant replacement circuit 1 is
It always outputs "0". Control signal SC
When the control circuit SC is connected to the control pad (PAD) and the memory circuit 3 is to be operated, the address signal A
DD is taken into the memory circuit 3 without being stopped by the replacement signal SX '. When the redundant storage circuit 2 is operated, the replacement signal SX ′ is set when the control signal SC is set to “0”.
Will be "0" depending on the address signal ADD,
The address signal ADD to the storage circuit 3 is stopped, and one of the four areas of the redundant storage circuit 2 operates. This makes it possible to confirm which area is good or bad and the area of the redundant storage circuit 2. After the fuse of the redundant replacement circuit 1 is blown, the control signal SC is not connected to anything, so that the control signal SC is fixed at "1" by the high resistance P, and the replacement is switched by the address signal ADD.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In FIG. 2, in the present embodiment, the replacement control circuit 4'includes a semiconductor integrated circuit control signal CS and an address signal ADD.
With, it is possible to set which of the storage circuit 3 and the redundant storage circuit 2 is to be operated. Which region of the redundant memory circuit 2 is to be operated is determined by the address signal ADD after the above setting.

After the fuse of the redundant replacement circuit 1 is cut, a fuse is provided inside the replacement control circuit 4'so that the replacement control circuit 4'will not operate, and the fuse is cut together after the fuse of the redundant replacement circuit 1 is cut. Memory circuit 3
The operation of the redundant memory circuit 2 is not selected.

[0018]

As described above, according to the present invention, the good / defective of the redundant memory circuit and its area can be confirmed before the fuse is blown, so that the defective redundant memory circuit is replaced with the memory circuit. Since this can be avoided, there is an effect that the non-defective rate of the semiconductor integrated circuit can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit with a conventional redundant memory circuit that can be read from and written to at any time.

[Explanation of symbols]

 1 redundant replacement circuit 2 redundant storage circuit 3 storage circuit 4, 4'replacement control circuit A, B inverter circuit C, D, E, F, O, Q NAND circuit G, H, I, J, K, L, M, N NOR circuit P High resistance SX, SX 'Substitution signal ADD Address signal SC Control signal CS Semiconductor integrated circuit control signal DATA Data signal

Claims (2)

[Claims] 1. A semiconductor integrated circuit, comprising: a redundant memory circuit; and a redundant replacement circuit for replacing the redundant memory circuit with a defective memory circuit, capable of reading and writing at any time. Redundant memory control for controlling the output of the redundant replacement circuit. A semiconductor integrated circuit having a circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the redundant memory control circuit has a severable fuse.