JP2001067891A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a yield by adding a function of disabling a spare element to a redundancy control circuit for selecting which of an element and the spare element is to be used. SOLUTION: When a fuse of a disable fuse latch circuit 43 in a redundant word line-selecting circuit is cut once, it generates a state in which a (Vss) level is outputted. Irrespective of a state of the other fuse latch circuits and a state of address signals, an output signal of a logic circuit 45, namely, a signal ordering to activate a redundant word line becomes the Vss level at all times. In consequence of this, a redundant word line corresponding to the redundant word line-selecting circuit including the latch circuit 43 with the fuse cut cannot be used any more. When a redundant memory cell used as a replacement comes to fail, the failing redundant memory cell is disabled and then replaced with a different redundant memory cell not used yet.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art A redundant circuit used in a conventional semiconductor memory device will be described.

FIG. 18 is a block diagram showing a configuration of a conventional redundant circuit.

[0004] This redundant circuit has a fuse latch circuit 10
1, enable fuse latch circuit 102, comparison circuit 1
03 and a logic circuit 104. The fuse latch circuits 101 and the comparison circuits 103 are prepared by the number of addresses necessary for selecting one word line corresponding to a memory cell. The enable fuse latch circuit 102 is a fuse latch circuit for an enable fuse, and one is provided for each of the fuse latch circuit 101 and the comparison circuit 103.

An output signal of the fuse latch circuit 101 corresponding to each of the address signals A0, A1,..., An is input to the comparison circuit 103. Logic circuit 10
4, the output signal of each comparison circuit 103 and the output signal of the enable fuse latch circuit 102 are input. The logic circuit 104 outputs the result of the logic synthesis as the activation signal RWLEj of the redundant word line corresponding to the redundant memory cell. Then, the activation signal RW of this redundant word line
When LEj attains the Vcc level, the redundant memory cell is activated.

FIG. 19 is a circuit diagram of the fuse latch circuit 101.

In this fuse latch circuit 101, FIG.
When the fuse F101 is not blown by performing the initial sequence shown in (1) at the time of power-on, the reference voltage Vss level is output to the first output terminal, and the power supply voltage Vcc level is output to the second output terminal. . On the other hand, fuse F1
When 01 is disconnected, the Vcc level is output to the first output terminal and the Vss level is output to the second output terminal. In either case, this state is maintained unless the power is turned off. The enable fuse latch circuit 102 is also shown in FIG.
The signal FENBLj is output from the first output terminal.

FIG. 20 is a circuit diagram of the comparison circuit 103.

In the comparison circuit 103, the first output terminal of the fuse latch circuit 101 is at the Vss level, and the second output terminal is at the Vss level.
In the case of the cc level, that is, when the fuse F101 of the fuse latch circuit is not blown, the transfer gate circuit TG101 is inactivated and the clocked inverter circuit CV101 is activated. As a result, the comparison circuit 10
3 always outputs the inverted state of the address signal An as the comparison result signal FCOMPnj.

On the other hand, when the first output terminal of the fuse latch circuit is at the Vcc level and the second output terminal is at the Vss level, that is, when the fuse of the fuse latch circuit is cut, the transfer gate circuit TG101 is activated. Then, clocked inverter circuit CV101 is deactivated. As a result, the address signal An is directly used as the comparison result signal FCOM.
Output as Pnj. That is, the address signals A0, A
When the fuse F101 of the fuse latch circuit 101 corresponding to 1,..., An is not blown, the comparison result signal FCOMPnj becomes Vcc when the address signal is at the Vss level.
Level, and when the fuse F101 is blown, the comparison result signal goes to the Vcc level when the address signal is at the Vcc level.

FIG. 21 is a circuit diagram of the logic circuit 104.

This logic circuit 104 has N input terminals.
It comprises an AND circuit ND101 and an inverter circuit IV104 connected to the output terminal of the NAND circuit.
The output terminal of inverter circuit IV104 outputs an activation signal RWLEj for a redundant word line corresponding to the redundant memory cell. The NAND circuit ND101 has input terminals of the number obtained by adding one to the number of addresses necessary for selecting one redundant word line corresponding to a redundant memory cell. Signals FCOMP0j to FCO
MPnj and an output signal FENBLj of the enable fuse latch circuit 102 are input. Then, V is applied to all input terminals.
Only when the cc level is input, the activation signal RWLEj of the redundant word line of the logic circuit 104 becomes the Vcc level.

For example, the address required to select one word line in a DRAM is 4 bits (A0, A0).
1, A2, A3), and the address of the word line corresponding to the defective memory cell is A0 = Vcc, A1 = Vss, A2 = V
ss, A3 = Vcc. In this case, when replacing a defective memory cell with a redundant word line, the enable fuse in the fuse set corresponding to the redundant word line is cut off, and among the four address fuses, those corresponding to A0 and A3 Disconnect. That is,
Since the fuse is blown in the enable fuse latch circuit 102, the Vcc level is always held at the first output terminal. In the comparison circuit 103 corresponding to A1 and A2, since the fuse of the corresponding fuse latch circuit 101 is not blown, the comparison result signal FCOMPnj goes to the Vcc level when the address is at the Vss level. In the comparison circuit 103 corresponding to A0 and A3, the corresponding fuse latch circuit 1
01 is blown, the address is Vcc
In the case of the level, the comparison result signal becomes the Vcc level.

Thus, after the fuse is blown, the address signals of the defective word line (A0 = Vcc, A1 = Vss, A2
= Vss, A3 = Vcc)
All inputs of the D circuit ND101 are aligned at the Vcc level. As a result, the activation signal RWLEj of the redundant word line output from the logic circuit 104 becomes the Vcc level, and the redundant word line is activated.

When the redundant word line is used as described above,
The address information of the defective word line to be replaced is permanently retained by cutting the fuse. For this reason, the redundant word line whose fuse has been cut once and decided to be used is uniquely connected to the corresponding defective word line, and thereafter activated only when an address signal for selecting the corresponding defective word line is input. Will be done.

[0016]

In using this redundant memory cell, a test of the redundant memory cell itself is performed before replacement, and after confirming that there is no defect, the fuse is blown. Normally, replacement with a cell is performed.

However, a defective memory cell may be included in a redundant memory cell. In consideration of such a case, an erroneous memory cell is determined until the chip is finally determined to be a good or defective product. Therefore, there is a problem that the test result of the redundant memory cell must be held so that the redundant memory cell which is defective in the test is not used.

Since replacement is performed by selecting a normal redundant memory cell, no defect should normally occur after replacement. However, as described above, after actually replacing a defective memory cell, a redundant memory cell that was normal in a test may become a defective memory cell after undergoing various tests. For this reason, although the defective memory cell is replaced with the redundant memory cell, the chip may eventually become defective and the yield may be reduced.

In spite of the replacement with such redundant memory cells, other unused redundant memory cells often remain in a chip that eventually becomes defective. In the conventional redundant circuit as described above, the fuse is blown, and once the connection between the defective memory cell and the redundant memory cell is determined, it cannot be replaced with another redundant memory cell. Therefore, there is a problem in that an unused product is defective without using up unused redundant memory cells, thereby lowering the yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and has been made in advance to test a redundant memory cell by adding a function of disabling the use of the redundant memory cell to a conventional redundant circuit. The result can be stored in the redundant circuit itself, and even if a redundant memory cell once used becomes defective, the memory cell is disabled and replaced with an unused normal redundant memory cell It is an object of the present invention to provide a semiconductor memory device capable of improving the yield and improving the yield.

[0021]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises an element normally used for storing data and an element used when the element is a defective element. And a redundant element for selecting which of the element and the spare element to use in accordance with a result of comparison between an address stored in a programmable read-only storage unit and an externally input address. And a control circuit, wherein the redundant control circuit has a function of disabling the spare element.

In the semiconductor memory device configured as described above, by adding a function of disabling the use of the spare element to the redundant circuit, the test result of the redundant memory cell performed in advance can be stored in the redundant circuit itself. Even if a spare element once used becomes defective, the spare element is made unusable and replaced with an unused normal spare element, thereby improving the yield. be able to.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

As shown in FIG. 1, an address buffer 11 to which an address signal is input from the outside is provided with a row decoder 1.
2, the column decoder 13 and the redundancy control circuit 14, respectively. The row decoder 12 is connected to a word line driver 15 for raising a word line, and the column decoder 13 is connected to an I / O gate 16. The redundancy control circuit 14 is connected to the word line driver 15 for raising a word line and the redundant word line driver 17 for raising a redundant word line.

The memory cell section includes a memory cell array 18 in which memory cells which are normally used are arranged, a redundant memory cell array 19 in which redundant memory cells provided for replacing the memory cells in case of failure are arranged, and a sense cell. It has an amplifier 20 and an I / O gate 16. The memory cells in the memory cell array 18 are connected to word lines WL0, WL1,..., WLi, and the memory cells in the redundant memory cell array 19 are connected to a redundant word line RWL.
, RWL1,..., RWLj are connected. Also,
The I / O gate 16 is connected to an input buffer 21 used when inputting data and an output buffer 22 used when outputting data.

Next, the operation of the semiconductor memory device thus configured will be described.

The address buffer 11 temporarily stores an externally input address signal and outputs it to the row decoder 12, the column decoder 13, and the redundancy control circuit 14. The row decoder 12 selects a word line based on the input address signal, and outputs a word line selection signal for selecting the word line to the word line driver 15. The column decoder 13 selects a column select line (CSL) based on the input address signal, and outputs a column select signal for selecting the column select line (CSL) to the I / O gate 16.

The redundancy control circuit 14 compares the input address signal with the address programmed by the fuse and outputs a selection signal according to the comparison result.
This selection signal is input to each of the word line driver 15 and the redundant word line driver 17, and activates either the word line driver 15 or the redundant word line driver 17. As a result, either the word line or the redundant word line is activated. The redundancy control circuit 14 will be described later in detail.

In writing, the input buffer 22
Is written to a memory cell or a redundant memory cell via an I / O gate 16. In reading, data read from a memory cell or a redundant memory cell is output from the output buffer 22.

Next, the redundancy control circuit 14 provided in the semiconductor memory device will be described.

FIG. 2 is a circuit diagram showing a configuration of the redundancy control circuit.

The redundancy control circuit 14 includes redundant word lines RWL0, RWL1,.
, Redundant word line selection circuit for selecting RWLj
.., 31-j and the normal word lines WL0, WL1,.
... NOR circuit 3 for selecting whether to start WLi
And 2.

An externally input address signal is A0,
A1, A2,..., An. The redundant word line selection circuits 31-0 to 31-j are connected to one of the redundant word lines RWL0 to RWLj.
One line is provided corresponding to one line. Here, a case will be described in which one redundant word line selecting circuit is provided with one redundant word line. However, a case where one redundant word line selecting circuit is provided with a plurality of redundant word lines is described. But the same is true.

The redundant word line selecting circuit 31-0 to which the address signals A0 to An are input selects whether or not to activate the redundant word line RWL0 based on the address signal, and outputs a signal RW.
LE0 is output. The redundant word line selection circuit 31-1 to which the address signals A0 to An are input selects whether to activate the redundant word line RWL1 based on the address signal, and outputs a signal RWLE1. Similarly, the redundant word line selection circuits 31-2 to 31-j perform the same processing as described above, and
2 to RWLEj are output. Here, the signal R
WLE1 to RWLEj are set to “H” (Vcc
Level) and "L" (Vss level) when not activated.

Further, the signals RWLE0 to RWLEj are
The signals are input to the input terminals of the NOR circuit 32, respectively. The NOR circuit 32 outputs the signal NWLE = “H” to the word line driver 15 when the signals RWLE0 to RWLEj are all “L”, that is, when none of the redundant word lines is activated. When the signal NWLE is "H", the normal word line is enabled.

Next, details of the redundant word line selection circuit in the redundancy control circuit 14 will be described.

FIG. 3 is a block diagram showing a configuration of the redundant word line selection circuit.

The redundant word line selection circuits 31-0 to 31-j
, 41-n, enable fuse latch circuit 42, disable fuse latch circuit 43, comparison circuits 44-0, 44-1, ..., 44-n, respectively.
And a logic circuit 45.

The fuse latch circuits 41-0 to 41-n and the comparison circuits 44-0 to 44-n are prepared by the same number as the number of bits of the address signals A0 to An.

An address A0 is input to a first input terminal of the comparison circuit 44-0, and an output signal of the fuse latch circuit 41-0 corresponding to the address A0 is input to a second input terminal. Similarly, addresses A1 to An are input to first input terminals of the comparison circuits 44-1 to 44-n, respectively, and fuse latch circuits 44-1 to 4 corresponding to the addresses A1 to An are input to their second input terminals. 44-n output signals are input.

The logic circuit 45 includes comparison circuits 44-0 to 44
-n, the output signal of the enable fuse latch circuit 42, and the output signal of the disable fuse latch circuit 43, respectively. Then, the input signal is logically synthesized, and the redundant word line RWL0 is synthesized.
RWLE0 to RWLE0 that indicate whether to activate RWLj.
RWLEj are output. When the activation signal of the redundant word line attains the "H" level, the redundant word line is activated.

Next, details of the fuse latch circuit in the redundant word line selection circuit will be described.

FIG. 4 is a circuit diagram showing a configuration of the fuse latch circuit.

The fuse latch circuits 41-0, 41-1,...
41-n are, as shown in FIG. 4, an n-channel MOS transistor having one terminal supplied with the reference voltage Vss, a set signal FSET at the gate, and a source connected to the other terminal of the fuse F1. (Hereinafter referred to as nMOS transistor) NT1, a reset signal bFRST is supplied to the gate, the power supply voltage Vcc is supplied to the source, and the nMO transistor is supplied to the drain.
P-channel MOS transistor (hereinafter referred to as pMOS transistor) P to which the drain of S transistor NT1 is connected
T1 and the nMOS transistors NT1 and p
An inverter circuit IV1 to which a connection point with the MOS transistor PT1 is connected;
1 is connected to the output terminal of the inverter circuit I.
An inverter circuit IV2 to which an input terminal of V1 is connected, an output terminal of the inverter circuit IV1 to an input terminal,
An inverter circuit IV3 having an output terminal as a first output terminal of the fuse latch circuit is provided. Inverter circuit I
The output terminal of V1 becomes the second output terminal of the fuse latch circuit. Then, the signal FLATnj is output from the first output terminal, and the signal bFLATnj is output from the second output terminal.
The fuse F1 is a programmable read-only storage device, specifically, an electric fuse capable of electrically changing a circuit state (connection or disconnection), a laser fuse capable of cutting a circuit by a laser or the like, or E.
It consists of an EPROM or the like.

These fuse latch circuits 41-0 to 41-n are
By performing the initial sequence as shown in FIG. 5 at the time of power-on, if the fuse F1 is not blown, the Vss level is output to the first output terminal and the Vcc level is output to the second output terminal. . When the fuse F1 is cut, the Vcc level is output to the first output terminal, and the Vss level is output to the second output terminal. In either case, this state is maintained unless the power is turned off.

The enable fuse latch circuit 42
Is configured in the same manner as the fuse latch circuit as shown in FIG. 6, and a signal FENBLj is output from a first output terminal. No output is taken from the second output terminal.

Next, the details of the disable fuse latch circuit 43 in the redundant word line selection circuit will be described.

FIG. 7 is a circuit diagram showing a configuration of the disable fuse latch circuit.

The disable fuse latch circuit 4
3, a fuse F2 having one terminal supplied with the reference voltage Vss and a set signal FSET at the gate, as shown in FIG.
NMO with the other terminal of the fuse F2 connected to the source
The reset signal bFRS is applied to the S transistor NT2 and the gate.
T, the source voltage Vcc is supplied to the source, and the drain is connected to the drain of the nMOS transistor NT2.
A MOS transistor PT2, an inverter circuit IV4 having an input terminal connected to the contact point of the nMOS transistor NT2 and the pMOS transistor PT2, an input terminal connected to an output terminal of the inverter circuit IV4, and an output terminal connected to the inverter circuit IV4. It comprises an inverter circuit IV5 to which an input terminal is connected. Then, the output terminal of the inverter circuit IV4 becomes the output terminal of the disable fuse latch circuit. The signal bFDISj is output from this output terminal.

The disable fuse latch circuit 4
3 is an address fuse latch circuit 41-0 to 41-
n, or a configuration in which the inverter circuit IV3 is removed from the enable fuse latch circuit 42 for enabling. The output signal of the disable fuse latch circuit 43 is the same as the output signal from the second output terminal of the fuse latch circuit. Therefore, when the fuse F2 is not cut, the Vcc level is output, and when the fuse F2 is cut, the Vss level is output.

Next, the details of the comparison circuit in the redundant word line selection circuit will be described.

FIG. 8 is a circuit diagram showing the configuration of the comparison circuit.

The comparison circuits 44-0 to 44-n correspond to FIG.
As shown in the figure, an address signal is input to one end of the current path, and the output signal bFLATnj of the second output terminal of the fuse latch circuit and the nMOS
A transfer gate circuit TG1 to which the output signal FLATnj of the first output terminal of the fuse latch circuit is input is connected to the gate on the transistor side, an address signal is connected to the input terminal, and the other end of the current path of the transfer gate circuit is connected to the output terminal. And a clocked inverter circuit CV1.

FIG. 9 shows a circuit configuration of the clocked inverter circuit CV1. This clocked inverter circuit C
At V1, the output signal FL of the first output terminal of the fuse latch circuit is applied to the clock gate of the pMOS transistor PT3.
ATnj is input, and the output signal bFLATnj of the second output terminal of the fuse latch circuit is input to the clock gate of the nMOS transistor NT3. Further, an address signal is input to an input terminal of an inverter circuit including the pMOS transistor PT4 and the nMOS transistor NT4.
Then, a signal FCOMPnj indicating a comparison result is output from a connection point between the output terminal of the transfer gate circuit TG1 and the output terminal of the clocked inverter circuit CV1.

In the comparison circuit, when the first output terminal of the fuse latch circuit is at the Vss level and the second output terminal is at the Vcc level, that is, when the fuse F1 of the fuse latch circuit is not blown, the transfer gate circuit TG1 Is deactivated, the clocked inverter circuit CV1 is activated, and the inverted state of the address signal is always changed to the comparison result signal FCOMPn.
Output as j.

On the other hand, when the first output terminal of the fuse latch circuit is at the Vcc level and the second output terminal is at the Vss level, that is, when the fuse F1 of the fuse latch circuit is cut, the transfer gate circuit TG1 is turned off. Activated,
The clocked inverter circuit CV1 is inactivated, and the address signal is always output as it is as the comparison result signal FCOMPnj.

That is, in the fuse latch circuits 41-0 to 41-n corresponding to the address signals A0 to An, if the fuse F1 is not cut, the comparison result is obtained when the address signal is at the Vss level. Signal FCOMPnj is Vcc
Level, and when the fuse is blown, the comparison result signal FCOMPnj when the address signal is at the Vcc level.
Becomes the Vcc level.

Next, details of the logic circuit in the redundant word line selection circuit will be described.

FIG. 10 is a circuit diagram showing a configuration of the logic circuit.

As shown in FIG. 10, the logic circuit 45 has a NAND circuit ND1 having a plurality of input terminals, an input terminal connected to an output terminal of the NAND circuit ND1, and an output terminal activating a redundant word line. RWLEj.

The NAND circuit ND1 has input terminals of the number obtained by adding 2 to the number of addresses required to select one word line, and the comparison circuits 44-0 to 44 corresponding to the number of addresses.
-n comparison result signals FCOMP0j to FCOMPnj, the output signal FENBLj of the enable fuse latch circuit 42, and the output signal bFDISj of the disable fuse latch circuit 43 are input. A signal instructing activation of a redundant word line output from the logic circuit only when all of these signals input to NAND circuit ND1 are at Vcc level.
RWLEj is at the Vcc level.

The operation of the thus configured redundancy control circuit 14 will be described.

In the redundancy control circuit 14, the output signal bFDISj of the disable fuse latch circuit 43 in the redundancy word line selection circuit is connected to the NAND circuit N constituting a logic circuit.
It is input to the input terminal of D1. Therefore, when the fuse F2 of the disable fuse latch circuit 43 is not blown, that is, when the Vcc level is output as the output signal bFDISj, the redundancy control circuit 14 operates in exactly the same manner as the conventional circuit shown in FIG. Will do.

However, once the fuse F2 is cut, that is, when the Vss level is always output as the output signal bFDISj, regardless of the state of the other fuse latch circuits and the state of the address signal, the logic circuit 45 is switched off. RWLEj, that is, a signal instructing activation of the redundant word line is always at the Vss level. As a result, the fuse F2
The redundant word line corresponding to the redundant word line selection circuit (fuse set) having the disabled fuse latch circuit 43 whose fuse has been cut off can no longer be used again.

As described above, although the fuse F2 of the disable fuse latch circuit 43 is not normally cut,
When the redundant memory cell used for replacement becomes defective, the fuse F2 of the disable fuse latch circuit 43 corresponding to the redundant memory cell is blown. After making the defective redundant memory cell unusable,
A defective memory cell which should be replaced anew is replaced with another unused redundant memory cell. By performing such replacement, the yield of the semiconductor memory device can be improved.

When a test of a redundant memory cell before replacement is found to be defective, the fuse F2 of the disable fuse latch circuit 43 corresponding to the defective redundant memory cell is cut off, and Making the redundant memory cell unusable again. By storing the test results in the redundancy control circuit itself in this way, it is not necessary to store the test results externally, and the work efficiency can be improved.

As described above, according to the first embodiment, the test result can be stored in the redundant circuit itself by adding the function of disabling the use of the redundant memory cell to the redundant circuit. Even if a redundant memory cell that is once used becomes defective, it can be disabled and replaced with an unused normal redundant memory cell to improve the yield. It is possible to provide a semiconductor memory device that can be operated.

In the first embodiment, the case where the redundant word line corresponding to the redundant memory cell is disabled has been described. However, the same applies to the redundant bit line pair corresponding to the redundant memory cell. It can be made unusable by the method of.

Next, as a modification of the first embodiment, a signal line (address) to which an address signal is supplied by adding an inverter circuit in front of an input section of a comparison circuit to which an address signal is supplied. The circuit configuration may be such that the capacitance seen from the viewpoint becomes constant. Other configurations are the same as those of the first embodiment.

As shown in FIG. 11, there are fuse sets 0 to fuse set j corresponding to redundant word lines RWL0 to RWLj for selecting each redundant memory cell, and addresses A0 to An are assigned to the respective fuse sets. In the case of the input method, the capacity seen from the address line differs depending on whether the fuse F1 is cut or not (the transfer gate circuit TG1 is activated or the clocked inverter CV1 is activated). That is, the transfer gate circuit TG
When 1 is activated, the gate capacitance of the NAND circuit ND1 having many input terminals at the subsequent stage is also added.

Such a change in the capacitance should be substantially unnoticeable if only one address line is connected. However, as in this method, one
When a single address line is connected, even if the change in capacitance at one location is small, it is not negligible because it is the sum of the changes at multiple locations.

For example, if the address line is connected to 1
If the clocked inverter circuit CV1 is activated, the capacitance added to the address line is 10 fF, while if the transfer gate circuit TG1 is activated, the gate capacitance of the subsequent stage is 5 fF. Is also added, so that the total is 15 fF.

In this case, the capacitance difference at one location is only 5f
F, but consider the case where there are 100 redundant word lines in the entire chip (one address line is connected to 100 locations). Here, suppose that the fuse A1 corresponding to the address A0 is completely cut and the fuse A1 is
It is assumed that all 1s are not cut. Then, a capacitance of 15 fF × 100 = 1.5 pF is added to the address line of A0, and a capacitance of 10 fF × 100 = 1 pF is added to the address line of A1. At this time, the difference in capacitance is 0.5 pF, which can no longer be ignored.

In order to solve this, as shown in FIG. 12, two inverter circuits IV71, IV71 are provided before the transfer gate circuit TG1 and the clocked inverter circuit CV1.
An IV 72 is added so that the fuse blowing does not affect the address lines. Further, by adding these inverter circuits, the added capacity per one place can be reduced.

That is, when there is no inverter circuit, the capacitance generated by the clocked inverter circuit CV1 and the transfer gate circuit TG1 is added to the address line. When an inverter circuit is added, the inverter circuit is added to the address line. Only capacity is added. Since the capacity can be reduced at a plurality of locations in this way, the effect of the reduction is significant. In this way, by adding the inverter circuit, the capacity seen from the address line (added to the address line) can be made constant. Other functions and effects are the same as those of the first embodiment.

As described above, according to the modification of the first embodiment, the function of disabling the use of the redundant memory cell is added to the redundant circuit, so that the test result is stored in the redundant circuit itself. Even if a redundant memory cell that has been used once becomes defective, the memory cell can be disabled and replaced with an unused normal redundant memory cell. It is possible to provide a semiconductor memory device capable of improving the yield.

Further, by adding an inverter circuit before the input section of the comparison circuit to which the address signal is supplied, the capacity added to the address line can be reduced to a certain level.

[Second Embodiment] Next, a semiconductor memory device according to a second embodiment of the present invention will be described.

In a mixed LSI in which a memory and a logic are mixed, the required memory capacity differs depending on the application. For this reason, it is necessary to design a number of embedded LSIs having different memory capacities. However, in many cases, other than the memory capacities, other logic and redundant circuits can be commonly used. In such a case, only the memory part is newly designed,
If other logics and redundant circuits can be shared, the burden on the design can be reduced.

The second embodiment is an example in which the present invention is applied to a plurality of semiconductor devices having different memory capacities by sharing a redundant circuit. Here, a case where the same redundant circuit and the same redundant memory cell array are used for the memory cell arrays having a capacity of 2 MB and 1 MB will be described as an example.

FIG. 13 is a diagram showing a simple configuration of a memory portion of a semiconductor memory device having a capacity of 2 MB. FIG.
FIG. 3 is a block diagram showing a configuration of a redundant word line selection circuit in a redundancy control circuit in the semiconductor memory device.

In this semiconductor memory device, in order to distinguish each of normal word lines WL0 to WL1023 in memory cell array 51, 10-bit address signals A0 to A10 are used.
9 is required. When the normal word line is replaced with the redundant word lines RWL0 to RWL15 in the redundant memory cell array 52, the information of the word line to be replaced is naturally recorded (programmed) by 10-bit data (fuse).
is necessary. Therefore, the redundant word line selection circuit is provided with fuse latch circuits 41-0 to 41-9, and the information of the word line to be replaced with these fuse latch circuits 41-0 to 41-9 is recorded (programmed). I have. Except for the disable fuse latch circuit 43, the other configuration is the same as that of the semiconductor memory device having the redundant word line selection circuit shown in FIG.

The case where the redundancy control circuit in the 2 MB semiconductor memory device thus configured is used for a 1 MB semiconductor memory device will be described.

FIG. 15 is a diagram showing a simple configuration of a memory section of a semiconductor memory device having a capacity of 1 MB. FIG.
FIG. 3 is a block diagram showing a configuration of a redundant word line selection circuit in a redundancy control circuit in the semiconductor memory device.

In a 1 MB semiconductor memory device, 9-bit address signals A0 to A8 are used to distinguish each of normal word lines WL0 to WL511 in memory cell array 53.
A9 used in the case of 2 MB is not used for decoding the word line and is unnecessary. The normal word line is connected to the redundant word line RW in the redundant memory cell array 54.
When replacing L0 to RWL15, 9-bit fuse latch circuits 41-0 to 41-8 only need to be provided, and the 10-bit fuse latch circuit 41-9 corresponding to A9 is left. The fuse latch circuit 41-9 and the comparison circuit 44-9 are used for a disable fuse latch circuit 55 as shown in FIG.

FIG. 17 is a circuit diagram showing a configuration of the disable fuse latch circuit. This disable fuse latch circuit has a configuration in which the fuse latch circuit and the comparison circuit are connected, and is originally used as a disable fuse latch circuit by supplying Vss to an input terminal of a comparison circuit portion to which an address is input. Is what you do. Other configurations are the same as those of the semiconductor memory device according to the first embodiment shown in FIG.

As described above, the first memory capacity (2 MB)
If the circuit used for the fuse latch circuit and the comparison circuit in the semiconductor memory device of the above is used as a disable fuse latch circuit in a semiconductor memory device of a second memory capacity (1 MB) different from the first memory capacity, Therefore, there is no need to carry out the design work of the redundant control circuit, and the burden on the design can be reduced.

[0089]

As described above, according to the present invention, by adding a function of disabling the use of a redundant memory cell to a redundant circuit, a test result of a redundant memory cell performed in advance is stored in the redundant circuit itself. Even if a redundant memory cell that has been used once becomes defective, the memory cell can be made unusable and replaced with an unused normal redundant memory cell. ,
It is possible to provide a semiconductor memory device capable of improving the yield.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a redundancy control circuit provided in the semiconductor memory device.

FIG. 3 is a block diagram showing a configuration of a redundant word line selection circuit in the redundancy control circuit.

FIG. 4 is a circuit diagram showing a configuration of a fuse latch circuit in the redundant word line selection circuit.

FIG. 5 is a timing chart showing an initial sequence performed at the time of power-on.

FIG. 6 is a circuit diagram showing a configuration of an enable fuse latch circuit in the redundant word line selection circuit.

FIG. 7 is a circuit diagram showing a configuration of a disable fuse latch circuit in the redundant word line selection circuit.

FIG. 8 is a circuit diagram showing a configuration of a comparison circuit in the redundant word line selection circuit.

FIG. 9 is a circuit diagram showing a configuration of a clocked inverter circuit in the comparison circuit.

FIG. 10 is a circuit diagram showing a configuration of a logic circuit in the redundant word line selection circuit.

FIG. 11 is a circuit diagram showing connection of address lines in the redundancy control circuit.

FIG. 12 is a circuit diagram showing an example of a circuit configuration in which the capacitance as viewed from an address line in the redundancy control circuit is constant.

FIG. 13 is a diagram showing a simple configuration of a memory unit of a semiconductor storage device having a capacity of 2 MB.

FIG. 14 is a block diagram showing a configuration of a redundant word line selection circuit in a redundancy control circuit in the semiconductor memory device.

FIG. 15 is a diagram showing a simple configuration of a memory unit of a semiconductor memory device having a capacity of 1 MB.

FIG. 16 is a block diagram showing a configuration of a redundant word line selection circuit in a redundancy control circuit in the semiconductor memory device.

FIG. 17 is a circuit diagram showing a configuration of a disable fuse latch circuit in the redundant word line selection circuit.

FIG. 18 is a block diagram showing a configuration of a conventional redundant circuit.

FIG. 19 is a circuit diagram showing a configuration of a fuse latch circuit in the redundant circuit.

FIG. 20 is a circuit diagram showing a configuration of a comparison circuit in the redundant circuit.

FIG. 21 is a circuit diagram showing a configuration of a logic circuit in the redundant circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Address buffer 12 ... Row decoder 13 ... Column decoder 14 ... Redundancy control circuit 15 ... Word line driver 16 ... I / O gate 17 ... Redundant word line driver 18 ... Memory cell array 19 ... Redundant memory cell array 20 ... Sense amplifier 21 ... Input Buffer 22 Output buffer 31-0, 31-1, ..., 31-j Redundant word line selection circuit 32 NOR circuit 41-0, 41-1, ..., 41-n Fuse latch circuit 42 Enable fuse latch Circuit 43: Disable fuse latch circuit 44-0, 44-1,..., 44-n Comparison circuit 45: Logic circuit 51: Memory cell array 52: Redundant memory cell array 53: Memory cell array 54: Redundant memory cell array WL0, WL1, ..., WLi ... word lines RWL0, RWL1, ..., RWLj ... redundant word lines

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Munehiro Yoshida 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Microelectronics Center Co., Ltd. 5L106 CC04 CC17 CC31 CC38 EE02 EE07 GG05

Claims (13)

[Claims] An element commonly used to store data; a spare element used instead if the element is a bad element; and an address stored in a programmable read-only memory. A redundancy control circuit that selects which of the element and the spare element to use in accordance with a comparison result of an address input from the outside, wherein the redundancy control circuit disables the spare element A semiconductor memory device having a function of performing 2. The semiconductor memory device according to claim 1, wherein the function of disabling the spare element can be performed before replacing the spare element with a defective element. 3. The function of making the spare element unusable can be performed after the spare element is replaced with a defective element.
3. The semiconductor memory device according to claim 1. 4. The semiconductor memory according to claim 1, wherein the function of disabling the spare element can be performed before or after replacing the spare element with a defective element. apparatus. 5. The semiconductor memory device according to claim 1, wherein the function of disabling the spare element is provided for each spare element. 6. An element according to claim 1, wherein said element corresponds to a memory cell.
6. The memory device according to claim 1, wherein the spare element is one or a plurality of redundant word lines corresponding to a redundant memory cell.
6. A semiconductor memory device according to any one of the preceding claims. 7. The device according to claim 1, wherein said element corresponds to a memory cell.
6. A pair or a plurality of pairs of bit lines, wherein the spare element is one or a plurality of pairs of redundant bit lines corresponding to a redundant memory cell. Semiconductor storage device. 8. The semiconductor memory device according to claim 1, wherein said programmable read-only memory is a fuse. 9. The semiconductor memory device according to claim 1, wherein said programmable read-only storage section can change storage information even after packaging. 10. The semiconductor memory device according to claim 9, wherein said programmable read-only memory is an electric fuse capable of electrically changing a connection state of a circuit. 11. When the same redundancy control circuit and the same spare element are employed for two or more types of semiconductor memory devices having different capacities, only the semiconductor memory device having the largest capacity is used. 2. The semiconductor memory device according to claim 1, wherein a programmable read-only memory corresponding to an unused address is used as means for disabling the spare element in the other semiconductor memory devices. . 12. The redundancy control circuit, wherein a parasitic capacitance added to a signal line to which an address is supplied is constant before and after storing an address of a defective element in the programmable read-only storage unit. The semiconductor memory device according to claim 1. 13. The semiconductor memory device according to claim 1, wherein said semiconductor memory device includes means for testing said spare element.