KR100396305B1 - A semiconductor memory device and test method thereof - Google Patents

Abstract

Provided are a semiconductor memory device capable of realizing a BIST circuit capable of suppressing an increase in pattern area to a minimum and obtaining redundancy relief information, and reducing the defective rate of the BIST circuit itself using a simple algorithm, and a test method thereof.

A memory element for redundancy data storage comprising a memory circuit 10 having an array 11 of ordinary memory cells and an array 12 of redundancy cells, and a nonvolatile element that is programmable from outside and can not be rewritten. 16), a redundancy determination circuit 14 which determines whether or not a redundancy cell is used by comparing a register 15 for storing data of a memory element after power-on, and the data stored in the register with an address input from the outside; And a redundancy data rewrite circuit 17 capable of rewriting redundancy data other than the storage element into the register and rewriting the stored redundancy data.

Description

Semiconductor memory device and test method thereof {A SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a test method thereof, and more particularly, to a fuse data change circuit and a prefabricated automatic test circuit for changing data programmed into a fuse element, for example, used in a dynamic semiconductor memory (DRAM). Will be.

Recently, attention has been paid to a technique in which a self-assembled automatic test circuit (BIST circuit) is mounted on a semiconductor memory and the test cost is reduced by using a BIST circuit in place of an external memory tester. In particular, in a so-called memory mixed logic LSI (system LSI) in which a plurality of functions including memory functions (memory macros) are integrated on one chip and a specific system is formed in one chip, it is possible to test without using a memory tester. It is demanded as a possible technique.

On the other hand, in recent years, as the integration of high-density semiconductor devices progresses, a redundant circuit is provided to replace the defective cells with redundant cells to improve the yield. Therefore, the technique of the BIST circuit which acquires the substitution information (redundancy information) of a cell has been considered. (JSSCC Vol.33 No.11 November, 1998 p.p 1731-1740)

However, in order to increase the rescue efficiency, the number of redundant cells must be increased, and there is a problem that the amount of redundancy information increases, thereby increasing the pattern area of the register for redundancy information storage and the BIST circuit.

In addition, increasing the number of redundant cells in order to increase the rescue efficiency requires a complicated substitution decision algorithm and a complicated pattern sequence necessary for obtaining redundancy information, which complicates the logic circuit which executes it, thereby reducing the defect rate of the BIST circuit itself. There were many difficulties in actual use.

As described above, the BIST circuit of the conventional semiconductor memory has a problem in that, when the number of redundant cells is increased in order to increase the rescue efficiency, the pattern area of the register for redundancy information is increased, so that a complicated substitution decision algorithm and a complicated pattern sequence are performed. Since it is necessary to complicate the logic circuit which executes it, the defect rate of the BIST circuit itself is raised, and there existed a problem that it was difficult in actual use.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is possible to realize a BIST circuit capable of obtaining redundancy relief information by suppressing an increase in the pattern area to a minimum, and to lower the defective rate of the BIST circuit itself using a simple algorithm. An object of the present invention is to provide a semiconductor memory device and a test method thereof.

Further, another object of the present invention is to be able to transfer other data to the rear end circuit as needed, regardless of the data of the memory element which is not electrically rewritable of the stored data, thereby providing flexibility in the input state to the rear end circuit. It is to provide a semiconductor memory device which can be provided with.

1 is a block diagram schematically showing a part of a DRAM according to a first embodiment of a semiconductor memory of the present invention;

FIG. 2 is a circuit diagram showing a specific example by extracting the redundancy data storage element 16, the register 15, and the redundancy data rewriting circuit 17 in FIG. 1, and a timing waveform diagram showing the operation example thereof.

FIG. 3 is a circuit diagram showing a specific example by extracting the redundancy data storage element 16, the register 15 and the redundancy data rewriting circuit 17 in FIG. 1, and a timing waveform diagram showing the operation example thereof.

4 is a block diagram schematically illustrating a modification of the DRAM of FIG. 1;

Fig. 5 is a block diagram schematically showing a part of a DRAM according to the second embodiment of the semiconductor memory of the present invention.

FIG. 6 is a flowchart illustrating a test method for the DRAM of FIG. 5. FIG.

Fig. 7 is a flowchart showing an example of a sequence of test operations in a DRAM according to the third embodiment of the semiconductor memory of the present invention.

8 is a block diagram showing a portion of a memory circuit portion and a portion of a BIST circuit for executing the sequence of FIG.

<Explanation of symbols for main parts of drawing>

10: memory circuit

11: ordinary cell array

12: redundant cell array

14: redundancy determination circuit

15: register

16: redundancy data storage element

17: redundancy data rewrite circuit

The semiconductor memory device of the present invention comprises a memory circuit having an array of ordinary memory cells and an array of redundancy cells, a memory device for redundancy data storage, which comprises a nonvolatile element that is capable of storing data programs from outside and is not rewritable, and a power supply. A redundancy determination circuit for determining whether to use the redundancy cell by comparing a register for storing data of the storage element after the input, data stored in the register with an address input from the outside, and a register other than the storage element. And a redundancy data rewriting circuit capable of re-input of other redundancy data from the data and rewriting the stored redundancy data.

In the semiconductor memory device, the redundancy data rewriting circuit can be controlled by a test circuit mounted on a chip of the semiconductor memory device or a signal from a test circuit external to the chip. In this case, it is possible to mount a prefabricated test circuit capable of generating a test pattern on a chip as a test circuit, and to control the redundancy data rewrite circuit by a signal from the prefabricated test circuit.

The prefabricated test circuit includes a data generation circuit for generating a pattern of data to be written to the memory circuit, an address generator for generating an address pattern for designating an address of the memory circuit, and expected data for output data of the memory circuit. The redundancy assigning circuit having a generated expectation generating circuit, a data comparing circuit comparing the output data with the expected data, and a redundancy assigning circuit configured to receive an output of the data generating circuit and the address generating circuit and determine allocation of the redundancy cell; It is possible to control the redundancy data rewrite circuit by the output of the allocation circuit.

Further, in a semiconductor memory device having a two-dimensional address space of X and Y and a two-dimensional redundancy cell, as the prefabricated test circuit, one address Y is fixed and the other address X is changed to a relief unit. When the test is performed and the redundancy cell of X cannot be rescued, the redundancy of Y is used, and when the redundancy cell of X can be rescued, the redemption of the redundancy cell of X is performed. A series of X tests are carried out, and the test operation is continued until the defect is eliminated. Then, when the defect is eliminated, a series of X tests are continued to the last unit while the X address of the next relief unit is similarly saved. Direction test is carried out, and the Y direction test is then performed by changing the Y space, and the final relief stage in the Y direction It is possible to have a sequence of outputting a pass signal when the test is performed to the above unit, and outputting a fail signal when all relief cells are used in the middle of outputting the pass signal. Do.

Further, the test method of the semiconductor memory device of the present invention, when the semiconductor memory device is tested by a prefabricated test circuit mounted in the semiconductor memory device having an array of ordinary memory cells and an array of redundancy cells for relief, The address is changed by using a remedy cell so that there is no defect by changing the address in the redundancy remedy unit, the remedy information is input into the register, the test is performed on the address again in the relieved state, and the test is performed until the defect is eliminated. When the repair operation is continued and the defect is eliminated, a step of executing the sequence of continuing the test while relieving similarly from the address of the next redundancy relief unit, and outputting a pass signal when the test of the last redundancy relief unit is completed, Moreover, relief is performed in the middle before outputting the said path signal. When the cells are used up, the method may include outputting a fail signal to terminate the test operation.

Further, the test method of the semiconductor memory device of the present invention has a two-dimensional address space of X and Y and a two-dimensional redundancy cell, and the semiconductor memory device is constructed by a prefabricated test circuit mounted on a chip of the semiconductor memory device. When performing the test, one address Y is fixed, the other address X is changed to the relief unit, and the test is performed. When the redundancy cell of X cannot be saved, the redundancy cell of X is used, and the redundancy cell of X is used. If it is possible to rescue from the redundancy cell of X, the test is performed on the X address again in the rescued state, and the test operation is continued until the defect is eliminated. A series of X-directions that continue the test and test to the last unit, similarly retrieving the X address of the next remedy unit When the test is performed, the X direction test is performed by changing the Y space, and the test is performed to the last relief unit in the Y direction, a pass signal is output, and the relief is performed on the way before the pass signal is output. When all the cells are used, the sequence for outputting the fail signal and ending the test operation is executed.

In addition, the semiconductor memory device of the present invention includes a memory element capable of programming data to be stored and electrically rewriting the stored data, transfer means capable of transferring the stored data of the memory element to a subsequent circuit, and the transfer means. Included in the, characterized in that it comprises a change means for selectively changing the content of the transmission data.

The transfer means of the semiconductor memory device may further include data holding means for holding the storage data of the storage element, and the changing means may destroy the holding data of the data holding means and change it to other data. The changing means may invalidate the transmission contents of the data of the storage element and change the data to other data.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>

1 schematically shows a part of a DRAM according to the first embodiment of the semiconductor memory of the present invention.

In Fig. 1, the memory circuit 10 replaces an array in which ordinary memory cells are arranged in a matrix (normal cell array 11), and replaces them in row units or column units when the cells of the conventional cell array are defective. A general configuration such as an array of redundancy cells (redundant cell array) 12 to be performed, and an address decoder 13 for selecting either one of the above-mentioned conventional cell array or redundant cell array by decoding address data.

The redundancy data storage element 16 is for storing redundancy data (redundancy relief information, cell replacement information), and the storage data is programmed by the replacement data programming means. In the DRAM, as the redundancy data storage element 16, a nonvolatile element, usually a fuse element, in which data to be stored can be programmed from the outside and electrical rewriting of the stored data is impossible, usually a fuse element is used. Blown by a laser beam).

The register 15 stores the redundancy data. When the DRAM is powered on, the register 15 stores the stored data of the redundancy data storage element 16. The redundancy data storage element 16 and the register 15 are basically necessary parts of a redundancy system of DRAM.

The redundancy data rewriting circuit 17 reinputs the redundancy data into the register 15 from the other than the redundancy memory element 16 in order to rewrite the redundancy data stored in the register 15.

The redundancy determination circuit 14 compares the address input from the outside with the redundancy data stored in the register 15, and if it is not suitable, sends the external input address to the address decoder 13 as it is, and if appropriate, the external input address. Instead, a redundancy address that should be used originally is sent to the address decoder 13. That is, the redundancy determination circuit 14 determines whether or not the redundancy cell is used instead of the cell specified in the input address.

The address decoder 13 activates the selection line of the memory cell array 11 or the selection line of the redundancy cell array 12 in accordance with the address data from the redundancy determination circuit 14. As a result, the data of the cells of the selected memory cell array 11 or the redundancy cell array 12 becomes a data output.

FIG. 2A illustrates a specific example by extracting the redundancy data storage element 16, the register 15, and the redundancy data rewriting circuit 17 in FIG. 1.

In Fig. 2A, reference numeral 21 denotes a fuse element which is a redundancy data storage element (16 in the figure), and " 1 " of data depending on whether or not the fuse element 21 is laser cut. "/" 0 "is distinguished.

Reference numerals 22, 24, and 27 denote PMOSFETs (PM0S transistors), and reference numerals 23, 25, 26, 28, and 29 denote MOSFETs (NMOS transistors). Of these, the source of the PMOS transistor 22 is connected to the power supply potential VDD node, and the drains of the PMOS transistor 22 and the NMOS transistor 23 are commonly connected to the node FCt, and the NMOS transistor ( The fuse element 21 is connected between the source of the 23 and the node of the ground potential VSS. The precharge control signal FCLRn is input to the gate of the PMOS transistor 22, and the fs set signal FSETp is input to the gate of the NMOS transistor 23.

On the other hand, the PMOS transistors 24 and 27 and the NMOS transistors 25, 26 and 28 constitute the above resistor 15. That is, the source of the PM0S transistor 24 is connected to the VDD node, the source of the NMOS transistor 26 is connected to the ground node, and the NMOS transistor 25 between each drain of the PM0S transistor 24 and the NMOS transistor 26. Is connected between the drain and the source, and the signal FCLRn is input to the gate of the NMOS transistor 25. The source of the PMOS transistor 27 is connected to the VDD node, and the source of the NMOS transistor 28 is connected to the ground node.

Each gate of the PMOS transistor 27 and the NMOS transistor 28 and each drain of the PMOS transistor 24 and the NMOS transistor 25 are connected in common and are connected to the node FCt.

In addition, each gate of the PMOS transistor 24 and the NMOS transistor 26 and each drain of the PMOS transistor 27 and the NMOS transistor 28 are connected in common to each other as a resistor output node FCc.

In addition, in this embodiment, one redundancy data rewriting circuit 17 is added to one redundancy data storage element 16. As this redundancy data rewrite circuit 17, one NMOS transistor 29 having a drain and a source connected between the node FCt and the VSS node is used, and a rewrite control signal RDATc is input to the gate thereof. .

FIG. 2B is a timing waveform diagram illustrating an operation example of FIG. 2A. In Fig. 2B, the horizontal axis represents time, and before the point A, the data storage operation to the register 15 at the time of power supply is shown, and after the point A, the redundancy data writing operation to the register 15 is shown.

First, the data storage operation to the register 15 at the time of power supply is explained. At the time of power supply, the precharge control signal FCLRn goes from "H" to "L". The PM0S transistor 22 is turned on to precharge the node FCt to "H". As a result, the NM0S transistor 28 is turned on, and the register output node FCc is precharged to "L". Thereafter, even when the signal FCLRn returns to " H ", the potentials of the nodes FCt and FCc do not change.

Thereafter, the fuse set signal FSETp becomes "H" from "L", so that the NMOS transistor 23 is turned on. At this time, both the PMOS transistor 24 and the NMOS transistor 23 are turned on, and the potential of the node FCt is determined by the balance of these driving capabilities, but the driving capability of the NM0S transistor 23 is designed to be strong.

Accordingly, at this time, when the fuse element 21 is cut off, the node FCt remains as "H" and the register output node FCc remains "L". On the other hand, when the fuse element 21 is not cut | disconnected, node FCt turns to "L", PM0S transistor 27 turns on by this, and register node FCc turns to "H". In the latter stage, when the state in which the fuse element 21 is cut off is treated as "H", the inversion logic of the node FCc is used as a signal.

Thereafter, even when the signal FSETp becomes " L ", the potentials of the nodes FCt and FCc do not change. Once set in this manner, there is no method for changing the logical values of the nodes FCt and FCc except for the power supply being cut off or performing the next redundancy data write operation. In addition, the rewrite control signal RDATc is " L " between the data storage operations to the register 15 at the time of power supply.

On the other hand, when the redundancy data is written to the register 15, the precharge control signal FCLRn becomes "H" from "H", and precharges the node FCt to "H" and the node FCc to "L". At that point, the information programmed into the fuse element 21 is lost. Thereafter, even if the signal FCLRn returns to " H ", the nodes FCt and FCc do not change.

Subsequently, in order to write "H" as redundancy data (to be in the same state as when the fuse element 21 is cut off), if the rewrite control signal RDATc is left as "L", the node FCt is The state of "H" remains as it is, and the node FCc remains of state of "L".

On the other hand, in order to write "L" as redundancy data (to make the same state as when the fuse element 21 is not cut off), when the rewrite control signal RDATc is "H", the NM0S transistor 29 ) Comes on. At this time, both the PNMOS transistor 24 and the NMOS transistor 29 are turned on, and the potential of the node FCt is determined by the balance of these driving capabilities, but the driving capability of the NMOS transistor 29 is designed to be strong. Accordingly, at this time, the node FCt becomes "L" and the node FCc becomes "H".

Thereafter, even if the signal RDATc becomes "L", there is no change in the potentials of the nodes FCt and FCc, and once set in this way, the power is cut off or the values of the nodes FCc and FCt are changed in addition to being reset to the above-described sequence. It is impossible.

In the DRAM of the first embodiment described above, specifically, the redundancy data stored in the fuse element 21 to the register 15 when the DRAM is powered on is rewritten by the redundancy data rewriting circuit 17 at the time of testing. It is possible to do. The data rewriting circuit 17 is configured to add one NMOS transistor 29 to one fuse element 21, which reduces the pattern area of the circuit much more than providing a register for redundancy information newly. There is a number.

In conventional DRAM fabrication, a test of a redundancy cell and a test of a normal cell are performed separately in order to acquire redundancy data in pre-sorting in a wafer process. Then, the fuse element 21 is programmed on the basis of the acquired redundancy data to rescue the defective cell, and then final die sorting is performed to select the defective chip.

On the other hand, in the DRAM of the first embodiment described above, since the value of the register 15 can be rewritten during the test as described above, the redundancy cell using state is not performed separately. Can be tested to improve test coverage.

In addition, since it is rewritten by the redundancy data rewriting circuit 17 at the time of a test, you may control by the signal in the test circuit mounted in the DRAM chip, or the test circuit outside the chip. In this case, as the test circuit mounted on the chip, it is possible to use a prefabricated test circuit capable of generating a test pattern by itself, for example, a prefabricated test circuit that automatically tests the memory circuit unit only with a clock from the outside.

In addition, the semiconductor memory device of the present invention, as described in the first embodiment described above, is capable of programming data to be stored and transferring data programmed in a memory element that cannot electrically rewrite the stored data to a subsequent circuit. The present invention also has a feature in that the transmitting means includes a changing means capable of selectively changing the contents of the transmission data. In the first embodiment described above, the data holding means (register 15) holding the stored data of the fuse element 21 in the means for transferring the stored data of the fuse element 21, A rewrite circuit 17 for destroying the retained data and changing it to other data is further provided.

Therefore, irrespective of the data (for example, redundancy data) of the memory element in which electrical rewriting of the stored data is impossible, it is possible to transfer other data to the rear circuit as needed (for example, in a test regarding redundancy). Thus, the input state to the rear end circuit can be made flexible.

As a change means provided in the transfer means capable of transferring the data of the storage element to the subsequent circuit, it is also possible to change the transfer of the data of the fuse element 21 to another data by making the transfer of the data invalid (non-destructive state). Also in this case, the same effects as described above can be obtained.

Next, in the case where a plurality of sets of circuits (fuse sets) of FIG. 2A are provided, and a plurality of sets of fuses can be selected and rewritten by an address signal, a set of fuse sets is typically extracted. It shows in FIG.3 (a).

The circuit of Fig. 3A is compared with the circuit described above with reference to Fig. 2A, and (1) shows an input signal FCLRp which is an inverted signal of the signal FCLRn and an address of a fuse set, for example. A NAND circuit NAND input by the signal FSAt [0: 2] of the bit is added, and an output signal thereof is input to the gates of the transistors 22 and 25 in place of the signal FCLRn, (2) the signal RDAT and the The AND circuit AND inputted by the signal FSAt [0: 2] is added, and the output signal is inputted to the gate of the transistor 29 in place of the signal RDAT, and otherwise the same sign is given. .

3B illustrates a data storage operation (before point A) to the register 15 at the time of powering up the circuit of FIG. 3A and a redundancy data write operation to the register 15 (point A). 2 sets of fuse sets are representatively extracted and shown. Here, the address signal FSAt [0: 2] of the first fuse set [111] is represented by FSAt [*], and the address signal FSAt [0: 2] of the second fuse set [000] is represented by FSAct [*].

First, when the power is turned on, the precharge control signal FCLRp is changed from "L" to "H". At the time of power supply, "H" is input as each bit of the signals FSAt [*] and FSAc [*], respectively. Therefore, in each set of fuses [111] and [000], the output signal of the NAND circuit NAND becomes "L", and the PMOS transistor 22 is turned on to precharge the node FCt to "H". As a result, the NM0S transistor 28 is turned on, and the register output node FCc is precharged to "L". Thereafter, even when the signal FCLRp returns to " L ", the potentials of the nodes FCt and FCc are not changed.

Thereafter, the fuse set signal FSETp becomes "H" from "L", so that the NMOS transistor 23 is turned on. At this time, both of the PMOS transistor 24 and the NMOS transistor 23 are turned on, and the potential of the node FCt is determined by the balance of these driving capabilities, but the driving capability of the NMOS transistor 23 is designed to be strong.

Accordingly, at this time, when the fuse element 21 is cut off, the node FCt remains as "H" and the register output node FCc remains "L". ) Is not cut, the node FCt becomes "L", thereby turning on the PM0S transistor 27, and the resistor node FCc becomes "H". If the cut-off state is treated as "H", the inversion logic of the node FCc is used as a signal.

Thereafter, even when the signal FSETp becomes " L ", the potentials of the nodes FCt and FCc do not change. Once set in this manner, there is no method for changing the logical values of the nodes FCt and FCc except for the power supply being cut off or performing the next redundancy data write operation. In addition, during the data storage operation to the register 15 at the time of power supply, the rewrite control signal RDATc is "L" and the output signal of the AND circuit AND is "L".

On the other hand, when the redundancy data is written to the register 15, the precharge control signal FCLRp is changed from "L" to "H". At this time, the second fuse set [000] is not selected by the signal FSAc [*] and continues to hold data before the redundancy data write operation.

On the other hand, the first fuse set [111] is selected by the signal FSAt [*], and performs the redundancy data write operation. That is, in the first fuse set 111, the output signal of the NAND circuit NAND becomes "L", and precharges the node FCt to "H" and the node FCc to "L". At that point, the information programmed into the fuse element 21 is lost. Thereafter, even if the signal FCLRp returns to " L ", the nodes FCt and FCc do not change.

After that, in order to write " H " as the redundancy data (to be in the same state as when the fuse element 21 is cut off), the rewrite control signal RDATc is left in the state of " L " The output signal of is left in the state of "L", the node FCt is in the state of "H", and the node FCc is in the state of "L".

On the other hand, in order to write "L" as redundancy data (to be in the same state as when the fuse element 21 is not cut off), when the rewrite control signal RDATc is "H", the output of the AND circuit AND The signal becomes " H " so that the NM0S transistor 29 is turned on. At this time, both the PMOS transistor 24 and the NMOS transistor 29 are turned on, and the potential of the node FCt is determined by the balance of these driving capabilities, but the driving capability of the NMOS transistor 29 is designed to be strong. Accordingly, at this time, the node FCt becomes "L" and the node FCc becomes "H".

Thereafter, even if the signal RDATc becomes "L", the potentials of the nodes FCt and FCc do not change, and once set in this way, the values of the nodes FCc and FCt are changed except for the power supply being cut off or reset to the above-described sequence. It is impossible.

<Modification of First Embodiment>

FIG. 4 schematically shows a modification of the DRAM of FIG. 1.

In Fig. 3, reference numerals 11 to 17 are the same as in Fig. 1. The redundancy data reading circuit 31 reads the data stored in the register 15 and outputs the data to an external terminal (for example, pad) 32 as redundancy data output. In addition, there are various methods of outputting the redundancy data read from the register 15 to the outside, and it is also possible to output the redundancy data via a normal data line.

By reading the value of the register 15 in this manner, the redundancy state during the test can be confirmed and the relief data can be read.

Second Embodiment

Fig. 5 schematically shows a part of the DRAM according to the second embodiment of the semiconductor memory of the present invention. In Fig. 5, reference numerals 11 to 17, 31, and 32 are the same as in Fig. 4. Reference numeral 58 denotes an address multiplexer, reference numeral 59 denotes a data multiplexer, and is respectively controlled by a test mode signal.

The address multiplexer 58 selects an external input address and supplies it to the redundancy determination circuit 14 when the test mode signal is in an inactive mode, and when the test mode signal is activated in the test mode, the BIST circuit 51 Is selected and supplied to the redundancy determination circuit 14.

The data multiplexer 59 selects internal data and supplies the internal data to the memory circuit unit when the test mode signal is in an inactive mode, and when the test mode signal is activated in the test mode, test data from the BIST circuit 51. Select to supply to the memory circuit section.

The BIST circuit 51 in FIG. 5 includes a BIST control circuit 52 which is a sequencer, a data generating circuit 53 for generating input data (data pattern) to the memory circuit section, and an address generating circuit for generating an input address to the memory circuit section. (54) Comparing the output of the expected value generating circuit 55 and the expected value generating circuit 55 and the data output from the memory circuit section by the address generating circuit 54 to compare the output of the data output (pass / fail). The result of the data comparison circuit 56 and the data comparison circuit 56 for determining the result is a redundancy assignment determination circuit 57 for assigning redundancy at the time of failure.

The redundancy assignment determination circuit 57 can directly control the register 15 for storing redundancy information through the redundancy replacement circuit 17 in the memory circuit section.

Next, the operation of the BIST circuit 51 will be described. First, the address is changed in the redundancy relief unit so as to eliminate the defect, the relief information is input into the register 15, the test is performed on the address again in the relief state, and the test is performed until the defect disappears. Continue the rescue operation. When the defect is eliminated, the address of the next relief unit is changed, the test is continued while the relief is performed as described above, and when the rescue operation of the last relief unit is completed, the pass signal Pass is output or the rescue is performed on the way. When all the cells are used, the sequence signal for outputting the fail signal Fail to end the test operation is not necessary, so that the redundant cells do not need to be tested individually, and the acquisition and replacement of the relief information can be realized in a simple logic BIST circuit. have.

Next, a test method for the DRAM of FIG. 5 will be described with reference to FIG. 6.

Since the BIST circuit 51 performs the test by rewriting the redundancy information until the test passes when the test is performed using the redundancy cell, the redundancy information at the end of the test is stored in the register 15. . After the test by the BIST circuit 51 ends, the program enters the program mode, reads information (redundancy data) of the register 15 to the outside, and based on the information, the redundancy data storage element 16 using the replacement data programming means. ). In this program mode, the circuit can be simplified by reading the contents of the register 15 in series by a scanning method, so that an extra pattern area is not required.

According to the DRAM of the second embodiment described above, the BIST circuit 51 includes the BIST control circuit 52, the data generating circuit 53, the address generating circuit 54, the expected value generating circuit 55, and the data comparing circuit 56. And a redundancy assignment determination circuit 57, which can automatically test the memory circuit section only with an external clock. At this time, by controlling the redundancy data rewriting circuit 17 by the output of the redundancy allocation determining circuit 57 to directly control the register 15 of the memory circuit section, the register for storing the redundancy data by the BIST circuit 51 is obtained. There is no need to newly install it, and the existing register 15 of the memory circuit section can be used, and the area (pattern area) of the BIST circuit 51 on the chip can be greatly reduced.

In addition, since redundancy can be tested in a state close to practical use, test coverage can be improved. In addition, since the individual test for redundancy is not necessary, and a bad address is not stored, and a normal cell is replaced and accessed, the test including the redundancy cell can be simplified and the BIST circuit 51 can be simplified.

Third Embodiment

7 is a flowchart showing an example of a sequence of test operations in a DRAM according to the third embodiment of the semiconductor memory of the present invention. This DRAM has two-dimensional address spaces of X and Y, and the basic configuration is similar to that of the DRAM described above with reference to FIG.

The test is performed by scanning in the first X direction of the two-dimensional address space of the DRAM. First, Y is fixed in the two-dimensional address space, and X is changed by changing the relief units. At this time, first, determination of Y defect is performed, and if there is no Y defect, determination of X defect is performed. If there is no X defect, the X relief unit is incremented to proceed to the test of the next X relief unit.

In the above process, when the number of reliefs in the redundancy cell of X is exceeded, relief is performed using the redundancy cell of Y. At that time, the number of rescued cells of Y used so far is counted, this count value is determined, and when the count value becomes unrecoverable, a fail flag is immediately set and the sequence is stopped (Test End).

On the other hand, when the redundancy cell of Y can be rescued, the same X rescue unit is tested again while the bad address of Y is written in the register for storing the rescue information of Y so as to be replaced by Y. do.

When the number of redundancy cells of X is not exceeded, a bad address of X is written into the register for storing the relief information of X so as to be replaced by the redundancy cell of X. After that, test the same X relief unit again.

In this way, a test is performed while replacing the redundancy cell of X or Y, and when failing to fail, the X relief unit is incremented to proceed to the next X rescue unit test.

When these operations are repeated and the test of all the relief units of X is performed, the same procedure as described above is performed by incrementing the Y address. When the testing of all the Y addresses is completed, a pass flag is set to end the sequence.

FIG. 8 shows part of the memory circuit section and part of the BIST circuit for executing the sequence of FIG.

In the memory circuit section in Fig. 8, reference numeral 15X denotes a register for X redundancy data, reference numeral 15Y denotes a register for Y redundancy data, reference numeral 716 denotes an X redundancy data reading circuit, and reference numeral 717 ) Is a Y redundancy data reading circuit, and reference numeral 32 is an external terminal.

The register 15X for X redundancy data has an X redundancy address register 77, an X redundancy use flag register 78, and an X redundancy counter 79.

The Y redundancy data register 15Y includes a redundancy address register 713 and a Y redundancy counter 714.

In the BIST circuit, reference numeral 71 denotes a sequencer (BIST control circuit) in charge of all control of the BIST circuit, reference numeral 72 denotes an X address generation circuit, reference numeral 56 denotes a data comparison circuit, and a reference numeral ( Reference numeral 57X denotes a redundancy assignment determination circuit for the X address, reference numeral 710 denotes a Y address generation circuit, reference numeral 57Y denotes a redundancy assignment determination circuit for the Y address, and the redundancy data is rewritten so that the circuit is omitted. The redundancy assignment determination circuits 57X and 57Y may be provided with one chip.

The X address generation circuit 72 receives the signal of the sequencer 71 and generates an address in the X direction. When the X relief unit ends, an X relief unit end signal (not shown) is incremented in the X relief unit. At the end, an X relief unit increment end signal (not shown) is output to the sequencer 71.

The X address register 73 holds the address generated by the X address generation circuit 72 until the data comparison circuit 56 performs data comparison. The X bad address register 74 stores a failed row address during a test in the relief unit. The X defective counter 75 is reset at the start of the test in the X relief unit, and counts the number of failures (defects) in the test in the X relief unit, and only counts up to the number that can be saved. . The zero signal Nul1 indicating that the output of this X defective counter 75 is "0" is output to the sequencer 71.

The X fail circuit 76 counts up the X fail counter 75 when a fail signal Fail is sent from the data comparison circuit 56. In addition, the value of the X address at the time of a failure is referred to the X address register 73, and it is stored in the X failure address register 74. FIG.

The Y address generation circuit 710 receives the signal of the sequencer 71 and generates an address in the Y direction, and when the Y relief unit ends, a Y relief unit end signal (not shown) is incremented in the Y relief unit. At the end, a Y relief unit increment end signal (not shown) is output to the sequencer 71.

When the sequencer 71 receives the test termination signal in the X relief unit sent from the X address generation circuit 72 when the test in the X relief unit ends, when the output signal of the X bad counter 75 is Null, Proceed to test the next X rescue unit, the next sequence. If the output signal of the X defective counter 75 is not Null at this point in time, it waits for a redundancy replacement operation, waits for a redundancy replacement operation termination signal from the X fail circuit 76 or the Y fail circuit 712, and Upon receiving the signal, test the same X relief unit again.

When the X fail-circuit 76 receives the test termination signal in the X relief unit sent from the X address generation circuit 72 when the test in the X relief unit ends, the value of the X fail counter 75 and the X redundancy data are used. The remaining values of the X redundancy counter 79 (indicates the number of spares of available X) in the register 15X are compared.

As a result, if the remaining value of the X redundancy counter 79 is equal to or larger than the value of the X bad counter 75, the number of X bad address registers 74 indicated by the X bad counter 75 will be X replacement. Input is made to the X redundancy address register 77 in the register 15X for X redundancy data.

On the other hand, if the value of the X defective counter 75 is larger than the remaining value of the X redundancy counter 79 (the number of spares of X that can be used), it is regarded as Y defective and outputs a YF (Y Fail) signal.

When the YF signal is input, the Y fail circuit 712 acquires the Y address currently being tested by the Y address register 711, and the Y redundancy address register 713 in the register 15Y for the Y redundancy data. In the table, and the Y redundancy counter 714 is counted up.

If there is a state where the value of the Y redundancy counter 713 becomes full, the full signal Full indicating it is output as a fail stop signal Fail Stop, and the operation of the sequencer 71 is stopped. The signal fail stop is later read through the pad.

When the remedy progresses and the test pattern ends to the end, the Y address generation circuit 7210 outputs an increment end signal (Pass end signal), and this pass end signal signal is also read later through the pad.

After the end of the test, the addresses recorded in the register 15X for the X redundancy data and the register 15Y for the Y redundancy data are read using the X redundancy reading circuit 716 and the Y redundancy reading circuit 717, Based on this readout output, programming is performed to the redundancy data storage element using a laser or the like.

Further, the X fail circuit 76 and the Y fail circuit 712 respectively need to be operated by referring to the addresses of the X address generating circuit 72 and the Y address generating circuit 710, respectively (X redundancy address register 77). ), X redundancy counter 79] and [Y redundancy address register 713, Y redundancy counter 714].

As described above, according to the present invention, a semiconductor memory device capable of realizing a BIST circuit capable of acquiring redundancy relief information by suppressing an increase in pattern area to a minimum, and capable of lowering a failure rate of the BIST circuit itself using a simple algorithm, and The test method can be provided.

In addition, according to the semiconductor memory device of the present invention, it is possible to transfer other data to the rear end circuit as necessary, regardless of the data stored in the memory element which is not electrically rewritable. You can have flexibility.

Claims (17)

In a semiconductor memory device, A memory circuit having a two-dimensional address space of X and Y and including an array of a plurality of normal memory cells and an array of a plurality of X and Y redundancy memory cells; A storage device for redundancy data storage, including a nonvolatile device that is externally programmable and cannot be electrically reprogrammed with data to be stored; A register holding redundancy data of the memory element when the semiconductor memory device is activated; A redundancy determination circuit for comparing the data held in the register with an address input from the outside to determine whether to use the redundancy memory cell; Redundancy data rewrite circuit for rewriting redundancy data held in the register as other redundancy data And a semiconductor memory device. The semiconductor memory device according to claim 1, wherein the redundancy data rewriting circuit is controlled by a signal from a test circuit provided on a semiconductor chip of the semiconductor memory device or a signal of a test circuit provided outside the semiconductor chip. . The semiconductor memory device according to claim 2, wherein the test circuit is a built-in type test circuit which generates a test pattern by itself. The method of claim 3, The prefabricated test circuit, Fixing the Y address and testing the X address of the normal memory cell in redundancy units to determine whether the X address of the normal memory cell is bad; When the X address of a normal memory cell is determined to be bad and is rescued using only the X redundancy cell, the normal memory cell of the X address is replaced with an X redundancy memory cell, and the X address of the normal memory cell is determined as bad and only the X redundancy cell is used. Replacing a normal memory cell of X address with a Y redundancy memory cell when it is not saved; Re-testing the X addresses of the normal memory cell and the replaced redundancy memory cell to determine whether the X addresses of the normal memory cell and the replaced redundancy memory cell are bad; Repeating the replacement step and the re-test step, changing the X or Y redundancy memory cells until it is determined that the X or Y address is not bad; The test step, the replacement step, and the re-test step for the next and subsequent X addresses of the normal memory cell while changing the X address of the normal memory cell in units of redundancy up to the last X address of the normal memory cell in redundancy units. And repeating the repeating step; Repeating the test step, the replacement step, the re-test step and the repetition steps, while changing the Y address, to the last X address of the conventional memory cell in the address space; And Outputs a pass signal when the test step, the replace step, the re-test step and the repeat steps are repeated until the last X address of the normal memory cell, but fails if all redundancy cells are replaced before outputting this pass signal. Outputting a signal to terminate the test step And performing a sequence of steps. The method of claim 3, The prefabricated test circuit, A data generation circuit for generating a pattern of data to be written to the memory circuit; An address generator circuit for generating an address pattern to address the memory circuit; An expectation generation circuit for generating expectation data for output data of the memory circuit; A data comparison circuit for comparing the output data with the expected data; And Redundancy allocation circuit for determining allocation of the redundancy cells in response to an output of the data generating circuit and an output of the address generating circuit Including; And said redundancy data rewriting circuit is controlled by an output of said redundancy allocation circuit. The method of claim 5, The prefabricated test circuit, Testing the address of the normal memory cell in redundancy units to determine whether the address of the normal memory cell is bad; Replacing the normal memory cell of the address with a redundancy memory cell to rescue a bad address of the normal memory cell; Inputting, by the redundancy data rewriting circuit, redundancy information into the register; Re-testing the addresses of the normal memory cell and the replaced redundancy memory cell to determine whether the addresses of the normal memory cell and the replaced redundancy memory cell are bad; Repeating the replacement step, the input step and the re-test step until it is determined that the address is not bad; Repeating the test step, the replace step, the input step, the re-test step and the repeat step for the next and subsequent addresses of the normal memory cell, up to the final address of the conventional memory cell in redundancy units; And A pass signal is output when the test step, the replacement step, the input step, the re-test step, and the repetition steps are repeated up to the last address of the normal memory cell, but before any redundancy cells are output before the pass signal is output. Outputting a fail signal to terminate the test step if replaced And performing a sequence of steps. The semiconductor memory device according to claim 1, further comprising a redundancy data reading circuit for reading data held in said register to the outside. 8. The semiconductor memory according to claim 7, wherein the redundancy data rewriting circuit is controlled by a signal from a test circuit provided on a semiconductor chip of the semiconductor memory device or a signal of a test circuit provided outside the semiconductor chip. Device. The semiconductor memory device according to claim 8, wherein the test circuit is a prefabricated test circuit which generates a test pattern by itself. The method of claim 9, The prefabricated test circuit, Fixing the Y address and testing the X address of the normal memory cell in redundancy units to determine whether the X address of the normal memory cell is bad; When the X address of a normal memory cell is determined to be bad and is rescued using only the X redundancy cell, the normal memory cell of the X address is replaced with an X redundancy memory cell, and the X address of the normal memory cell is determined as bad and only the X redundancy cell is used. Replacing a normal memory cell of X address with a Y redundancy memory cell when it is not saved; Re-testing the X addresses of the normal memory cell and the replaced redundancy memory cell to determine whether the X addresses of the normal memory cell and the replaced redundancy memory cell are bad; Repeating the replacement step and the re-test step, changing the X or Y redundancy memory cells until it determines that the X or Y address is not bad; The test step, the replacement step, and the re-test step for the next and subsequent X addresses of the normal memory cell while changing the X address of the normal memory cell in units of redundancy up to the last X address of the normal memory cell in redundancy units. And repeating the repeating step; Repeating the test step, the replacement step, the re-test step and the repetition steps, while changing the Y address, to the last X address of the conventional memory cell in the address space; And Outputs a pass signal when the test step, the replace step, the re-test step and the repeat steps are repeated until the last X address of the normal memory cell, but fails if all redundancy cells are replaced before outputting this pass signal. Outputting a signal to terminate the test step And performing a sequence of steps. The method of claim 9, The prefabricated test circuit, A data generation circuit for generating a pattern of data to be written to the memory circuit; An address generator circuit for generating an address pattern to address the memory circuit; An expectation generation circuit for generating expectation data for output data of the memory circuit; A data comparison circuit for comparing the output data with the expected data; And Redundancy allocation circuit for determining allocation of the redundancy cells in response to an output of the data generating circuit and an output of the address generating circuit Including; And said redundancy data rewriting circuit is controlled by an output of said redundancy allocation circuit. The method of claim 11, The prefabricated test circuit, Testing the address of the normal memory cell in redundancy units to determine whether the address of the normal memory cell is bad; Replacing the normal memory cell of the address with a redundancy memory cell to rescue a bad address of the normal memory cell; Inputting, by the redundancy data rewriting circuit, redundancy information into the register; Re-testing the addresses of the normal memory cell and the replaced redundancy memory cell to determine whether the addresses of the normal memory cell and the replaced redundancy memory cell are bad; Repeating the replacement step, the input step and the re-test step until it is determined that the address is not bad; Repeating the test step, the replace step, the input step, the re-test step and the repeat step for the next and subsequent addresses of the normal memory cell, up to the final address of the conventional memory cell in redundancy units; And A pass signal is output when the test step, the replacement step, the input step, the re-test step, and the repetition steps are repeated up to the last address of the normal memory cell, but before any redundancy cells are output before the pass signal is output. Outputting a fail signal to terminate the test step if replaced And performing a sequence of steps. In a semiconductor memory device, A memory element capable of programming of data and not capable of electrical reprogramming of data; A transmission circuit for transmitting data programmed in the storage element to a subsequent circuit; And A changing circuit in the transmitting means for selectively changing the data to be transmitted And a semiconductor memory device. The method of claim 13, The transmission circuit further includes a data retention circuit for holding data programmed into the storage element, And the change circuit changes data held in the data holding circuit into other data. The method of claim 13, And the change circuit invalidates the transfer of data programmed into the storage element and changes the data to other data. A method for testing a semiconductor memory device including an array of ordinary memory cells and an array of redundancy memory cells for relief by a prefabricated test circuit, Testing the address of the normal memory cell in redundancy units to determine whether the address of the normal memory cell is bad; Replacing the normal memory cell of the address with a redundancy memory cell to rescue a bad address of the normal memory cell; Inputting redundancy information into the register; Re-testing the addresses of the normal memory cell and the replaced redundancy memory cell to determine whether the addresses of the normal memory cell and the replaced redundancy memory cell are bad; Repeating the replacement step, the input step and the re-test step until it is determined that the address is not bad; Repeating the test step, the replace step, the input step, the re-test step and the repeat step for the next and subsequent addresses of the normal memory cell, up to the final address of the conventional memory cell in redundancy units; And A pass signal is output when the test step, the replacement step, the input step, the re-test step, and the repetition steps are repeated up to the last address of the normal memory cell, but before any redundancy cells are output before the pass signal is output. Outputting a fail signal to terminate the test step if replaced And testing the semiconductor memory device. A method for testing a semiconductor memory device including a two-dimensional address space of X and Y, an array of a plurality of ordinary memory cells and an array of a plurality of X, Y redundancy memory cells by a prefabricated test circuit, Fixing the Y address and testing the X address of the normal memory cell in redundancy units to determine whether the X address of the normal memory cell is bad; When the X address of a normal memory cell is determined to be bad and is rescued using only the X redundancy cell, the normal memory cell of the X address is replaced with an X redundancy memory cell, and the X address of the normal memory cell is determined as bad and only the X redundancy cell is used. Replacing a normal memory cell of X address with a Y redundancy memory cell when it is not saved; Re-testing the X addresses of the normal memory cell and the replaced redundancy memory cell to determine whether the X addresses of the normal memory cell and the replaced redundancy memory cell are bad; Repeating the replacement step and the re-test step, changing the X or Y redundancy memory cells until it is determined that the X or Y address is not bad; The test step, the replacement step, and the re-test step for the next and subsequent X addresses of the normal memory cell while changing the X address of the normal memory cell in units of redundancy up to the last X address of the normal memory cell in redundancy units. And repeating the repeating step; Repeating the test step, the replacement step, the re-test step and the repetition steps, while changing the Y address, to the last X address of the conventional memory cell in the address space; And Outputs a pass signal when the test step, the replace step, the re-test step and the repeat steps are repeated until the last X address of the normal memory cell, but fails if all redundancy cells are replaced before outputting this pass signal. Outputting a signal to terminate the test step And testing the semiconductor memory device.