JP3734075B2 - Compound memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a floating gate and capable of storing a defective address of another semiconductor memory device, and a semiconductor capable of accessing a spare memory for redundancy relief by an external signal The present invention relates to a composite memory in which a storage device is enclosed in the same package.
[0002]
[Prior art]
In the manufacturing process of a semiconductor memory device, a technique is used in which redundant repair is performed by replacing a memory cell that has become defective in a test with a spare memory cell in order to improve yield, and finally a non-defective product is used. This is generally performed by trimming a fuse with a trimmer or the like so that a spare memory cell is selected when an address of a defective memory cell is input in a wafer test process.
[0003]
FIG. 7 shows a wafer test flow of a conventional semiconductor memory device. First, data for redundant relief is collected in the pretest process. Then, in the next trimming process, trimming is performed to cut the fuse provided in the chip of the semiconductor memory device as shown in FIG. When this fuse is blown, the redundancy relief signal becomes LOW level and the spare memory cell is accessed. Thereafter, a post-test process may be performed to check whether the defective memory cell has been replaced with a spare memory cell.
[0004]
However, in such a redundant remedy method, when a defect is caused by burn-in after packaging, or when the spare memory cell is defective when the post-test process of FIG. 7 is not performed, redundant remedy of the semiconductor memory device is performed. I can't do it. In addition, since it is necessary to perform trimming in the wafer test process, the number of test steps increases and the cost of the product increases. Further, since it is impossible to access the spare memory cell unless the fuse is cut, it is very difficult to test the spare memory cell during the wafer test. Therefore, even if a defective memory cell is replaced with a spare memory cell after the fuse is blown, the spare memory cell may be defective, so that the repair rate is reduced and the yield of the semiconductor memory device is reduced. Connected.
[0005]
In order to solve such a problem, a method as disclosed in JP-A-8-16486 has been devised. This is to develop a new LSI for redundancy relief, encapsulate it in the same package as the semiconductor memory device, and replace it with a defective portion of the semiconductor memory device. A method as disclosed in JP-A-10-149694 has also been devised. This is because an EEPROM is provided inside the semiconductor memory device, a defective address is written in the EEPROM, and the semiconductor memory device can be redundantly repaired after packaging.
[0006]
[Problems to be solved by the invention]
However, in the method disclosed in Japanese Patent Laid-Open No. 8-16486, it is necessary to newly develop an LSI for redundant relief, and it is also necessary to test the LSI for redundant relief. Further, in the past, a semiconductor memory device was encapsulated in only one chip, but a new technique or material for encapsulating a redundant relief LSI in the same package is required, leading to an increase in product cost. . Further, in the method disclosed in Japanese Patent Laid-Open No. 10-149694, for example, when performing redundancy repair of SRAM, since the manufacturing process is completely different between SRAM and EEPROM, it is technically very difficult and the characteristics are also different. Come. That is, since it is necessary to construct a new process, there is a problem that costs are increased and a development period is extended.
[0007]
The present invention has been made to solve such problems of the prior art, and can provide redundant relief after packaging, thereby reducing manufacturing costs and preventing process problems and changes in characteristics. An object is to provide a composite memory that can be used.
[0008]
[Means for Solving the Problems]
The composite memory according to the present invention includes a nonvolatile semiconductor memory element configured in an array by a plurality of nonvolatile memory cells each having a floating gate , and a redundant relief semiconductor configured in an array by volatile memory cells. A composite memory in which a storage element is enclosed in the same package, wherein the redundant relief semiconductor storage element is constituted by an array of the volatile memory cells, and each of the volatile memory cells constituting the array the volatile normal memory unit in which data are stored, respectively, is constituted by an array of said volatile memory cell, a spare memory unit failure in the volatile memory cell in the normal memory unit is used in the event of has the non-volatile semiconductor memory device is constituted by an array of the nonvolatile memory cell, the A nonvolatile normal memory unit data in each non-volatile memory cell of the array of volatile memory cells are stored respectively, are constituted by an array of the nonvolatile memory cells, volatile in the redundancy repair semiconductor memory device When a defect occurs in the volatile memory of the normal memory unit, a redundant relief address storage memory unit that stores a defective address that is an address of the defective volatile memory cell, and an address input from the outside include the defect A redundancy relief signal output unit for outputting a redundancy relief signal to the redundancy relief semiconductor memory element when the address matches the address, and the redundancy relief semiconductor memory element receives the redundancy relief signal an input unit, when the redundancy repair signal is input to the redundant repair signal input unit, wherein in place of the volatile normal memory Characterized in that it adapted to select the spare memory.
[0009]
A second power supply voltage different from the power supply voltage supplied to the nonvolatile normal memory section in the nonvolatile semiconductor memory element may be supplied at the time of reading and writing data from the redundant relief semiconductor memory element.
[0010]
The second power supply voltage may be supplied to the redundant relief address storage memory unit in the nonvolatile semiconductor memory element .
[0011]
The operation of the present invention will be described below.
[0012]
In recent years, a composite memory in which a nonvolatile semiconductor memory element having a floating gate and another semiconductor memory element are enclosed in the same package has been developed. For example, there is one in which a FLASH memory and an SRAM are enclosed in the same package. Therefore, in the present invention, a portion for storing a defective address of another semiconductor memory element is provided in the nonvolatile semiconductor memory element having a floating gate. In another semiconductor memory element, a circuit is provided so that a spare memory cell is accessed when a redundant relief signal is input from the outside. When these two semiconductor memory elements are enclosed in the same package and a defective address in another semiconductor memory element is input, a redundant relief signal is output from the nonvolatile semiconductor memory element, and the redundant relief signal is transferred to another semiconductor By inputting to the storage element and accessing a spare memory cell instead of a normal memory cell, redundant relief can be achieved. Here, since the non-volatile semiconductor memory element needs to be an electrically rewritable non-volatile semiconductor memory element, non-rewritable elements such as a mask ROM are excluded. Further, other semiconductor memory elements may be volatile or non-volatile.
[0013]
By providing a normal memory unit in addition to the redundant relief address storage memory unit in the nonvolatile semiconductor memory element, it can be used as a normal composite memory in a memory such as a mobile phone.
[0014]
Further, when the power supply voltage is supplied to the redundant relief address storage memory unit separately from the normal memory cell array at the time of reading and writing data from other semiconductor memory elements, the nonvolatile semiconductor memory device can be in the stand state. However, the redundant relief address storage memory unit can be operated. As this power supply voltage, a power supply voltage common to other semiconductor memory elements can be used.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0016]
FIG. 1 shows a block diagram of a composite memory according to an embodiment of the present invention. This composite memory includes a non-volatile semiconductor memory element FM (FLASH memory in this embodiment) having a floating gate and a semiconductor memory element MEM (SRAM in this embodiment) having a redundancy relief function enclosed in the same package. is there.
[0017]
The nonvolatile semiconductor memory element FM includes a normal memory cell array FMC and redundant relief address storage memory cell arrays RCA to RCN each storing a defective address of the semiconductor memory element MEM. The normal memory cell array FMC is supplied with voltage from the power supply FVCC, and the redundant relief address storage memory cell arrays RCA to RCN are supplied with voltage from the power supply SVCC.
[0018]
The address ADR is input in common to the nonvolatile semiconductor memory element FM and the semiconductor memory element MEM. The address ADR input to the nonvolatile semiconductor memory element FM is input in common to the normal memory cell array FMC and the redundant relief address storage memory cell arrays RCA to RCN.
[0019]
Since the nonvolatile semiconductor memory element FM and the semiconductor memory element MEM cannot be operated at the same time, the operation state of each element is controlled by the chip enable terminal FCE and the chip enable terminal SCE. When the chip enable terminal FCE of the nonvolatile semiconductor memory element FM is at the HIGH level, the normal memory cell array FMC of the nonvolatile semiconductor memory element FM is in the standby state, and when it is at the LOW level, it is in the operating state. Similarly, the semiconductor memory element MEM is in a standby state when the chip enable terminal SCE of the semiconductor memory element MEM is at a HIGH level, and is in an operating state when it is at a LOW level. Here, the nonvolatile semiconductor memory element FM needs to output the redundancy relief signal RS when the semiconductor memory element MEM is in an operating state, and the portions other than the normal memory cell array FMC of the nonvolatile semiconductor memory element FM are: It is necessary to operate the semiconductor memory element MEM when it is in an operating state. Accordingly, the power supply SVCC serves as a common power supply in parts other than the normal memory cell array FMC of the semiconductor memory element MEM and the nonvolatile semiconductor memory element FM, and the chip enable terminals of the redundant relief address storage memory cell arrays RCA to RCN are connected to the semiconductor memory element MEM. The chip enable terminal SCE. When the normal memory cell array FMC of the nonvolatile semiconductor memory element FM is accessed, the redundant relief address storage memory cell arrays RCA to RCN and the semiconductor memory element MEM are in a standby state, so that there is no inconvenience in use.
[0020]
In this composite memory, when the semiconductor memory element MEM is tested as defective by a memory tester or the like and is remedied, the chip enable terminal SCE is set to the LOW level and the address ADR is used. A command is input to set the redundant relief address storage memory cell arrays RCA to RCN to the write state. Then, the clock is input to the write enable signal FWE, the counter CNT is counted up, the redundant relief address storage memory cell arrays RCA to RCN are sequentially selected by the demultiplexer DMUX, and the defective address to be repaired is written. FIG. 2 shows a truth table of the demultiplexer DMUX. The demultiplexer DMUX outputs the contents of the output of the counter CNT (in FIG. 2 (a) and FIG. 2 (b), the inputs A to N of the demultiplexer DMUX) (whether they are LOW level (L) or HIGH level (H)). Thus, the LOW level of the outputs Y0 to Yn is shifted. An example of the demultiplexer DMUX is SN74LS139 (see Texas Instruments TTL data book).
[0021]
The gates GTA to GTN of the redundant relief address storage memory cell arrays RCA to RCN are gates that are opened when a LOW level is input, and are selected by the gate selection switch circuits SWA to SWN and written with data. FIG. 3 shows a circuit diagram of the gate selection switch circuits SWA to SWN. In this gate selection switch circuit, the P-type transistors TR1 and TR2 are turned ON when a LOW level is applied to the gate of the transistor. When the write enable signal FWE is at the LOW level, the P-type transistor TR1 is turned on, and the output level of the demultiplexer DMUX shown in FIG. 2 is input to the gates GTA to GTN as it is through the resistor R3. At this time, the defective address data to be repaired written in the redundant repair address storage memory cell arrays RCA to RCN shown in FIG. 1 is input from the address ADR. On the other hand, when the write enable signal FWE is at the HIGH level and the read enable signal FOE is at the LOW level, the P-type transistor TR2 shown in FIG. 3 is turned on, and the LOW level is given to all the gates GTA to GTN by the pull-down resistor R4. It is done. As a result, all the gates GTA to GTN are opened, and all the data written in the redundant relief address storage memory cell arrays RCA to RCN are output to the redundant relief data comparison circuit COMP. In the OR circuit OR shown in FIG. 3, since the write enable signal FWE is a negative input, even if the write enable signal FWE and the read enable signal FOE simultaneously become HIGH level, the P-type transistors TR1 and TR2 Are not turned on at the same time.
[0022]
When the address of the semiconductor memory element MEM is inputted to the address ADR, the redundancy relief address data written in the redundancy relief address storage memory cell arrays RCA to RCN and the inputted address ADR are compared by the redundancy relief data comparison circuit COMP, When the two match, the redundant relief signal RS becomes LOW level.
[0023]
FIG. 4 shows a circuit diagram of the redundancy repair data comparison circuit COMP in the present embodiment. Each data written to the redundant relief address storage memory cell arrays RCA to RCN is determined to match or not match by the input address ADR and the exclusive OR circuits XORA to XORN. The LOW level is output by ORN. The logical sum circuits ORA-ORN are logically ANDed by a logical product circuit AND, and if any one of the logical sum circuits ORA-ORN outputs a LOW level, the logical product circuit AND becomes a LOW level. The output of the AND circuit AND becomes the redundancy relief signal RS. For example, the respective bits RCA1 to RCAn of the redundant relief storage memory cell array RCA are compared with the respective bits ADRA1 to ADRAn of the address ADR by the exclusive OR circuits XORA1 to XORAn. When the data of the bits RCA1 to RCAn and the data of the bits ADRA1 to ADRAn all match, the exclusive OR circuits XORA1 to XORAn are all set to the LOW level, and the output of the OR circuit OR is set to the LOW level. When the output of ORA becomes LOW level, the redundancy relief signal RS output from the AND circuit AND also becomes LOW level.
[0024]
In FIG. 1, the semiconductor memory element MEM has a normal memory cell SMC and a spare memory cell SC for redundancy relief. When the redundancy relief signal RS becomes LOW level, the address ADR input to the semiconductor memory element MEM accesses the spare memory cell SC for redundancy relief, and replaces the defective normal memory cell with the spare memory cell. Replace with Normally, since the redundancy relief signal RS is at the HIGH level by the pull-up resistor R1, the normal memory cell SMC of the semiconductor memory element MEM is accessed. Further, even if the initial value of the redundant relief address data stored in the redundant relief address storage addresses RCA to RCN is 0, for example, it is a spare memory cell for redundancy relief when 0 is input to the address ADR. The SC is only accessed, and there is no inconvenience in use. Since the redundancy relief signal RS is output both at the time of writing and at the time of reading, the spare memory cell of the semiconductor memory element MEM is selected in both cases of writing and reading.
[0025]
Hereinafter, the configuration and operation of each of the nonvolatile semiconductor memory element FM and the semiconductor memory element MEM will be described.
[0026]
FIG. 5 is a block diagram of a nonvolatile semiconductor memory element having a floating gate according to this embodiment. The nonvolatile semiconductor memory device FM has a normal memory cell array FMC (for example, used as a normal FLASH memory in a mobile phone or the like) and redundant relief address storage memory cell arrays RCA to RCN. The normal memory cell array FMC and other portions are separate power sources, and voltages are supplied from the respective power sources FVCC and SVCC.
[0027]
When writing redundant relief address data to the redundant relief address storage memory cell arrays RCA to RCN, a clock is input from the write enable signal FWE to count up the counter CNT, and the output of the counter CNT is input to the demultiplexer DMUX. Then, according to the output of the demultiplexer DMUX, the gate selection switch circuits SWA to SWN select the gates GTA to GTN, and the gates GTA to GTN are sequentially opened, so that the redundant relief address data is stored in the redundant relief address storage memory cell arrays RCA to RCN. Written.
[0028]
When the read enable signal FOE is at the LOW level and the write enable signal FWE is at the HIGH level, the LOW level is simultaneously input to the gates GTA to GTN, and the gates GTA to GTN are all opened. As a result, all the data written in the redundant relief address storage memory cell arrays RCA to RCN are simultaneously output. Data output from the redundant relief address storage memory cell arrays RCA to RCN is compared with the address ADR by the redundancy relief data comparison circuit COMP. If even one of the data in the memory cell arrays RCA to RCN for redundant relief address coincides with the address ADR, the redundant relief signal RS becomes LOW level. This redundant relief signal RS is normally at a HIGH level by the pull-up resistor R2. Note that reading and writing to the normal memory cell array FMC are performed by command input or the like as in the normal FLASH memory.
[0029]
FIG. 6 is a block diagram of a semiconductor memory element having a redundant relief function according to this embodiment. When the address ADR is input to the semiconductor memory element MEM, the normal memory cell SMC is accessed via the decoder or the spare memory cell SC for redundancy relief is accessed depending on the state of the redundancy relief signal RS. Is decided. Since the control method for selecting the SC address from the SMC address by the redundancy repair signal RS is the same as the redundancy repair method for a normal SRAM or the like, the description thereof is omitted here.
[0030]
This redundant relief signal RS plays the same role as the redundant relief signal in the prior art shown in FIG. 8, and is normally at the HIGH level by the pull-up resistor R1. For example, by setting the redundancy relief signal RS to the LOW level at the time of the wafer test, it is possible to access the spare memory cell SC that could not be accessed except by fuse cutting. It becomes possible to test the memory cell SC.
[0031]
In the above embodiment, as the nonvolatile semiconductor memory element FM having a floating gate, a ferroelectric memory (FeRAM), EEPROM, magnetic memory (MRAM) or the like can be used in addition to the FLASH memory. . In addition to the SRAM, a DRAM, a mask ROM, or the like can be used as the semiconductor memory element MEM having a redundant relief function.
[0032]
【The invention's effect】
As described above in detail, according to the present invention, since it is possible to perform redundancy relief of a semiconductor memory element, which has been conventionally performed in a wafer state, after packaging, even if a defective memory cell occurs due to burn-in or the like. By redundant relief, it can be made non-defective and the yield is improved. Further, since it is not necessary to perform redundant relief during the wafer test of the semiconductor memory element, the number of wafer test steps can be reduced, and the manufacturing cost can be reduced. In addition, since a conventionally used composite memory can be used, it is not necessary to develop a new technology. Furthermore, since the same memory cell is used as a spare memory cell used for relief, there is no change in characteristics. In addition, since a storage unit for storing a defective address for redundancy relief is provided in a nonvolatile semiconductor storage element using a floating gate of a composite memory that has been conventionally used, there is no problem in terms of process, and characteristics of There is no change. Further, by inputting a redundant relief signal to the semiconductor memory element during the wafer test, it becomes possible to access the spare memory cell portion. Therefore, even if redundancy repair is possible at the time of a wafer test, it is possible to screen a chip in which a defect exists in a spare memory cell, and it is possible to prevent a failure due to redundancy repair after packaging. In particular, in the case of a composite memory, if it becomes defective after packaging, even if the non-volatile semiconductor memory element enclosed at the same time is a non-defective product, the composite memory becomes defective and is processed as a defective product. Screening is very important and leads to significant cost reduction.
[Brief description of the drawings]
FIG. 1 is a block diagram of a composite memory in which a nonvolatile semiconductor memory element having a floating gate and a semiconductor memory element having a redundancy relief function according to an embodiment of the present invention are enclosed in the same package.
FIGS. 2A and 2B are truth tables of a demultiplexer in a composite memory according to an embodiment of the present invention.
FIG. 3 is a gate selection switch circuit in the composite memory according to the embodiment of the present invention.
FIG. 4 is a redundant relief data comparison circuit in the composite memory according to the embodiment of the present invention.
FIG. 5 is a block diagram of a nonvolatile semiconductor memory element having a floating gate in the composite memory according to one embodiment of the present invention.
FIG. 6 is a block diagram of a semiconductor memory element having a redundant relief function in a composite memory according to an embodiment of the present invention.
FIG. 7 is a wafer test flow of a conventional semiconductor memory device.
FIG. 8 is a diagram for explaining a conventional semiconductor memory device that performs redundancy relief by trimming fuses;
[Explanation of symbols]
A to N Demultiplexer input ADR addresses ADRA1 to ADRAn, ADRB1 to ADRN1 address bits AND logical product circuit CNT counter COMP redundant relief data comparison circuit DMUX demultiplexer FCE chip enable terminal FM nonvolatile semiconductor memory Memory element FMC Normal memory cell array FOE of nonvolatile semiconductor memory element Read enable signal FVCC Power supply FVCC
FWE Write enable signal GTA to GTN Gate MEM Semiconductor memory element OR OR circuit OR to ORN OR circuit R1, R2, R3, R4 Resistor RCA to RCN Redundant relief address storage memory cell arrays RCA1 to RCAn, RCB1 to RCN1 Redundant relief memory Each bit RS of the memory cell array Redundancy relief signal SC Normal memory cell SCE of the semiconductor memory element Chip enable terminal SMC of the semiconductor memory element Spare memory cell SVCC for redundancy relief of the semiconductor memory element Power supply SWA to SWN Gate selection switch circuit TR1, TR2 P-type transistors XORA to XORN, XORA1 to XORAn, XORB1 to XORN1 Exclusive OR circuit Y0 to Yn Output of demultiplexer

Claims (3)

Nonvolatile semiconductor memory elements each configured in an array by a plurality of nonvolatile memory cells each having a floating gate, and redundant relief semiconductor memory elements each configured by an array of volatile memory cells in the same package A composite memory encapsulated in,
The semiconductor memory element for redundancy repair is constituted by an array of the volatile memory cells, and a volatile normal memory unit in which data is stored in each of the volatile memory cells constituting the array, and the volatile memory A spare memory unit configured by an array of cells and used when a failure occurs in a volatile memory cell in the normal memory unit ;
The nonvolatile semiconductor memory element is constituted by an array of nonvolatile memory cells, and a nonvolatile normal memory unit in which data is stored in each nonvolatile memory cell constituting the array of nonvolatile memory cells, When a failure occurs in the volatile memory of the volatile normal memory unit in the redundant relief semiconductor memory element , which is constituted by an array of nonvolatile memory cells , a defective address which is an address of the defective volatile memory cell is A redundant relief address storage memory unit for storing, and a redundant relief signal output unit for outputting a redundant relief signal to the redundant relief semiconductor memory element when an externally input address matches the defective address ,
The redundancy repair for the semiconductor memory device has a redundancy repair signal input portion to which the redundancy repair signal is input, when the redundancy repair signal is input to the redundant repair signal input section, of the volatile normal memory composite memory, characterized in that is adapted to select said spare memory instead. 2. The second power supply voltage different from the power supply voltage supplied to the nonvolatile normal memory section in the nonvolatile semiconductor memory element is supplied at the time of reading and writing data from the redundant relief semiconductor memory element. Compound memory described in 1. The composite memory according to claim 2, wherein the second power supply voltage is supplied to the redundant relief address storage memory unit in the nonvolatile semiconductor memory element .

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