JPH0512735B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to addition in a data flow type computer,
The present invention relates to a queuing circuit that controls data queuing and operation start for binary operations such as subtraction.

(Prior art) Regarding data flow type computers, Nikkei Electronics, May 28, 1979 issue, P64-P81, June 11, 1979 issue, P92-P109, published by Nikkei McGro-Hill,
It is described in detail on pages 116 to 131 of the June 25, 1979 issue.

In a data flow type computer, when performing a binary operation such as addition or multiplication, the operation is started immediately when two pieces of data to be operated on are input to the operation section. When two pieces of data arrive at the arithmetic unit at different times, it is necessary to make the data that arrived first wait in a waiting circuit until the other data arrives. When the other data is input, that data is output to the arithmetic circuit together with the other paired data stored in the queuing circuit.

FIG. 1 shows a block diagram of an example of a binary operation section of a general data flow type computer. Input data 49
is input to the waiting circuit 50 of the binary operation section together with the variable name 100 of the data. Since the input data is input serially one word at a time, the waiting circuit is
Prepare the pair data for the binary operation, that is, the operation input A data 52 and the operation input B data 53,
Both data 52 and 53 are output to the binary arithmetic circuit 51. The binary operation circuit 51 performs a predetermined binary operation on both of these input data 52 and 53, and outputs the operation result as operation output data 54.

An example of a prior art configuration of this queuing circuit 50 is shown in a block diagram in FIG. The variable name 100 is an 8-bit numerical value attached to each input data 49 for data identification. Generally, in a dataflow type computer, each piece of data has a variable name.
When input to the calculation unit, the variable name of the data to be calculated, the contents of the calculation such as addition/reduction, the new variable name 101 to be given to the calculation result, etc. are determined by the variable name. The waiting circuit uses this variable name 100 to identify the other party's data to be operated on. If multiple data are given the same variable name, they will be interpreted as a series of data strings. The operation partner of the data string is also a data string, and the data strings that are arranged in the same order, that is, the order in which they are input to the calculation unit are the same, are calculated.

The variable name conversion unit 1 includes a storage circuit, and stores a variable name conversion table in the storage circuit. According to the variable name conversion table, the variable name 10 attached to the data 49 input to the waiting circuit
0 is a new variable name 101 that is easy to handle in the waiting circuit
and a data matching flag 104. The variable name conversion unit 1 converts variable names 100 attached to two data pairs to perform a binary operation.
is the new variable name 1 that is the same in each pair
01 and a data matching flag 104 that is different for each pair. For example, if the variable names 100 attached to two data 49 forming a pair are A and B, respectively, the variable name C common to both data is output as the variable name 101, and the matching flag is used for both data. "1" and "0" are added and output. The variable name 100 consists of 8 bits, the converted new variable name 101 consists of 7 bits, and the data matching flag 104 consists of 1 bit.

When the variable name 100 is converted into a new variable name 101 by the variable name conversion unit 1, this new variable name 101
The base address 110, read count value 111, write count value 112, and maximum word count 113 are read out from the received base address section 10, read counter 3, write counter 4, and maximum word count section 11, respectively.
Further, the read/write control section 2 includes an internal memory circuit, and stores a data matching table in this memory circuit. This data matching table records whether the variable name 101 has already been input or not, and if the variable name 101 has already been input, whether the data matching flag 104 of the input data is "1" or "0" is recorded. Every time data is input to the queuing circuit, the operation of the queuing circuit is determined based on the new variable name 101 of the input data, the data matching flag 104, and the data matching table of the read/write control section 2.

FIG. 3 is a diagram illustrating how the variable name 100 input to the variable name converter 1 of the queuing circuit is converted. In the read/write control section 2, there are data matching tables 105 and 106 of 1 bit each for H and L. There are already 10 variable names
1 has been input into the matching memory 8 and the data matching flag 104 is "1", the data matching table H105 in the read/write control unit 2 is set to "1". . Conversely, when data with the data matching flag 104 being "1" is input to the matching memory 8 of the matching circuit, the data matching table L106 is set to 1. When there is no data waiting for the variable name 101 in the matching memory 8, the data matching tables H105 and L106 of the address corresponding to the variable name 101 are both "0". This matching table 1
Depending on the state of the matching flag inputted as 05, 106, there are three cases in which the matching circuit shown in FIG. 2 operates.

The first case is when data of a certain variable name 101 is input and the values of the data matching tables H105 and L106 corresponding to this variable name 101 are both "0". In this case, the data is written into the queue memory 8 by calculating the sum of the base address 110 of the base address section 10 and the write count value 112 of the write counter 4 in the adder 12, and using this sum as address 115. . Multiplexer 5 selects the write count value 112 and sends it to adder 12. Then, when the data matching flag 104 input to the read/write control unit 2 at that time is "1", the variable name 1 of the data matching table H105
When the data matching flag 104 is "0", the area addressed by the variable name 101 of the data matching table L106 is set to "1". Further, the write count value 112 of the write counter 4 is incremented.

Second, a certain variable name 101 is input, this data matching flag 104 is "1", and the value of the area corresponding to the variable name 101 in the data matching table H105 is "0" in the data matching table L.
This is a case where the value of the area corresponding to the variable name 101 in 106 is "1". At this time, it means that the waiting memory 8 stores data that is paired with the input data. The input data is output as it is to the arithmetic circuit connected next to the waiting circuit, and at the same time it is output to the base address section 10.
The value obtained by adding the base address 110 and the read count value 111 of read counter 3 is set to address 115.
The value 116 read out from the queue memory 8 as a pair of data is output to the arithmetic circuit. And the read count value of this read counter 3 is 111
Increment. The input data matching flag 104 is “0” and the data matching table H105 is “1” data matching table L10
It operates in exactly the same way when 6 is "0".

Third, a certain variable name 101 is input, the data matching flag 104 is "1", the value of the area corresponding to the variable name 101 of the data matching table H105 is "1", and the value of the area corresponding to the variable name 101 of the data matching table L106 is "1". This is a case where the value of the area corresponding to variable name 101 is "0". At this time, data having the same variable name as the variable name 100 of the input data is stored in the waiting memory 8. Therefore, the input data is the base address 110 of the base address section 10 and the write count value of the write counter 4.
112 is written into the queue memory 8 as address 115. Then, the write count value 112 of the write adapter 4 is incremented by one. The data matching flag 104 is "0", the value of the area corresponding to the variable name 101 of the data matching table H105 is "0", and the data matching table L1
Exactly the same behavior occurs when the value of the area corresponding to variable name 101 of 06 is "1".

In the second case, when the read count value 111 is incremented and becomes equal to the write count value 112, it means that there is no longer any waiting data in the waiting memory 8, and the variable name of the data matching table H105, L106 The values of the areas corresponding to 101 are both set to "0". This is comparator 1
3. In the second or third case, when the read count value 111 or the write count value 112 becomes equal to the maximum number of words 113 as a result of incrementing, the read count value 111 or the write count value
112 is cleared. The maximum number of words 113 indicates the size of the queue memory 8 allocated to the variable name 101.

In the third case, when the write count value 112 becomes equal to the read count value 111 as a result of incrementing, that is, when the write count value 112 catches up with the read count value 111, the number of words of the input data allocated to the queue memory 8 This means that the message was written for a meeting. 1 variable name 10
Since the size of the queue memory 8 allocated to 1 has only the value of 113, the maximum number of words corresponding to the variable name 101, only the data with the same variable name 101 and the same data matching flag 104 can be consecutively stored with the maximum number of words.
If a value greater than 113 is input, data will overflow from the waiting memory 8 as shown above. in this case,
Overflowing data disappears and cannot be processed correctly. Base address 1 in Figure 4
10 shows the relationship between the read count value 111, the write count value 112, the maximum number of words 113, and the address of the waiting memory 8.

The capacity of the queuing memory 8 is limited due to physical constraints such as the number of integrated circuits. Therefore, in the conventional waiting circuit, it is impossible to allocate a large memory size to one variable name 101. Therefore, in conventional queuing circuits, care must be taken to limit the flow rate of data so that data does not overflow from the queuing memory when creating a program for a data flow computer, and since there is a limit to the data flow rate,
A drawback is that it is difficult to operate a dataflow computer efficiently.

(Object of the Invention) An object of the present invention is to provide a queuing circuit that prevents data from overflowing from the queuing memory even if the storage capacity of the queuing memory is limited.

(Structure of the Invention) The queuing circuit in the data flow type computer according to the present invention includes a memory having a plurality of blocks for temporarily storing data that arrives first for queuing data; and data attached to input data. a variable name conversion unit that generates a new internal variable name from a variable name for identification and a data matching flag of at least 1 bit indicating which of two pairs of data having the same internal variable name; a read counter that has an address for each internal variable name and generates an element of a read address of the memory; a write counter that has an address for each internal variable name and generates an element of a write address to the memory; Each time data is input, whether data having the same internal variable name is stored in the memory or data paired with data having the same internal variable name is read from the memory is determined by the data matching flag and the pair. In order to indicate whether or not data is stored in the memory, either one is set or reset according to the value of the data matching flag attached to the data when writing or reading data to the memory. Writing input data when data with the same internal variable name is not stored in the memory, based on the theoretical values of the first and second data matching tables corresponding to the internal variable name. and increments the write counter, sets the value of the data matching table corresponding to the internal variable name attached to the data written at that time and the data matching flag, and matches the input data with the pair. When data is stored in the memory, it instructs the reading of the stored data, increments the read counter, and sets the internal variable name attached to the data read at that time and the data matching flag. A read write that resets the value of the corresponding data matching table and, when data with the same internal variable name as the input data is stored in the memory, instructs writing of the input data and increments the write counter. a control unit; comprising an address conversion table for addressing the output of each of the read counters or the write counters to a block corresponding to the memory in response to reading or writing; an address conversion unit that receives the plurality of bits of the memory and the internal variable name as input and generates the upper plurality of bits of the memory read or write address as a block address; and stores all the divided blocks of the memory as usable blocks in an initial state. When writing each piece of data corresponding to the internal variable name to the memory, the outputs of the read counter and the write counter are checked, and if the output values are both zero, the paired data is determining that the block is not stored in the memory, and specifying the first number of the usable block as a block address in a word specified by the internal variable name of the address conversion table and the upper bit group of the write counter;
When it is determined that the write data exceeds the capacity of one divided block, the start number of another available block is set to the word specified by the same internal variable name of the address conversion table and the upper bit group of the write counter. The address conversion table is rewritten by specifying it as the block address to be assigned, and when it is determined that the paired data has already been written to the memory, all the written data is read out and the block becomes empty. It has an address control unit that manages it as a usable unused block.

(Example) Next, the present invention will be explained in detail with reference to Examples.

FIG. 5 is a block diagram of one embodiment of the present invention. This embodiment includes a variable name conversion section 1, a read/write control section 2, a read counter 3, a write counter 4, an address multiplexer 5, an address conversion section 6, an address control section 7, and a queue memory 8.

The variable name conversion unit 1 converts the variable name 100 attached to the data 49 into a new variable name (internal variable name) 101 and a data matching flag 104 based on a variable name conversion table stored in an internal storage circuit. do. The read/write control unit 2 uses the variable name 101
In accordance with the data matching flag 104, it is controlled whether to write the data 49 to the matching memory 8 or to read the partner of the data 49 from the matching memory 8. The read counter 3 and the write counter 4 are counters for generating a read address and a write address for the queue memory 8, respectively, and are composed of a memory for holding an address for each variable name and an adder. The multiplexer 5 alternately switches the outputs of the read counter 3 and the write counter 4 in synchronization with the clock from the read/write controller 2, and outputs the output from the waiting memory 8.
and is output to the address converter 6 (however, writing and reading in the queue memory 8 are not necessarily performed alternately). Address conversion section 6
stores an address conversion table in its internal storage circuit, and generates the address high-order bits of the queuing memory 8 by comparing the upper bits of the output of the multiplexer 5 and the variable name 101 with the address conversion table. The address control unit 7 has a read count value.
111 and write count value 112, outputs address conversion table rewriting data 117, and controls rewriting of the address conversion table.

This embodiment is a waiting circuit in which the variable name 100 has 8 bits and the waiting memory 8 has 64K words. Variable name 1
Since 00 is 8 bits, it is necessary to have a conversion table for each variable name, and the variable name conversion table is
256 words are required. This variable name conversion table is provided in the variable name conversion section 1. At this time, the new variable name 101 consists of 256 words of data, which constitutes pair data, so it consists of half of the data, 128, or 7 bits.
The operation of the variable name conversion table is exactly the same as the conventional method shown in FIG.
Convert to 4. This variable name 101 is the data matching flag 10 input to the read/write control unit 2.
The operation to the waiting memory 8 is determined by the state of 4.

Variable name 100 attached to input data 49
is the third variable name conversion table of variable name conversion section 1.
As shown in the figure, a 1-bit data matching flag 104 indicates which of the paired data is.
and an internal variable name 101 representing a set of paired data, and this internal variable name 101 is input to the read/write control unit 2 shown in FIG.

The read/write control unit 2 is equipped with data matching tables 105 and 106 shown in FIG. It is determined whether the data matching flag 104 between the input data and the data already stored in the waiting memory 8 is the same.

When the data paired with the input data 49 is not stored in the matching memory 8 (when the data matching tables H105 and L106 are both "0"), this input data 49 is written to the matching memory 8, and the write counter 4 Increment.

At this time, the data matching flag 104 is “1”
If so, the area corresponding to the variable name 101 in the data matching table H105 is set to "1", and if the data matching flag 104 is "0", the area corresponding to the variable name 101 in the data matching table L106 is set to "1". Write 1”.

When the data paired with the input data 49 has already been stored in the matching memory 8 (the data matching flag 104 is "1" and the data matching table H105 corresponding to the variable name 101 is "0",
When L106 is "1", or the data matching flag 104 is "0" and the data matching table H105 corresponding to the variable name 101 is "1",
When L106 is "0"), the read counter 3 instructs to read the pair data from the queue memory 8 and increments the read counter 3.

When data that has the same variable name as the input data but is not paired with this input data is already stored in the matching memory 8 (the data matching flag 104 is "1" and the variable name 10
When the data matching table H105 corresponding to 1 is "1" and L106 is "0", or the data matching flag 104 is "0" and the variable name 10
1), this input data 49 is written to the matching memory 8, and the write counter 4 is incremented.

According to the conventional method, the output of lead adapter 3
111 is added to the output 110 of the base address section 10 and then directly addresses the queue memory 8. However, in this embodiment, only the lower 8 bits of the output address of the multiplexer 5 are used as the address of the queue memory 8, and the upper 8 bits are used as the variable name 10.
It is input to the address conversion unit 6 together with the 7 bits of 1.

FIG. 6 is a block diagram showing in detail the input/output of the address translation section 6. This address conversion unit 6 is
It has an 8-bit memory circuit with a capacity of 32K words, and an address conversion table is stored in this memory circuit. A variable name 101 is connected to the upper 7 bits of the address line of the address conversion table, and the upper 8 bits of the output of the multiplexer 5 are connected to the lower 8 bits. With this configuration, the waiting memory 8 can be divided into blocks for every 256 words. By dividing the matching memory 8 into blocks in this way, if there is a large amount of waiting data per variable name and the size of the matching memory 8 is insufficient, the number of matching words per variable name can be increased in that block unit. It becomes possible.

FIG. 7 shows that the address conversion table of the address conversion section 6 is the output of the multiplexer 5 (read count value
111 or write count value 112) into an address of the waiting memory 8. The upper 7 bits of the input address of the address conversion table are variable names 101, and the conversion table has 256 words for each variable name 101.

In this embodiment, first, one block of the waiting memory 8 is allocated to a variable name that may be input. Here, one block of the waiting memory has 256 words and a block number is assigned to each block. When one block of waiting memory is allocated, a block number equal to the above allocated block number is set in the 256 word area to which the same variable name of the address translation table is allocated. In addition,
The purpose of setting equal block numbers is to protect data in blocks used by other variables from being destroyed even if an error occurs in the program.

If the upper 8 bits of read count value 111 and write count value 112 are different, different words in the address translation table are being accessed. At this time,
It is necessary to change the contents of the address conversion table indicated by the write count value 112 to a different block number.
That is, one block is assigned to this variable name.
At this time, the address control section 7 manages unused blocks, sets the contents of the address conversion table to a new block number, and marks the block as used. With this method,
If only one type of variable name is entered, 256 blocks, or 64K words, of queue memory can be allocated to this variable name. Similar to the traditional method,
When paired data is input, the waiting memory 8
The contents of are read and the read count value 111 is incremented. Blocks in the waiting memory 8 that are no longer needed are again marked as unused blocks by the address control unit 7.

Next, details of the operation of rewriting the address conversion table and allocating an unused portion of the waiting memory 8 will be explained.

The address control unit 7 stores and manages block addresses of available memory blocks in the waiting memory 8. Since no data is stored in the waiting memory 8 at the time of initial setting by turning on the power, resetting, etc., all divided blocks of the waiting memory 8 become usable blocks. data 49
is input and data with a certain attached variable name is written to the waiting memory 8, the write count value 112 and read count value 111 are checked. As a result of the inspection, if the write count value 112 and read count value 111 are both "0" (no data), set the first block number of the unused block group to a variable in the address conversion table to write new data. The block address 1 is stored in the word specified by the name and the upper 8 bits of the read count value or write count value.
Output as 17. The block with this first block number is managed as a used block.

If the writing continues and the number of data is more than an integer multiple of one memory block, for example, when writing the 257th word,
In other words, if the upper 8 bits of the write count value 112 (the bits indicating 256) change, the first block number of the unused block group is used as the variable name in the address conversion table and the upper 8 bits of the write count value. block address 1 in the word specified by
Output as 17. Then, the block with the outputted first block number is managed as a used block. This means that a new block of 256 words has been secured.

When data with various variable names are input one after another, each block in the waiting memory 8 can be assigned as many variable names as the block numbers of unused blocks managed by the address control section 7.

On the other hand, when data with a certain variable name is stored in the waiting memory 8 and data paired with that data is input, that is, the lead count value 111
When the upper 8th bit of the block changes (when all the blocks are read), the corresponding block of the waiting memory 8 which becomes empty after reading out the paired data of the waiting memory 8 is managed as an unused block.

In this embodiment, the variable name 100 is 8 bits, the capacity of the queue memory 8 is 64K words, and the address conversion table is 32K words (8 bits), but it is clear that the present invention can be realized with other combinations.

(Effects of the Invention) As explained above, the present invention converts the outputs of a read counter and a write counter using an address conversion table, and controls the contents of the address conversion table using an address control unit, thereby converting a specific variable into Even when waiting data is concentrated for a variable name, an unused portion of the matching memory can be allocated as matching memory for that variable name, so the limited size matching memory can be used effectively. As described above, according to the present invention, it is possible to provide a queuing circuit in which data does not overflow from the queuing memory even if the storage capacity of the queuing memory is limited. Therefore, if data flow arithmetic processing is performed using the queuing circuit of the present invention, there is little risk of overflowing the queuing memory, so there is usually no need to limit the data flow rate, and extremely high-speed and highly efficient arithmetic processing is possible. becomes. Further, since the program for a data flow computer equipped with the queuing circuit of the present invention requires little attention to the prevention of data overflow from the queuing memory, the program can be created easily and quickly.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a binary operation unit in a general data flow computer, Figure 2 is a block diagram of a conventional queuing circuit, and Figure 3 explains the operation of the conventional queuing circuit shown in Figure 2. FIG. 4 is a diagram explaining address generation of the queuing memory in the queuing circuit of FIG. 2, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. A diagram showing the input and output of the converter 6 in detail,
FIG. 7 is a diagram showing an example of address conversion using the address conversion table in the embodiment of FIG.

Claims (1)

[Claims] 1. A memory having a plurality of blocks for temporarily storing data that arrives earlier in order to wait for data; a variable name conversion unit that generates a variable name and a data matching flag of at least 1 bit indicating which of two pairs of data having the same internal variable name; and an address for each internal variable name; a read counter that generates an element of a read address of the memory; a write counter that has an address for each internal variable name and generates an element of a write address to the memory; and a write counter that generates an element of a write address to the memory; The data matching flag indicates whether data having the same internal variable name is stored in the memory or data paired with data having the same internal variable name is read from the memory, and whether paired data is stored in the memory. The first and second variables corresponding to the internal variable names are set or reset depending on the value of the data matching flag attached to the data when writing or reading data to the memory to indicate the state. and the logic value of the second data matching table, and when data with the same internal variable name is not stored in the memory, the input data is instructed to be written, the write counter is incremented, and the write counter is incremented. When the value of the data matching table corresponding to the internal variable name attached to the written data and the data matching flag is set, and the data paired with the input data is stored in the memory. Instructs to read the stored data, increments the read counter, and resets the value of the data matching table corresponding to the internal variable name and data matching flag attached to the data read at that time. a read/write control unit that instructs writing of the input data and increments the write counter when data having the same internal variable name as the input data is stored in the memory; An address conversion table is provided for addressing the output of each of the read counters or the write counters to a corresponding block of the memory, and the upper bits of the output of the read counter or the write counter and the internal variable name are input. an address conversion unit that generates a plurality of high-order bits of the read or write address of the memory as a block address; and an address converter that stores all divided blocks of the memory as usable blocks in an initial state, and stores the blocks corresponding to the internal variable names. When writing each piece of data to the memory, the outputs of the read counter and the write counter are checked, and if the output values are both zero, it is determined that the paired data is not stored in the memory. specifying the first number of the usable block as a block address in the word specified by the internal variable name of the address conversion table and the upper bit group of the write counter;
When it is determined that the write data exceeds the capacity of one divided block, the start number of another available block is set to the word specified by the same internal variable name of the address conversion table and the upper bit group of the write counter. The address conversion table is rewritten by specifying it as the block address to be assigned, and when it is determined that the paired data has already been written to the memory, all the written data is read out and the block becomes empty. A queuing circuit in a data flow computer, comprising: an address control unit that manages the block as a usable unused block;