JPS6012185Y2 - data storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a data storage device for a programmable small electronic computer.

Conventional programmable small electronic calculators (hereinafter referred to as computers) use RAM (random access memory) as data memory, as shown in Figure 1, for example.
In addition, each row address area is set in a register (12 in the example shown).
It has a capacity of t5).

However, in general, 1wI of data is not stored in each register, and usually data of several digits is often stored.

For this reason, the upper digits of each register are unused, reducing usage efficiency and, of course, requiring a large-capacity RAM, which is uneconomical.

This invention was made to improve the above-mentioned points, and its purpose is to convert either the row address area or the row address area of the data memory of a programmable small electronic calculator into multiple data areas. An object of the present invention is to provide a data storage device that can store data by dividing it into two parts.

One embodiment will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a circuit diagram of the main part. In the figure, the program memory 1 stores the program inputted from the key input section (as shown) and is composed of a RAM, and as shown in FIG. It is divided into 6 digits (area B) and used.

In addition, program memory 1 has program data reading and writing operations controlled by a read/write signal R/W output from a CPU (central processing unit, as shown), and also receives a +1 signal output from the CPU. The address is designated by the output of the program counter 2, which performs a counting operation upon input.

Further, instruction data for each step read from the program memory 1 is given to an instruction decoder 3 via a data bus, and numerical data is given to a data memory 4, an arithmetic unit 5, a divided digit number storage circuit 6, and a multiplication circuit 7, respectively. It will be done.

The instruction decoder 3 decodes the input instruction data, and sends a read/write signal R/W to the data memory 4, an operation command signal to the multiplier circuit 7 and an adder circuit 8, which will be described later, and an AND gate 9, A gate control signal is given to each of 10 and 10, respectively.

In this embodiment, the data memory 4 is a RAM in which column addresses 0 to 11 are divided into four as shown in FIG. 4, and each divided column 0 to 3 can store three-digit data. be.

Then, by the output of the address register 11 which inputs and stores the output signal of the adder circuit 8, the column address 0 of each column is set.
~11 is specified.

The calculation unit 5 is composed of an adder circuit, a plurality of calculation registers, etc., and executes a predetermined calculation based on data input from the program memory 1 and the data memory 4, and sends the calculation result to the data memory 4 for storage.

The division digit number storage circuit 6 is a circuit that stores the division digit number of each column 0 to 3 outputted from the program memory 1 (in the embodiment, r3), and the division digit number stored in this circuit 6 is stored in the multiplication circuit. 7 and comparison operation circuit 12 immediately.

In this case, the multiplication circuit 7 simultaneously stores the program memory 1
, that is, data indicating a column of data to be read or written to the data memory 4.

Therefore, the multiplication circuit 7 multiplies the input data and outputs the multiplication result to the addition circuit 8 and the comparison calculation circuit 12.

In other words, the above calculation result indicates the minimum column address of the column of data to be read or written to the data memory.

The comparison calculation circuit 12 then stores the input divided digit number storage circuit 6.
The data r3J from and the above multiplication result are added to calculate the upper limit column address corresponding to the above minimum column address.

On the other hand, the adder circuit increments the above multiplication result by +1 using the +1 signal output from the CPU, and the addition result is sent to the address register 11 and used as a column address designation signal for the data memory 4. At the same time, the addition result is used for comparison operation. The data is sent to the circuit 12 and compared, and when both data match, a match signal is output from the comparison calculation circuit 12 and the output of the +1 signal to the addition circuit 8 is stopped.

As a result, the numerical data specified by the program in the program memory 1 is written into or read from the specified column in the data memory 4.

Next, the operation of the present invention configured as described above will be explained.

As shown in Figure 4, data 1 is placed in one column of row address 1.
12J is written, and this data 12Y is written to row address 2.
The operation will be explained by taking as an example the case where the data is stored in three columns.

That is, the operator manually inputs the program for the above-mentioned purpose and programs the data of steps 1 to 9 as shown in FIG.

In this case, a read/write signal R/W of a write command is given to the program memory 1 from the CPU.

First, in step 1, in order to divide the data memory, code data is divided into areas A and B, respectively, and the number of divided digits r.
Enter 3J.

This indicates that each column of the data memory has three digits.

Next, in steps 2 and 3, data 11yo and '2-1 are written in area B, respectively.

This indicates data "12yo" to be written into the data memory.

Next, in step 4, command data "MIN" is written in area A.

This command data "MINJ" is command data for writing the data r12J into the data memory 4 using the data in the next step 5.

Next, in step 5, data 11 is written to areas A and B, respectively.

Data r1 in area A. ．． ．． l indicates a row address of the data memory 4, and data r1j in area B indicates one column of the row address.

Next, in step 6, instruction data rMR is written in area A.

This command data rMR. is command data for storing the above-mentioned data 12J in the read-out calculation unit 5 according to the data in the next step 7.

Next, in step 7, data 11 is added to areas A and B, respectively.
Write.

The meaning of data rIJ in each area A and B is step 5
It is the same as that of .

Next, in step 8, the instruction data 'MIN' is stored in area A.
Write J, and then in step 9 write data 11 yo and r3 yo in areas A and B, respectively.

Next, when the above program starts executing, a read/write signal R/W of a read command is applied to the program memory 1 from the CPU.

First, the data of step 1 is read out and stored in the division digit number storage circuit 6 with the division digit number 13. is set via the AND gate 10, and this divided digit number 131 is given to the multiplication circuit 7 and comparison operation circuit 12.

Next, in steps 2 and 3, the data 112 is stored in a predetermined register in the arithmetic unit 5 via the AND gate 9.

Next, in steps 4 and 5, the operation of writing the data 12 into one column of the row address 1 of the data memory 4 is executed.

In this case, the multiplication circuit 7 multiplies the number of divided digits being input, ``3J'', by the column data 11. from area B of the program memory, and the multiplication result 131 is used as the data memory 4.
The minimum column address 3 of is obtained and given to the adder circuit 8 and the comparison operation circuit 12.

Therefore, in the comparison calculation circuit 12, the input data r31,'
3 and y to calculate the upper limit address 6 for the minimum column address 3.

A +1 signal is output from the CPU to the adder circuit 8, which sequentially increments the initial value 3 by 1, and then outputs the column address signal 3.
4. 5. 6 is output and given to the data memory 4 via the address register 11.

Therefore, data 12 in the arithmetic unit 12 is transferred and written to one column of the row address 1 of the data memory 4.

Then, when the contents of the adder circuit 8 reach the upper limit column address 6, a match signal is output from the comparison calculation circuit 12, and the +1 signal from the CPU is no longer output.
Complete operation 5.

Next, the operation of step 6.7 is executed, and the operation of reading out the data written in the row address 1.1 column and writing it into a predetermined register of the arithmetic unit 5 is executed.

The operation in this case is similar to steps 4 and 5 described above.

Next, the operations in steps 8 and 9, that is, the data 1 in the calculation section 5
12J is stored in row address 2, column 3 in data memory 4.

In this case, the division digit number storage circuit 6 similarly stores the division digit number 73.
J is set.

On the other hand, in the multiplication circuit 7, the number of divided digits r3. is multiplied by the data in area B (column 3), and the multiplication result, ie, the minimum column address 9, is calculated and given to the addition circuit 8 and the comparison calculation circuit 12.

Then, the comparison calculation circuit 12 adds the input divided digit number r3 and the minimum column address 9 to calculate and hold the upper limit column address 12.

On the other hand, in the adder circuit 8, +
1 operation is executed, and as a result, column addresses 9 to 11 of data memory 4 are sequentially specified, row address 2, column 3
Data 12J is written to.

Furthermore, the addition result of the adder circuit 8 is 112. When this happens, a match signal is output from the comparison calculation circuit 12, and the operations of steps 8 and 9 are completed.

In the above embodiment, the column address of the data memory 4 is set to 4.
Although it is divided, the number of division digits is arbitrary.

It is also possible to divide the row address into any number of digits.

Further, in the above embodiment, a case has been described in which data is written to or read from one column of the data memory 4, but this idea can be similarly applied to two or more columns.

Furthermore, in the above embodiment, the code data rD, . . . the number of division digits is input in order to divide the data memory 4 into the program memory 1, but the number of divisions may be input instead of the number of division digits. .

As explained above, this invention provides a data storage device in which either the row address area or the column address area of a data memory is divided into a plurality of data areas, and data can be stored in each data area. As a result, data memory usage efficiency is increased, and therefore, a large program can be processed with a small capacity data memory, and it is also highly economical.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the usage status of conventional data memory, Figure 2 is a diagram showing the usage status of conventional data memory.
3 to 3 show one embodiment of this invention, FIG. 2 is a circuit configuration diagram of the main part, FIG. 3 is a state diagram showing an example of a program assembled in the program memory 1, and FIG. 3 shows a storage state diagram of the data memory 4 according to the program shown in FIG. 3. FIG. 1...Program memory, 3...Instruction decoder, 4...Data memory, 5...Interval calculation unit, 6...Division digit number storage circuit,
7...Multiplication circuit, 8...Addition circuit, 1
2... Comparison calculation circuit.

Claims (1)

[Scope of utility model registration request] A programmable small-sized electronic calculator is provided with a data memory for storing calculation data, and a dividing means for dividing the data memory according to the number of division digits or the number of divisions inputted from the outside, and the data memory can be arbitrarily divided. A data storage device that can be divided to write and read calculation data.