JPH0934788A - Device and method for translating address - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily translate a physical address to a logical address. SOLUTION: An address translator 2 is provided with an inverse address translation table 5a for translating the physical address to the logical address and by referring to the inverse address translation table 5a of the address translator 2, the physical address in a physical address space 4 is translated to the logical address in a logical address space 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion device and an address conversion method, and is particularly suitable for application to an address conversion device and an address conversion method for converting a physical address into a logical address in a virtual memory system. .

[0002]

2. Description of the Related Art In a conventional address translation device, it is common to employ a virtual memory system in which the physical address space of a main memory device appears to be larger than it actually is and the physical address space of the main memory device is used efficiently. Is done in a regular manner. That is, as a region for storing a program, in addition to the physical address space of the main storage device, a logical address space virtually provided for executing a job is provided. The physical address space of the main storage device is also called a real address space, and the logical address space virtually provided for executing a job is also called a virtual address space. Then, there is a memory management system called virtual memory in order to associate the logical address space and the physical address space, and the virtual memory system includes a single virtual memory system and a multiple virtual memory system.

As shown in FIG. 16, the single virtual memory system exists in a virtual memory device, and exists in a logical address space 14 to which logical addresses are allocated, an address conversion table 15, and a main memory device. However, the physical address space 16 to which physical addresses are allocated is provided. And
A plurality of programs 1 are stored in one logical address space 14.
To n are stored, and the start addresses of the programs 1 to n are different.

On the other hand, the multiple virtual storage system, as shown in FIG. 17, corresponds to a plurality of logical address spaces 17 existing on a virtual storage device and assigned logical addresses, and each logical address space 17. It is provided with a plurality of provided address conversion tables 18 and a physical address space 19 existing in the main memory and having physical addresses allocated thereto.
Further, one program 1 to n is stored in one logical address space 17, and the start addresses of the programs 1 to n are the same. That is, since each logical address space 17 is independent and invisible from the other logical address spaces 17, each program 1 to n is
Are protected by each logical address space 17, and the same address is assigned to each virtual address space 17.

The logical address space 14 of FIG. 16 and FIG.
17, the physical address spaces 16 and 19 are divided into fixed-length areas called pages, as shown in FIG. In a general computer system, the size of one page is 4 KB (kilobytes), and each logical page 0 to n in the logical address space has logical page numbers 0 to n in order from the first logical page 0. The physical pages 0 to n in the physical address space are assigned physical page numbers 0 to n in order from the first physical page 0.

The address conversion tables 15 and 18 shown in FIGS. 16 and 17 are for converting a logical address into a physical address, and each logical page has one entry. As shown in FIG. 19, one entry includes a physical page number corresponding to a logical page number and control information such as a flag indicating whether the physical page number stored in the entry is valid.

Next, the operation of the conventional address translation device will be described. First, as shown in step S71 of FIG. 20, when a program is executed by the CPU of the computer system to perform page access processing, the logical addresses of the logical address spaces 14 and 17 of FIGS. 16 and 17 are referred to. As shown in FIG. 21, the content of the logical address is composed of a logical page number and an offset of a portion less than the size of one page.

Next, as shown in step S72, a logical page number is acquired from the contents of the logical address. next,
As shown in step S73, the entry corresponding to the logical page number is acquired by referring to the address conversion tables 15 and 18 of FIGS.

Next, in step S74, when the valid bit included in the control information of the entry is "1",
In step S76, the physical page numbers of the physical address spaces 16 and 19 of FIGS. 16 and 17 are obtained by referring to the physical page numbers of the acquired entries of the address conversion tables 15 and 18, as shown in FIG. . A physical address can be obtained from the physical page numbers of the address conversion tables 15 and 18 and the offset of the logical address, and the contents of the actual program stored in the physical address space can be accessed.

On the other hand, when the valid bit contained in the control information of the entry is "0" in step S74,
That is, when the program refers to the logical address and the physical page number does not exist in the process of acquiring the physical page number from the logical page number, the process proceeds to step S75 and CP
Page fault handling occurs where U raises a page fault interrupt to the operating system.

In this page fault processing, first, as shown in step S81, a logical page number is acquired from the contents of the logical address that caused the page fault. Next, as shown in step S82, the entry corresponding to the logical page number is acquired by referring to the address conversion tables 15 and 18 of FIGS.

Next, as shown in step S83, free physical pages in the physical address spaces 16 and 19 are acquired. Next, as shown in step S84, the physical page number of the physical page acquired in step S83 is set in the entry of the address translation tables 15 and 18 corresponding to the logical page number that caused the page fault.

Next, as shown in step S85, the valid bit contained in the control information of the entry in which the physical page number is set is set to "1". As described above, the physical page is assigned to the logical page that caused the page fault.
As described above, in the conventional address translation device, when the program refers to the logical address, the CPU and the operating system automatically calculate the physical address.

[0014]

However, in the conventional address translator, for example, a physical address can be easily translated into a logical address while the operating system inputs / outputs data from / to an input / output device such as a hard disk. I couldn't.

That is, the operating system is called to issue a request to the input / output device to store the data in the buffer prepared by the program. In this case, the operating system converts the logical address of the buffer prepared by the program into a physical address that can be understood by the input / output device so that the input / output device can exchange data. Then, an input / output request is made to the input / output device by the physical address. After that, when the I / O device finishes its operation, an I / O completion interrupt is sent to the operating system to notify the end of the operation. Then, when the interrupt from the input / output device rises,
The operating system checks the status of the I / O device to see if the I / O completed successfully.
Here, in the case of abnormal termination, the program is notified that an error has occurred, and error tracing and logging are performed to inform the user of information effective for debugging the program.

However, so that the program can understand, when the logical address of the buffer in which the error has occurred is added to the information such as trace and logging, the information of the I / O completion interrupt processing of the operating system and the information of the I / O device are added. Therefore, although the physical address of the buffer can be obtained, the logical address cannot be easily obtained. That is, the conventional address translation device has a problem that it is necessary to trace many resources managed by the operating system in order to translate a physical address into a logical address.

Therefore, an object of the present invention is to provide an address translation device and an address translation method that can easily translate a physical address into a logical address.

[0018]

In order to solve the above problems, according to the invention of claim 1, there is provided a reverse address conversion table for converting a physical address into a logical address.

According to the second aspect of the invention, the logical page number of the logical address corresponding to the physical address is stored in each entry of the reverse address translation table. According to the invention of claim 3, the logical page number of the logical address corresponding to the physical address and the identifier of the program using the logical address are stored in each entry of the reverse address translation table.

According to the invention of claim 4, the entry has flag information indicating whether or not the stored logical page number is valid. Further, according to the invention of claim 5, an entry of the reverse address translation table is provided corresponding to each physical page of the physical address space divided into a plurality of stages.

Further, according to the invention of claim 6, the physical address is converted into the logical address by referring to the reverse address conversion table for converting the physical address into the logical address.

Further, according to the invention of claim 7, the physical address space is divided into a plurality of stages, and the entry provided for each stage corresponding to each physical page of the physical address space is referred to. , Converts physical address to logical address.

[0023]

According to the invention of claim 1, by providing the reverse address conversion table for converting the physical address into the logical address, the conversion from the physical address to the logical address can be easily performed.

According to the second aspect of the invention, the logical page number of the logical address corresponding to the physical address is stored in each entry of the reverse address translation table, so that the reverse address translation table can be searched once. The logical page number can be obtained, and the physical address can be easily converted to the logical address.

According to the third aspect of the invention, the logical page number of the logical address corresponding to the physical address and the identifier of the program using the logical address are stored in each entry of the reverse address translation table. Therefore, even when the same logical address is assigned to each program, a specific program can be easily accessed by referring to the program identifier.

Further, according to the invention of claim 4, since the stored logical page number has flag information indicating whether or not the logical page number is valid, by referring to the flag information, the invalid logical page number can be obtained. It is possible to omit the process of calculating the logical address from

According to the fifth aspect of the invention, by providing an entry of the reverse address translation table corresponding to each physical page of the physical address space divided into a plurality of stages, it is possible to correspond to the discontinuous physical address space. Thus, the reverse address conversion table can be provided in a continuous area, and the area required for storing the reverse address conversion table can be reduced.

Further, according to the invention of claim 6, the physical address can be easily converted to the logical address by referring to the reverse address conversion table for converting the physical address to the logical address.

According to the invention of claim 7, the physical address space is divided into a plurality of stages, and the entry provided for each stage corresponding to each physical page of the physical address space is referred to. , Since the physical address is converted to the logical address, the reverse address conversion table can be provided in the continuous area corresponding to the discontinuous physical address space, and the area necessary for storing the reverse address conversion table. Can be reduced.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An address translator according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an address translation device according to a first embodiment of the present invention. In FIG. 1, a main storage device 1 having a physical address space 4 to which physical addresses are allocated
And the processing device 3 having the logical address space 6 to which logical addresses are allocated are connected via the address translation device 2 having the reverse address translation table 5a and the address translation table 5b. The physical address space 4 is divided into physical pages 0 to n, and the logical address space 6 is divided.
Are divided into logical pages 0 to m. The size of this one page is set to 4 KB (kilobytes), for example. The address conversion table 5b is for converting a logical address into a physical address, and each logical page 0 to m.
Each has one entry 0-m. The reverse address conversion table 5a is for converting a physical address into a logical address, and has one entry 0 to n for each physical page 0 to n. Then, physical page numbers 0 to n indicating physical pages 0 to n of the main storage device 1 and indexes 0 to 0 indicating entries 0 to n of the address translation device 2
It is equal to n. One entry 0
As shown in FIG. 2, n is composed of logical page numbers 0 to m corresponding to physical pages 0 to n and a valid bit which is a flag indicating whether the logical page number stored in the entry is valid. The logical page numbers 0 to m indicate the page numbers 0 to m of the logical addresses when the physical pages 0 to n are allocated corresponding to the indexes 0 to n of the reverse address conversion table 5a. The reverse address translation table 5a is provided in the processing device 3 including the logical address space 6.
The logical addresses defined by are secured in consecutive locations.

In the above configuration, for example, when an error occurs in the input / output interrupt processing routine of the operating system, and the error-causing physical address is converted into a logical address in order to debug this error, FIG. As shown, the physical address of the physical address space 4 of FIG. 3 is referred to. The content of this physical address is
It consists of physical page numbers 0 to n and an offset. And
As shown in FIG. 3, by referring to indexes 0 to n of the reverse address translation table 5a corresponding to physical page numbers 0 to n, logical pages 0 to 0 of the logical address space 6 are referred to.
Logical page numbers 0 to m corresponding to m can be obtained. Then, as shown in FIG. 4, this logical page number 0
The logical address can be easily obtained from the offset of ~ m and the physical address. For example, when the operating system has acquired the physical address 000025345H, the logical address is 00005345H by referring to the reverse address conversion table 5a in FIG.
Is easily understood.

The number of entries required for the reverse address translation table 5a is, for example, 16M for the main memory 1 of FIG.
For a computer system having a storage capacity of B (megabytes), as shown in FIG. 5, 4096 entries are required. For example, when the index of the entry starts from 0, the index is from 0 to 4095, and the physical address of the physical address space 7 of FIG.
The index at address 00H is 16. That is,
The physical page number and the entry index are equal.

Next, the operation of the address translator according to the first embodiment of the present invention will be described. Here, prior to the address conversion from the physical address to the logical address, FIG.
A page fault process for setting information in the reverse address translation table 5a is performed. That is, when a page fault interrupt occurs and the operating system allocates a free physical page to a logical page to create the address conversion table 5b, the reverse address conversion table 5a of FIG. 1 corresponding to the allocated physical page is displayed. create.

In this page fault processing, first, as shown in FIG.
As shown in step S1 of FIG. 1, a logical page number is acquired from the contents of the logical address of the processing device 3 in FIG.

Next, as shown in step S2, the entry corresponding to the logical page number is acquired by referring to the address conversion table 5b. Next, step S
As shown in FIG. 3, an empty physical page in the physical address space 4 of the main memory 1 is acquired.

Next, as shown in step S4, the physical page number of the physical page acquired in step S3 is set in the entry of the address translation table 5b corresponding to the logical page number that caused the page fault.

Next, as shown in step S5, the valid bit contained in the control information of the entry of the address conversion table 5b in which the physical page number is set is set to "1". Next, as shown in step S6, an entry of the reverse address translation table 5a having the same index as the physical page number of the obtained free physical page is obtained.

Next, as shown in step S7, the logical page number of the contents of the logical address which caused the page fault is set in the entry of the reverse address translation table 5a. Next, as shown in step S8, the valid bit of the entry of the reverse address translation table 5a is set to "1".

Next, based on the reverse address conversion table 5a created by the page fault process of FIG. 6, the address conversion process from the physical address to the logical address is performed.

That is, as shown in step S11 of FIG. 7, the physical page number is acquired from the contents of the physical address in the physical address space 4 of the main memory of FIG. Next, as shown in step S12, the address translation device 2
By referring to the reverse address translation table 5a of
Get the entry corresponding to the physical page number.

Next, as shown in step S13, when the valid bit of the entry is "1", step S14
Then, by referring to the logical page number of the acquired entry, the logical page number in the logical address space 6 of the processing device 3 is obtained. Then, as shown in step S15, the logical address can be obtained from the logical page number of the reverse address translation table 5a and the offset of the physical address.

On the other hand, when the valid bit of the entry is "0" in step S13, that is, when the logical page number does not exist in the process of acquiring the logical page number from the physical page number, the processes of steps S14 and S15 are performed. The process is terminated without performing the process.

Next, an address translation device according to a second embodiment of the present invention will be described with reference to the drawings. Second of the present invention
The embodiment is an example of an address translation device using the multiple virtual storage system.

In FIG. 1, when the address translation device 2 uses the multiple virtual storage system, the logical address space 6 of the processing device 3 is divided into a plurality of logical address spaces, and the divided logical address spaces are associated with each other. A plurality of address conversion tables 5b are provided. One program is stored in each of the divided logical address spaces, and the same logical address is assigned to each logical address space.

On the other hand, the respective entries 0 to n of the reverse address translation table 5a have physical pages 0 to n as shown in FIG.
Of the logical page numbers 0 to m, a valid bit that is a flag indicating whether the logical page number stored in the entry is valid, and an identifier that indicates the program currently being executed. The logical page numbers 0 to m indicate the page numbers 0 to m of the logical addresses when the physical pages 0 to n are allocated corresponding to the indexes 0 to n of the reverse address conversion table 5a.

In the above configuration, when converting a physical address into a logical address, the physical address in the physical address space 4 of FIG. 1 is referred to. The content of this physical address consists of physical page numbers 0 to n and an offset. Then, the logical page numbers 0 to m corresponding to the logical pages 0 to m of the logical address space 6 can be obtained by referring to the indexes 0 to n of the reverse address translation table 5a corresponding to the physical page numbers 0 to n. it can. The logical address can be easily obtained from the logical page numbers 0 to m and the offset of the physical address. Here, in the case of the multiple virtual memory system, one logical address space is allocated to one program, and the same logical address is allocated to each logical address space, so that it is stored in the reverse address conversion table 5a. One logical address space is specified by referring to the program identifier. The number of entries required for the reverse address translation table 5a is the same as in the first embodiment.

Next, the operation of the address translator according to the second embodiment of the present invention will be described. In the page fault process, first, as shown in step S21 of FIG. 9, a logical page number is acquired from the contents of the logical address of the processor 3 of FIG.

Next, as shown in step S22, by referring to the address conversion table 5b, the entry corresponding to the logical page number is acquired. Next, as shown in step S23, a free physical page in the physical address space 4 of the main memory 1 is acquired.

Next, as shown in step S24, the physical page number of the physical page acquired in step S3 is set in the entry of the address translation table 5b corresponding to the logical page number that caused the page fault.

Next, as shown in step S25, the valid bit contained in the control information of the entry of the address conversion table 5b in which the physical page number is set is set to "1".
Next, as shown in step S26, the entry of the reverse address translation table 5a having the same index as the physical page number of the obtained free physical page is obtained.

Next, as shown in step S27, the logical page number of the content of the logical address that caused the page fault is set in the entry of the reverse address translation table 5a.

Next, as shown in step S28, the valid bit of the entry of the reverse address translation table 5a is set to "1". Next, as shown in step S29, the identifier of the program currently being executed is set in the entry of the reverse address translation table 5a. In this case, the identifier of the currently executing program that caused the page fault can be easily retrieved by the operating system.

Next, an address conversion process from a physical address to a logical address will be described. First, as shown in step S31 of FIG. 10, a physical page number is acquired from the contents of the physical address in the physical address space 4 of the main storage device of FIG.

Next, as shown in step S32, the entry corresponding to the physical page number is acquired by referring to the reverse address translation table 5a of the address translation device 2.

Next, as shown in step S33, when the valid bit of the entry is "1", step S34
Then, by referring to the logical page number of the acquired entry, the logical page number in the logical address space 6 of the processing device 3 is obtained.

Next, as shown in step S35, a logical address is obtained from the logical page number of the reverse address translation table 5a and the offset of the physical address. next,
As shown in step S36, one logical address space is specified by acquiring the program identifier from the entry of the reverse address translation table 5a.

On the other hand, when the valid bit of the entry is "0" in step S33, that is, when the logical page number does not exist in the process of acquiring the logical page number from the physical page number, the processes of steps S34 to S36 are performed. The process is terminated without performing the process. Next, an address translator according to a third embodiment of the present invention will be described with reference to the drawings. The third embodiment of the present invention is an example of an address translation device in which a plurality of reverse address translation tables 5a of FIG. 1 are provided.

That is, the reverse address conversion table 5a of FIG. 1 comprises a final stage table for designating the logical page numbers 0 to m of the logical address space 6 and a front stage table for designating the next stage table. In the case of a single virtual memory, each entry 0 to n of the final stage table has logical page numbers 0 to m corresponding to physical pages 0 to n and logical page numbers stored in the entry, as shown in FIG. It consists of a valid bit which is a flag indicating whether it is valid. Further, in the case of multiple virtual storage, as shown in FIG.
Of the logical page numbers 0 to m, a valid bit that is a flag indicating whether the logical page number stored in the entry is valid, and an identifier that indicates the program currently being executed. The number of entries required for the final stage table is the same as the number of pages of the physical address space 4 to be inversely converted.

On the other hand, each entry 0 to n of the preceding table
As shown in FIG. 11, consists of a logical address of the reverse address translation table of the next stage, that is, a pointer to the reverse address translation table of the next stage, and a final stage flag composed of 2 bits. Here, when the value of the final stage flag is "11", it indicates that the reverse address translation table of the next stage is the final stage, and when the value of the final stage flag is "01", the table of the next stage is the final stage. If the value of the final stage flag is "00", it indicates that the entry of this reverse address translation table is invalid. It should be noted that the number of entries required for the preceding table is arbitrary depending on the computer system.

Here, the number of stages of the reverse address conversion table is preferably about two stages, because if the number of stages of the table is increased, it takes time to reverse the address. And in the case of a reverse address translation table composed of two stages,
The boundary of the start address and area size of the non-contiguous physical address space is determined by the number of divisions of the entry of the reverse address translation table in the first stage. For example, as shown in FIG. 12, the reverse address translation table 11 of the first stage is set to 10
When divided into 24, the boundary of the start address and area size is 4 MB.

In the above configuration, as shown in FIG. 12, when the physical address of the non-contiguous physical address space 10 is converted into the logical address, the physical address of FIG. 13 is referred to. Here, in FIG. 12, the physical address space 10 is 16 MB from the address 00000000H, and
If there is 4 MB from address 0000H, the reverse address translation table has a two-stage structure, and physical address space 10
8000000 from address 00000000H, 1000000
An example of converting a physical address of 4 MB from address 0H into a logical address will be shown. The contents of the physical address are shown in FIG.
As shown in, the physical page numbers 0 to n and the offsets are provided. The physical page numbers 0 to n are the indexes of the reverse address translation table 11 of the first stage and the reverse address translation tables 12a and 12b of the final stage having a 10-bit configuration. , 12c indexes. And the physical page number 1
By referring to the index of the reverse address conversion table 11 of the second stage, the reverse address conversion table 1 of the final stage
2a, 12b, 12c is selected, and the reverse address conversion tables 12a, 12b, 12 at the final stage selected are selected.
In c, the logical page number corresponding to the logical page of the logical address space 13 can be obtained by referring to the index of the reverse address translation table 12a, 12b, 12c at the final stage of the physical page number. The logical address can be easily obtained from the offset of the logical page number and the physical address.

Next, the operation of the address translator according to the third embodiment of the present invention will be described. In the page fault process, first, as shown in step S41 of FIG. 14, a logical page number is acquired from the contents of the logical address that caused the page fault.

Next, as shown in step S42, the entry corresponding to the logical page number is acquired by referring to the address conversion table. Next, step S4
As shown in 3, a free physical page in the physical address space is acquired.

Next, as shown in step S44, the physical page number of the physical page acquired in step S43 is set in the entry of the address translation table corresponding to the logical page number that caused the page fault.

Next, as shown in step S45, the valid bit contained in the control information of the entry of the address conversion table in which the physical page number is set is set to "1". Next, as shown in step S46, the physical page number of the physical page acquired in step S43 is set to, for example, FIG.
As shown in (4), it is divided into two so that 10 bits are provided. Next, as shown in step S47, the index of the reverse address conversion table 11 in the first stage of FIG. 12 is acquired. Here, the reverse address conversion table 1 of the first stage
As shown in FIG. 12, No. 1 is already created when the computer system starts up.

Next, as shown in step S48, the final stage flag of the entry of the reverse address translation table 11 of the first stage is acquired. Next, as shown in step S49,
The value of the final stage flag acquired in step S48 is "11".
Is determined. Then, the value of the final stage flag is "11", that is, the reverse address translation table of the next stage is the reverse address translation tables 12a, 12b, 1 of the final stage.
If it is 2c, the process proceeds to step S50, and if the value of the final stage flag is not "11", the process is ended.

Next, as shown in step S50, as shown in FIG.
The index of the reverse address conversion table 12 at the final stage of 2 is acquired. Next, as shown in step S51, the entry of the reverse address translation table 12 at the final stage is acquired.

Next, as shown in step S52, the logical page number of the content of the logical address that caused the page fault is set in the entry of the reverse address translation table 12 at the final stage.

Next, as shown in step S53, the valid bit of the entry of the reverse address translation table 12 at the final stage is set to "1". When the multiple virtual storage system is used, a process of setting the identifier of the program currently being executed in the entry of the reverse address translation table 12 is additionally performed.

Next, an address conversion process from a physical address to a logical address will be described. First, as shown in step S61 of FIG. 15, a physical page number is acquired from the contents of the physical address in the physical address space.

Next, as shown in step S62, the physical page number of the physical page acquired in step S61 is set to
Divide into 10 bits. Next, as shown in step S63, the index of the first-stage reverse address translation table 11 is acquired from the physical page number acquired in step S61.

Next, as shown in step S64, the final stage flag of the entry of the reverse address translation table 11 of the first stage is acquired. Next, as shown in step S65,
The value of the final stage flag acquired in step S64 is "1".
1 ", that is, if the next-stage reverse address translation table is the last-stage reverse address translation table 12a, 12b, 12c, the process proceeds to step S66, and if the last-stage flag value is not" 11 ", the process ends. .

Next, as shown in step S66, the index of the reverse address translation table 12 at the final stage is acquired from the physical page number acquired in step S61. Next, as shown in step S67, the entry of the final stage reverse address translation table 12 is acquired.

Next, as shown in step S68, when the valid bit of the entry acquired in step S67 is "1", the process proceeds to step S69, and the valid bit is "0".
If so, the process ends.

Next, as shown in step S69, the logical page number of the entry of the reverse address translation table 12 at the final stage is acquired. Next, as shown in step S70, a logical address is obtained from the logical page number acquired in step S69 and the offset of the physical address.

When the multiple virtual memory system is used, the process of specifying one logical address space by additionally acquiring the identifier of the program currently being executed from the entry of the reverse address translation table 12 is additionally performed. Be seen.

Further, in the above-described embodiment, the case where the physical address space 4 of FIG. 1 is provided in the main memory device 1 has been described, but also when the physical address space 4 is provided in a device other than the main memory device 1. The present invention is applicable. For example, in a computer system having a main storage device and a special register group, even if the final address of the main storage device and the start address of the special register group are widely separated and an unimplemented physical address space exists in the middle. The area of the reverse address translation table can be suppressed to the minimum necessary size.

[0078]

As described above, according to the first aspect of the invention, by providing the reverse address conversion table for converting the physical address into the logical address, the conversion from the physical address to the logical address can be easily performed. it can.

According to the second aspect of the invention, the logical page number of the logical address corresponding to the physical address is stored in each entry of the reverse address translation table, so that the reverse address translation table can be searched once. The logical page number can be obtained, and the physical address can be easily converted to the logical address.

According to the third aspect of the present invention, the identifier of the program using the logical address is stored in each entry of the reverse address translation table, so that the same logical address is assigned to each program. , A specific program can be easily accessed, and the efficiency in debugging the program can be improved.

Further, according to the invention of claim 4, it is possible to omit the process of calculating the logical address from the invalid logical page number by referring to the flag information, and to perform the conversion process from the physical address to the logical address. Can be speeded up.

According to the fifth aspect of the present invention, the reverse address conversion table is provided so as to correspond to the discontinuous physical address spaces, so that when the physical addresses of all the physical address spaces are not converted into the logical addresses, the reverse addresses are reversed. The area required to store the address conversion table can be reduced.

According to the sixth aspect of the invention, the physical address can be easily converted into the logical address by referring to the reverse address conversion table for converting the physical address into the logical address.

Further, according to the invention of claim 7, the conversion from the physical address to the logical address is carried out by dividing the physical address space into stages. Therefore, the reverse address is made to correspond to the discontinuous physical address space. A translation table can be provided and the area required to store the reverse address translation table can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an address translation device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a field configuration of a reverse address translation table according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram showing an address conversion method according to a first embodiment of the present invention.

FIG. 4 is a conceptual diagram showing a flow of address conversion according to the first embodiment of the present invention.

FIG. 5 is a diagram showing the number of entries in a reverse address translation table according to the first embodiment of the present invention.

FIG. 6 is a flowchart showing an operation when setting information in the address conversion table according to the first embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of the address translation device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a field configuration of a reverse address translation table according to a second embodiment of the present invention.

FIG. 9 is a flow chart showing an operation when setting information in the address conversion table according to the second embodiment of the present invention.

FIG. 10 is a flowchart showing the operation of the address translation device according to the second embodiment of the present invention.

FIG. 11 is a diagram showing a field configuration of a reverse address translation table other than the final stage according to the third embodiment of the present invention.

FIG. 12 is a conceptual diagram showing an address conversion method according to a third embodiment of the present invention.

FIG. 13 is a diagram showing a field structure of a physical address according to a third embodiment of the present invention.

FIG. 14 is a flow chart showing an operation when setting information in the address conversion table according to the third embodiment of the present invention.

FIG. 15 is a flowchart showing the operation of the address translation device according to the third embodiment of the present invention.

FIG. 16 is a conceptual diagram showing an address conversion method in a conventional single virtual memory system.

FIG. 17 is a conceptual diagram showing an address conversion method in a conventional multiple virtual storage system.

FIG. 18 is a diagram showing the concept of a page in a conventional logical address space or physical address space.

FIG. 19 is a diagram showing a field configuration of a conventional address translation table.

FIG. 20 is a flowchart showing the operation of a conventional address translation device.

FIG. 21 is a conceptual diagram showing a conventional address conversion method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 main storage device 2 address translation device 3 processing device 4, 7, 10 physical address space 5a, 8 reverse address translation table 5b address translation table 6, 9, 13 logical address space 11 1st stage reverse address translation table 12a, 12b, 12c Last stage reverse address conversion table

Claims (7)

[Claims] 1. An address translator according to the virtual memory system, comprising an inverse address translation table for translating a physical address (real address) into a logical address (virtual address). 2. The reverse address translation table comprises an entry corresponding to each physical page of a physical address space,
The address translation device according to claim 1, wherein a logical page number of a logical address corresponding to the physical address is stored in each of the entries. 3. The reverse address translation table comprises an entry corresponding to each physical page of a physical address space,
The address translation device according to claim 1, wherein a logical page number of a logical address corresponding to the physical address and an identifier of a program using the logical address are stored in the entry. 4. The address translation device according to claim 2, wherein the entry has flag information indicating whether or not the stored logical page number is valid. 5. The address translation device according to claim 1, wherein the reverse address translation table is provided with an entry corresponding to each physical page of a physical address space divided into a plurality of stages for each step. 6. An address conversion method according to the virtual memory system, wherein a physical address is converted into a logical address by referring to a reverse address conversion table for converting a physical address into a logical address. 7. An address translation method using a virtual memory system, wherein a physical address space is divided into a plurality of stages, and an entry provided for each stage corresponding to each physical page of the physical address space is referred to. , An address conversion method characterized by converting a physical address into a logical address.