CN116932428A - Method for transparent transmission data of memory management unit and memory management unit - Google Patents

Abstract

The present disclosure relates to a method for transparent data transfer of a memory management unit and a memory management unit. The method comprises the following steps: obtaining a virtual address input into a memory management unit; judging whether the virtual address is in a transparent address space or not, wherein the transparent address space is determined by taking a single address space as granularity; and if the virtual address is in the passthrough address space, passthrough the virtual address. In the technical scheme provided by the disclosure, the transparent transmission address space is determined by taking a single address space as granularity, and the transparent transmission granularity is small and the flexibility is high.

Description

Method for transparent transmission data of memory management unit and memory management unit

Technical Field

The present disclosure relates generally to the field of computer technology, and in particular, to a method for transparent (Bypass) data for a memory management unit (Memory Management Unit, MMU) and a memory management unit.

Background

In a System On Chip (SOC), a memory management unit is used to convert a virtual address into a physical address. Traditional technical solutions for transparent data of a memory management unit include Global transparent (Global Bypass), transparent (Context Based Bypass) based on processes, and transparent (Virtual Function Based Bypass) based on virtual users. Global transparent refers to that the memory management unit does not perform virtual address to physical address conversion; the transparent transmission based on the process refers to that the memory management unit only does not convert virtual addresses into physical addresses for some processes, but still converts virtual addresses into physical addresses for other processes; the transparent transmission based on the virtual users refers to that the memory management unit does not perform virtual address to physical address conversion only for some virtual users, but still performs virtual address to physical address conversion for other virtual users.

As can be seen, the conventional transparent granularity of the technical scheme for transparent data of the memory management unit is global, process or virtual user. However, in a practical application scenario, such a large pass-through granularity may not be required.

In summary, the conventional technical solution for transparent data transmission of the memory management unit has the following disadvantages: the transparent transmission granularity is large and the flexibility is poor.

Disclosure of Invention

In view of the above problems, the present disclosure provides a method for transparent data of a memory management unit and a memory management unit, where in the provided technical solution, a transparent address space is determined by using a single address space as granularity, and the transparent data has small granularity and high flexibility.

According to a first aspect of the present disclosure, there is provided a method for transparent data transmission of a memory management unit, the method comprising: obtaining a virtual address input into a memory management unit; judging whether the virtual address is in a transparent address space or not, wherein the transparent address space is determined by taking a single address space as granularity; and if the virtual address is in the passthrough address space, passthrough the virtual address.

In some embodiments, the transparent address space is one of the non-trivial subspaces comprised by a first virtual address space comprising at least one transparent address space, the first virtual address space being a partially transparent address space; alternatively, the transparent address space is a second virtual address space, and the second virtual address space is a completely transparent address space.

In some embodiments, the first virtual address space comprises: a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process.

In some embodiments, the second virtual address space comprises: a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process.

In some embodiments, the non-trivial subspace comprises an address segment comprising a first address segment, the first address segment being a segment of continuous addresses, or the first address segment being a single discrete address.

In some embodiments, the method further comprises: the transparent address space is determined based on pre-configured transparent configuration data, and the transparent configuration data comprises a valid mark, an address segment base address, an address segment length and a transparent form for each address segment in the transparent address space.

In some embodiments, the method further comprises: if the virtual address is not in the transparent address space, the virtual address is translated to a physical address.

In some embodiments, the method further comprises: modifying the virtual address based on a pre-configured virtual address modification instruction in response to the transparent virtual address; and outputting the modified address data.

In some embodiments, modifying the virtual address includes: and directly modifying the virtual address according to a preset rule.

In some embodiments, the method further comprises: acquiring attribute information corresponding to a virtual address input into a memory management unit; modifying the attribute information based on a pre-configured attribute information modification instruction in response to the transparent virtual address; and outputting the modified attribute information.

In some embodiments, the attribute information includes information related to security of the virtual address and information related to verification of the virtual address.

According to a second aspect of the present disclosure, there is also provided a memory management unit including a translation cache unit configured to: obtaining a virtual address input into a memory management unit; judging whether the virtual address is in a transparent address space or not, wherein the transparent address space is determined by taking a single address space as granularity; and if the virtual address is in the passthrough address space, passthrough the virtual address.

The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to the provided drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 illustrates a schematic diagram of a memory management unit according to an embodiment of the present disclosure.

Fig. 2 illustrates a flowchart of a method for transparent data transfer of a memory management unit according to an embodiment of the present disclosure.

Fig. 3 illustrates an exemplary transparent address space in accordance with an embodiment of the present disclosure.

Fig. 4 illustrates exemplary pass-through configuration data according to an embodiment of the present disclosure.

Fig. 5 illustrates a flowchart of a method for transparent data transfer of a memory management unit according to an embodiment of the present disclosure.

Fig. 6 illustrates a flowchart of a method for transparent data transfer of a memory management unit according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments, and they should not be construed as limiting the scope of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

As described above, in the conventional technical solution for transparent transmission data of a memory management unit, the transparent transmission granularity is large and the flexibility is poor.

To at least partially address one or more of the above problems, as well as other potential problems, the present disclosure proposes a method for transparent data transfer for a memory management unit and a memory management unit. In the technical scheme of the disclosure, the transparent transmission address space is determined by taking a single address space as granularity, and the transparent transmission granularity is small and the flexibility is high.

Further, in embodiments of the present disclosure, by determining the transparent address space based on pre-configured transparent configuration data, at least the design is simple and easy to implement.

Further, in the embodiment of the disclosure, the transparent configuration data includes, for each address segment in the transparent address space, an effective flag, an address segment base address, an address segment length, and a transparent form, and at least the transparent configuration data can be set for a plurality of address segments included in the transparent address space, so that flexibility of setting the transparent address space is further improved.

Further, in embodiments of the present disclosure, by modifying a virtual address based on a pre-configured virtual address modification indication in response to a pass-through virtual address, at least the modification of the virtual address may be pre-configured and efficient because the modification is not based on translating a page table.

Still further, in embodiments of the present disclosure, by modifying attribute information corresponding to a virtual address based on a pre-configured attribute information modification indication in response to a pass-through virtual address, at least the modification of the attribute information may be pre-configured, facilitating software programming, and efficient because the modification is not based on a translation page table.

The present disclosure is illustrated by the following several specific examples. Detailed descriptions of known functions and known components may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any element of an embodiment of the present disclosure appears in more than one drawing, the element is identified by the same reference numeral in each drawing.

Fig. 1 illustrates a schematic diagram of a memory management unit 100 according to an embodiment of the present disclosure. As shown in fig. 1, the memory management unit 100 includes a translation cache unit (Translation Buffer Unit, TBU) 120. It should be appreciated that memory management unit 100 may also include additional components not shown, the scope of the present disclosure is not limited in this respect.

Regarding the memory management unit 100, it may be configured to translate virtual addresses input to the memory management unit 100 into physical addresses, pass through virtual addresses, and modify virtual addresses. In addition, the memory management unit 100 may be further configured to modify attribute information corresponding to the virtual address input to the memory management unit 100.

It should be noted that the memory management unit 100 covers a system memory management unit (System Memory Management Unit, SMMU), an Input-output memory management unit (Input-Output Memory Management Unit, IOMMU), and other units having similar functions, and the embodiments of the present disclosure are not limited thereto.

It should be further noted that the memory management unit 100 may further include other components, which are not limited in this embodiment of the present disclosure. For example, the memory management unit 100 may further include a translation control unit (Translation Control Unit, TCU), which may communicate with the translation cache unit 120.

Regarding the translation cache unit 120, it may cache data required by the memory management unit 100 when it is operating. For example, a memory unit (not shown) in the translation cache unit 120 may be configured by software to store transparent configuration data, a virtual address modification indication, and an attribute information modification indication, and may also load a translation page table from a memory unit (not shown) external to the translation cache unit 120.

For example, the conversion cache unit 120 may be configured to: obtaining a virtual address input into a memory management unit; judging whether the virtual address is in a transparent address space or not, wherein the transparent address space is determined by taking a single address space as granularity; and if the virtual address is in the passthrough address space, passthrough the virtual address.

For example, the translation cache unit 120 may be further configured to: a transparent address space is determined based on the pre-configured transparent configuration data.

For example, the translation cache unit 120 may be further configured to: if the virtual address is not in the transparent address space, the virtual address is translated to a physical address.

For example, the translation cache unit 120 may be further configured to: in response to the pass-through virtual address, the virtual address is modified based on a pre-configured virtual address modification indication.

For example, the translation cache unit 120 may be further configured to: acquiring attribute information corresponding to a virtual address input into a memory management unit; in response to the pass-through virtual address, the attribute information is modified based on the pre-configured attribute information modification indication.

It should be noted that, in the embodiment of the present disclosure, the memory management unit 100 may perform at least some steps in the methods described below in connection with fig. 2, 5 and 6 to pass through data.

Fig. 2 illustrates a flowchart of a method 200 for transparent data transfer of a memory management unit according to an embodiment of the present disclosure. For example, the method may be performed by the memory management unit 100 described in connection with fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or that the blocks shown may be omitted, the scope of the disclosure being not limited in this respect.

In step 202, the translation cache unit 120 obtains the virtual address input to the memory management unit 100.

As regards the virtual address, it may come from, for example, a Master device (Master) corresponding to the translation cache unit 120. In the embodiment of the present disclosure, a master device refers to a device that transmits an address translation request to the memory management unit 100. For example, the master may be an IP core, a third level Cache (Cache) within an x86 architecture central processing unit (Central Processing Unit, CPU) or a system level Cache (System Level Cache, SLC) within a CPU of the handset, etc., as embodiments of the disclosure are not limited in this respect.

In step 204, the translation cache unit 120 determines whether the virtual address is in a transparent address space, which is determined with a single address space as granularity.

Regarding the transparent address space, it refers to an address space where the memory management unit 100 transparent data. It should be noted that, in the embodiment of the present disclosure, transparent refers to that data input to the memory management unit 100 is not converted via the conversion page table.

For example, in an embodiment of the present disclosure, the passthrough address space may be one of the non-trivial subspaces included in a first virtual address space that includes at least one passthrough address space, the first virtual address space being a partially passthrough address space. It should be noted that, in the embodiment of the present disclosure, the partial transparent transmission refers to that a part of, but not all of, the address space corresponding to the global transparent transmission, the transparent transmission based on the process, or the transparent transmission based on the virtual user is transparent. For example, the first virtual address space includes: a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process. It should also be noted that a non-trivial subspace of a space refers to a subspace of the space that is not itself, non-zero. In addition, in embodiments of the present disclosure, a "target" prior to a virtual user and process is used to illustrate that no virtual address to physical address translation is performed for that virtual user or for that process.

For example, in embodiments of the present disclosure, the transparent address space may be a second virtual address space, which is a fully transparent address space. In the embodiments of the present disclosure, the full transparent refers to transparent in all address spaces corresponding to global transparent, process-based transparent, or virtual user-based transparent. For example, the second virtual address space includes: a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process. It is noted that in embodiments of the present disclosure, while the second virtual address space may include a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process, it is determined at a single address space granularity, rather than at a global, process, or virtual user granularity.

For example, the non-trivial subspace may comprise an address segment comprising a first address segment, the first address segment being a segment of continuous addresses, or the first address segment being a single discrete address. It should be noted that the first address segment may refer to any one of the address segments included in the non-trivial subspace. It should also be noted that the number of address segments included in the non-trivial subspace may depend on the actual situation, as embodiments of the present disclosure do not limit this.

For example, the transparent address space and the address segments included therein may refer to the embodiment described later in conjunction with fig. 3, and will not be described herein.

Regarding the transparent address space being determined at a single address space granularity, for example, the translation buffer unit 120 may determine the transparent address space based on the transparent configuration data configured in advance for defining the transparent address space at a single address space granularity. For example, the transparent configuration data may be stored in the conversion cache unit 120 via software configuration at an initialization stage of the memory management unit 100. It should be noted that in embodiments of the present disclosure, a single address space may be a segment of continuous addresses or a single discrete address, such as the first address segment described above.

It should be noted that, in the embodiment of the present disclosure, a specific format of the transparent configuration data is not limited. For example, the transparent configuration data may refer to the embodiment described in connection with fig. 4, which will not be described herein.

In step 206, if the virtual address is in the transparent address space, the translation cache unit 120 transparent the virtual address.

With respect to pass-through virtual addresses, it refers to translating virtual addresses without a page table. For example, in the case of a transparent virtual address, address data output from the memory management unit 100 to a host device corresponding to the translation cache unit 120 may be identical to the virtual address input from the host device to the memory management unit 100.

In step 208, if the virtual address is not in the transparent address space, the translation cache unit 120 translates the virtual address to a physical address.

Regarding the conversion of the virtual address into the physical address, it includes, for example, the conversion cache unit 120 referring to the conversion page table, and converting the virtual address based on the conversion page table to obtain the corresponding physical address. For example, in the case of converting a virtual address into a physical address, the data output from the memory management unit 100 to the host device corresponding to the translation cache unit 120 is the physical address obtained by translation based on the translation page table. In embodiments of the present disclosure, a translation page table may be used to indicate the correspondence of virtual addresses and physical addresses. For example, the translation page table may be loaded into translation cache unit 120 from a storage unit (not shown) external to translation cache unit 120.

In the embodiment of the disclosure, the transparent address space is determined by taking a single address space as granularity, and the transparent address space has small granularity and high flexibility.

In addition, in the embodiments of the present disclosure, by determining the transparent address space based on the transparent configuration data configured in advance, at least the design is simple and easy to implement.

Fig. 3 illustrates an exemplary transparent address space in accordance with an embodiment of the present disclosure. In fig. 3, 3 example cases 310, 320, and 330 are shown, where the cross-line grid region represents a passthrough address space, the shaded region represents an address space where virtual addresses need to be translated to physical addresses based on a translation page table, and the address space range may optionally represent any of a global virtual address space, a virtual address space corresponding to a target virtual user, a virtual address space corresponding to a target process.

As shown in fig. 3, in an example case 310, the transparent address space includes only 1 address segment, and the address segment is a segment of consecutive addresses; in the example case 320, the transparent address space includes 6 address segments, and each of the 6 address segments is a segment of contiguous addresses; in the example case 330, the transparent address space includes 3 address segments, and each of the 3 address segments is a single discrete address.

It should be noted that the address segments included in the transparent address space in the example cases 310, 320, and 330 shown in fig. 3 are all a segment of continuous addresses or are all single discrete addresses, which are merely exemplary and not limiting of the present disclosure. For example, in one example, the transparent address space may include at least a second address segment that is a segment of continuous addresses and a third address segment that is a single discrete address, where the "second" and "third" are merely to distinguish between two address segments, which may be virtually any two different address segments included in the transparent address space.

Fig. 4 illustrates exemplary pass-through configuration data according to an embodiment of the present disclosure. In the embodiment shown in fig. 4, the transparent configuration data includes a valid flag, an address segment base address, an address segment length, a transparent form for each address segment in the transparent address space.

And a valid flag for indicating whether the address field is transparent. For example, the valid flag may be 1-bit binary data, and indicates that the address field is transparent in the case that the valid flag is a value of "1".

With respect to the address segment base address, it is used to indicate the starting address of the address segment.

Regarding the address segment length, it is used to indicate the length of the address included in the address segment.

For example, in embodiments of the present disclosure, the corresponding address segments may be determined at a single address space granularity based on the address segment base address and the address segment length. For example, in the case where the address segment length is 1, the address segment is a single discrete address. For example, in the case where the address segment length is 3, the address segment is a segment of consecutive addresses including 3 consecutive addresses starting from the start address indicated by the address segment base address.

Regarding the transparent transmission form, it is used to indicate the form of transparent transmission of data in the determined address segment. For example, the pass-through form may be a global form, a virtual user-based form, and a process-based form.

For example, in one example, the transparent address space may include at least a fourth address segment and a fifth address segment. For the fourth address segment, the length of the address segment corresponding to the fourth address segment is greater than 1, the valid flag indicates that transparent transmission is performed, and the transparent transmission form is a process-based form, a segment of continuous address corresponding to the fourth address segment can be determined based on the base address of the address segment and the length of the address segment, and for the segment of continuous address, the virtual address is only converted by the target process without the conversion page table, and for other processes except the target process, the virtual address is still converted by the conversion page table. For the fifth address segment, the length of the address segment corresponding to the fifth address segment is 1, the valid flag indicates that transparent transmission is performed, and the transparent transmission form is based on the virtual user, then a single discrete address corresponding to the fifth address segment can be determined based on the base address of the address segment and the length of the address segment, and for the single discrete address, the virtual address is only converted by the target virtual user without the conversion page table, and for other virtual users except the target virtual user, the virtual address is still converted by the conversion page table.

It should be noted that, in the embodiment of the present disclosure, in the case where the transparent address space includes a plurality of address segments, setting may be performed for the plurality of address segments included in the transparent address space, respectively. For example, the transparent address space includes n address segments, where n is a positive integer, and the transparent configuration data includes n groups of valid flags, address segment base addresses, address segment lengths, and transparent forms, where each group of valid flags, address segment base addresses, address segment lengths, and transparent forms corresponds to 1 address segment.

It should be further noted that the valid flag, the address segment base address, the address segment length, the specific data format and the relative order of the transparent transmission form in the transparent transmission configuration data described in fig. 4 may depend on the actual situation, and the embodiment of the present disclosure is not limited thereto.

In addition, in embodiments of the present disclosure, the transparent configuration data including a valid flag, an address segment base address, an address segment length, a transparent form for each address segment in the transparent address space is also merely exemplary and not limiting of the present disclosure. For example, the transparent configuration data may include a valid flag, an address segment base address, a base address post address length, a transparent form for each address segment in the transparent address space, which differs from the embodiment described in connection with fig. 4 in that the base address post address length is used to indicate the length of the address post the base address included in the address segment. For example, in the case where the address length is 0 after the base address, the address segment is a single discrete address. For example, in the case where the address segment length is 3, the address segment is a segment of consecutive addresses including 4 consecutive addresses starting from the start address indicated by the address segment base address.

In the embodiment of the disclosure, by means of the transparent configuration data, for each address segment in the transparent address space, the valid flag, the address segment base address, the address segment length and the transparent form are included, at least the plurality of address segments included in the transparent address space can be set respectively, so that the flexibility of setting the transparent address space is further improved. For example, as described above, the pass-through address space may include a fourth address field based on a form of a process and a fifth address field based on a form of a virtual user, thereby mixedly using different pass-through forms.

Fig. 5 illustrates a flowchart of a method 500 for transparent data transfer of a memory management unit according to an embodiment of the present disclosure. For example, the method may be performed by the memory management unit 100 described in connection with fig. 1. It should be understood that method 500 may also include additional blocks not shown and/or that the blocks shown may be omitted, the scope of the disclosure being not limited in this respect.

In step 502, the translation cache unit 120 modifies the virtual address based on the pre-configured virtual address modification indication in response to the transparent virtual address.

With respect to modifying virtual addresses, it is done based on a pre-configured virtual address modification indication and not based on translating page tables. In embodiments of the present disclosure, the virtual address modification indication may indicate a modification to the virtual address. For example, the virtual address modification instruction may be stored in the translation cache unit 120 via software configuration at an initialization stage of the memory management unit 100. It should be noted that, the data format of the virtual address modification indication and the indicated modification content may depend on the actual situation, and the embodiment of the present disclosure is not limited thereto.

For example, in one example, modifying the virtual address includes directly modifying the virtual address according to a preset rule. For example, the virtual address is added to a first predetermined value, or the virtual address is multiplied by a second predetermined value. It should be noted that the first predetermined value and the second predetermined value may depend on the actual situation, and the embodiment of the present disclosure is not limited thereto. It should also be noted that the specific implementation of adding the first predetermined value to the virtual address or multiplying the virtual address by the second predetermined value may depend on the actual situation, and embodiments of the present disclosure are not limited thereto. For example, a shift operation may be performed on the binary virtual address to achieve multiplication of the binary virtual address by an integer power of 2.

In step 504, the memory management unit 100 outputs the modified address data.

For example, the data output from the memory management unit 100 to the host device corresponding to the translation cache unit 120 is modified address data.

In embodiments of the present disclosure, by modifying a virtual address based on a pre-configured virtual address modification indication in response to a pass-through virtual address, at least the modification of the virtual address may be pre-configured and efficient because the modification is not based on translating a page table.

It should be noted that, in the embodiment of the present disclosure, not only the transparent virtual address but also the attribute information corresponding to the transparent virtual address may be modified.

For example, in an embodiment of the present disclosure, the method for transparent data of a memory management unit further includes: acquiring attribute information corresponding to a virtual address input into a memory management unit; modifying the attribute information based on a pre-configured attribute information modification instruction in response to the transparent virtual address; and outputting the modified attribute information. For example, refer to the embodiment described below in connection with fig. 6.

Fig. 6 illustrates a flowchart of a method 600 for transparent data transfer of a memory management unit according to an embodiment of the present disclosure. For example, the method may be performed by the memory management unit 100 described in connection with fig. 1. It should be understood that method 600 may also include additional blocks not shown and/or that the blocks shown may be omitted, the scope of the disclosure being not limited in this respect.

In step 602, the translation cache unit 120 obtains the virtual address input to the memory management unit 100 and attribute information corresponding to the virtual address.

As for the attribute information, which indicates the attribute of the corresponding virtual address, for example, information about security of the virtual address and information about verification of the virtual address may be included. For example, the information related to security of the virtual address includes AxPROT information, and the information related to verification of the virtual address includes AxCACHE information.

For example, the virtual address and attribute information corresponding to the virtual address may be from a master device corresponding to the translation cache unit 120.

In step 604, the translation cache unit 120 determines whether the virtual address is in a transparent address space, which is determined with a single address space as granularity. If the virtual address is in the transparent address space, proceed to step 606; if the virtual address is not in the transparent address space, then step 608 continues.

For example, the implementation of step 604 may refer to the relevant description of step 204 in fig. 2, and will not be described herein.

In step 606, the translation cache unit 120 transparently passes virtual addresses.

For example, the implementation of step 606 may refer to the relevant description of step 206 of fig. 2, and will not be described herein.

In step 608, the translation cache unit 120 translates the virtual address to a physical address.

For example, the implementation of step 608 may refer to the relevant description of step 208 in fig. 2, and will not be described herein.

In step 610, the conversion cache unit 120 modifies the attribute information based on the attribute information modification instruction configured in advance.

With respect to modifying attribute information, it is done based on a preconfigured attribute information modification instruction, and not based on translating a page table. In embodiments of the present disclosure, the attribute information modification indication may indicate a modification to the attribute information. For example, the attribute information modification instruction may be stored in the conversion cache unit 120 via software configuration at the initialization stage of the memory management unit 100. It should be noted that, the data format indicated by the modification of the attribute information and the indicated modification content may depend on the actual situation, and the embodiment of the present disclosure is not limited thereto.

In step 612, the memory management unit 100 outputs the modified attribute information.

For example, the data output from the memory management unit 100 to the host device corresponding to the translation cache unit 120 is modified attribute information.

In embodiments of the present disclosure, by modifying attribute information corresponding to a virtual address based on a pre-configured attribute information modification indication in response to a pass-through virtual address, at least the modification of the attribute information may be pre-configured, facilitating software programming, and efficient because the modification is not based on a translation page table.

In addition, in an embodiment of the present disclosure, the method for transparent data transmission of a memory management unit may further include: in response to converting the virtual address into the physical address, the conversion cache unit 120 may convert attribute information corresponding to the virtual address into converted attribute information based on the conversion page table; and the memory management unit 100 outputs the converted attribute information. In this case, the translation page table may also be used to indicate correspondence between attribute information corresponding to virtual addresses that are not transparent and the translated attribute information.

Note that, in the case of converting a virtual address into a physical address, attribute information corresponding to the virtual address may also be modified based on a pre-configured attribute information modification instruction, which is not limited in the embodiments of the present disclosure. For example, in an embodiment of the present disclosure, the method for transparent data of a memory management unit may further include: in response to converting the virtual address into the physical address, the conversion buffer unit 120 may modify attribute information corresponding to the virtual address based on a pre-configured attribute information modification instruction; and the memory management unit 100 outputs the modified attribute information.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (12)

1. A method for transparent data transfer of a memory management unit, the method comprising:

obtaining a virtual address input into the memory management unit;

judging whether the virtual address is in a transparent address space or not, wherein the transparent address space is determined by taking a single address space as granularity; and

and if the virtual address is in the transparent address space, transparent transmitting the virtual address.

2. The method of claim 1, wherein the transparent address space is one of non-trivial subspaces included in a first virtual address space, the first virtual address space including at least one of the transparent address spaces, the first virtual address space being a partially transparent address space;

or, the transparent address space is a second virtual address space, and the second virtual address space is a completely transparent address space.

3. The method of claim 2, wherein the first virtual address space comprises: a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process.

4. The method of claim 2, wherein the second virtual address space comprises: a global virtual address space, a virtual address space corresponding to a target virtual user, and a virtual address space corresponding to a target process.

5. A method according to claim 3, wherein the non-trivial subspace comprises an address field comprising a first address field, which is a continuous address field, or a single discrete address.

6. The method according to claim 1, wherein the method further comprises:

the transparent address space is determined based on pre-configured transparent configuration data comprising, for each address segment in the transparent address space, a valid flag, an address segment base address, an address segment length, a transparent form.

7. The method according to claim 1, wherein the method further comprises:

if the virtual address is not in the passthrough address space, the virtual address is translated to a physical address.

8. The method according to claim 1, wherein the method further comprises:

modifying the virtual address based on a pre-configured virtual address modification instruction in response to the transparent transmission of the virtual address; and

and outputting the modified address data.

9. The method of claim 8, wherein modifying the virtual address comprises: and directly modifying the virtual address according to a preset rule.

10. The method according to claim 1, wherein the method further comprises:

acquiring attribute information corresponding to the virtual address and input into the memory management unit;

modifying the attribute information based on a pre-configured attribute information modification instruction in response to the transparent transmission of the virtual address; and

and outputting the modified attribute information.

11. The method according to claim 10, wherein the attribute information includes information related to security of the virtual address and information related to verification of the virtual address.

12. A memory management unit, the memory management unit comprising a translation cache unit, wherein the translation cache unit is configured to:

obtaining a virtual address input into the memory management unit;

judging whether the virtual address is in a transparent address space or not, wherein the transparent address space is determined by taking a single address space as granularity; and

and if the virtual address is in the transparent address space, transparent transmitting the virtual address.