JPH051241U - Mount for semiconductor devices - Google Patents
Mount for semiconductor devicesInfo
- Publication number
- JPH051241U JPH051241U JP5563691U JP5563691U JPH051241U JP H051241 U JPH051241 U JP H051241U JP 5563691 U JP5563691 U JP 5563691U JP 5563691 U JP5563691 U JP 5563691U JP H051241 U JPH051241 U JP H051241U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- solder material
- die
- mount
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Abstract
(57)【要約】
【目的】 半田材を介して半導体素子をダイボンドする
半導体素子用マウントにおいて、放熱性の良い半導体装
置を歩留まり良く製造することを可能にする半導体素子
用マウントを提供する。
【構成】 半田材２を介して半導体素子３をダイボンド
する半導体素子用マウント５において、ダイボンド面に
前記半田材２を載置する凹部７を設け、該凹部７の容積
を半田材２の所望体積より小さくし、該凹部７の面形状
は半導体素子３のダイボンド面で完全に覆うことができ
るようにする。
(57) [Abstract] [PROBLEMS] To provide a semiconductor element mount in which a semiconductor element is die-bonded via a solder material, which makes it possible to manufacture a semiconductor device having good heat dissipation with a high yield. In a semiconductor element mount 5 in which a semiconductor element 3 is die-bonded via a solder material 2, a recess 7 for mounting the solder material 2 is provided on a die bonding surface, and the volume of the recess 7 is set to a desired volume of the solder material 2. It is made smaller so that the surface shape of the recess 7 can be completely covered by the die-bonding surface of the semiconductor element 3.
Description
【０００１】[0001]
本考案は、半導体素子のダイボンドに用いるマウントに関する。 The present invention relates to a mount used for die bonding of semiconductor devices.
【０００２】[0002]
従来、半導体素子をＡｕ−Ｓｎ、Ｐｂ−Ｓｎ系などの半田材を用いてマウント 上にダイボンドする場合、以下のようにして行われていた。即ち、図３（ａ）に 示すように、マウント１の平坦な電極６面上に、半田材２と半導体素子３をこの 順に重ねて載せる。８は半導体素子電極である。次いで、この状態で半田材２の 融点以上に加熱する。次いで、図３（ｂ）に示すように、半田材２が溶融した後 、ダイボンド用コレット４を用いてスクラブを行い、その後、冷却することによ り半導体素子３を固定していた。この際、半導体素子３側面への半田材２の回り 込みを防ぐため、半田材２の量を必要最小限にする必要があった。 Conventionally, when a semiconductor element is die-bonded onto a mount using a solder material such as Au-Sn or Pb-Sn, it has been performed as follows. That is, as shown in FIG. 3A, the solder material 2 and the semiconductor element 3 are placed in this order on the flat electrode 6 surface of the mount 1. Reference numeral 8 is a semiconductor element electrode. Next, in this state, the solder material 2 is heated to the melting point or higher. Next, as shown in FIG. 3B, after the solder material 2 was melted, scrubbing was performed using the die-bonding collet 4, and then the semiconductor element 3 was fixed by cooling. At this time, in order to prevent the solder material 2 from wrapping around the side surface of the semiconductor element 3, it is necessary to minimize the amount of the solder material 2.
【０００３】[0003]
上述のように、半導体素子とマウント間の半田材の量が充分でないため、半導 体素子の電極材とマウント電極材が半田材に溶け込むと、半田材の組成が大きく 変動する。その結果、半田材の凝固点が半導体素子面内および半導体素子間でば らつき、ダイボンド強度および熱抵抗値もばらつくという問題があった。 As described above, since the amount of the solder material between the semiconductor element and the mount is not sufficient, when the electrode material of the semiconductor element and the mount electrode material melt into the solder material, the composition of the solder material changes greatly. As a result, there is a problem in that the freezing point of the solder material varies in the plane of the semiconductor element and between the semiconductor elements, and the die bond strength and the thermal resistance value also vary.
【０００４】[0004]
本考案は上記問題点を解決した半導体素子用マウントを提供するもので、半田 材を介して半導体素子をダイボンドする半導体素子用マウントにおいて、ダイボ ンド面に前記半田材を載置する凹部を有し、該凹部の容積は使用する半田材の体 積より小さく、該凹部の面形状は半導体素子のダイボンド面で完全に覆うことが できることを特徴とするものである。 The present invention provides a semiconductor element mount that solves the above problems. In a semiconductor element mount in which a semiconductor element is die-bonded through a solder material, a recess is provided on the die bond surface for mounting the solder material. The volume of the recess is smaller than the volume of the solder material used, and the surface shape of the recess can be completely covered with the die-bonding surface of the semiconductor element.
【０００５】[0005]
【作用】 上述の半導体素子用マウントの凹部に、必要十分な量の半田材を載置し、その 上に、前記凹部を完全に覆うように半導体素子を重ねて半田材を溶融する。凹部 の容積は半田材の体積より小さいため、溶融した半田材は凹部からあふれ、凹部 の面形状を覆う半導体素子のダイボンド面に接触する。そこで、凹部の容積を適 切な大きさにし、あふれた半田材の量を調節すると、組成変動をふせぐ十分な量 の半田材を使用することができるとともに、あふれた半田材が半導体素子の側面 に回り込まないようにすることができる。A necessary and sufficient amount of solder material is placed in the recess of the semiconductor element mount described above, and the semiconductor element is stacked on the solder material so as to completely cover the recess, and the solder material is melted. Since the volume of the recess is smaller than the volume of the solder material, the molten solder material overflows from the recess and contacts the die-bonding surface of the semiconductor element that covers the surface shape of the recess. Therefore, by adjusting the volume of the recess to an appropriate size and adjusting the amount of solder material that has overflowed, it is possible to use a sufficient amount of solder material that prevents composition fluctuations, and the overflowed solder material can be applied to the side surface of the semiconductor element. You can avoid getting around.
【０００６】[0006]
以下、図面に示した実施例に基づいて本考案を詳細に説明する。 図１（ａ）は本考案にかかる半導体素子用マウントの一実施例の斜視図であり 、同図（ｂ）は同図（ａ）のＡ−Ａ断面図である。図中、５はマウント、６はマ ウント電極、７は凹部である。電極６は、バリア層をふくみ、表面がＡｕである 、Ｔｉ／Ｐｔ／Ａｕ、Ｍｏ／Ａｕなどで構成されている。凹部７のサイズは、縦 、横の長さは半導体素子の長さより小さく、容積は半田材の体積よりも１〜２割 小さくする。例えば、半導体素子のサイズ４００μ×４００μ、半田材３００μ ×３００μ×２０μの場合、凹部７の形状は３５０μ×３５０μ、深さ１２μと する。図２（ａ）〜（ｂ）に上記マウント５を用いて、半導体素子３をダイボン ドする工程を示す。先ず、マウント５上に半田材２を載せ、その上に半導体素子 ３を載せる（図２（ａ））。半導体素子３のダイボンド面には素子電極８が形成 されている。この状態で加熱すると、半田材２は溶融し、その体積が凹部７より も大きいため、半田材２は凹部７からあふれて、半導体素子３のダイボンド面全 面に広がる。 マウント５の製作は次のようにして行う。金属製の場合には、金型を用いて機 械加工により凹部７を形成し、次いで、メッキによりＮｉ／Ａｕ電極６を形成す る。また、Ｓｉなどの半導体で製作する場合には、レジストによるパターニング と、例えば、ＨＮＯ3 系溶液によるエッチングを組み合わせて、凹部７を形成し 、次いで、ＥＢ蒸着などによりＴｉ／Ｐｔ／Ａｕ電極６を形成する。Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. FIG. 1A is a perspective view of an embodiment of a semiconductor device mount according to the present invention, and FIG. 1B is a sectional view taken along the line AA of FIG. In the figure, 5 is a mount, 6 is a mount electrode, and 7 is a recess. The electrode 6 includes a barrier layer and has a surface of Au, and is made of Ti / Pt / Au, Mo / Au, or the like. The size of the concave portion 7 is such that the vertical and horizontal lengths are smaller than the semiconductor element length, and the volume is 10 to 20% smaller than the solder material volume. For example, when the size of the semiconductor element is 400 μ × 400 μ and the solder material is 300 μ × 300 μ × 20 μ, the shape of the recess 7 is 350 μ × 350 μ and the depth is 12 μ. 2A and 2B show a process of die-bonding the semiconductor element 3 using the mount 5. First, the solder material 2 is placed on the mount 5, and the semiconductor element 3 is placed thereon (FIG. 2A). A device electrode 8 is formed on the die-bonding surface of the semiconductor device 3. When heated in this state, the solder material 2 melts and its volume is larger than that of the concave portion 7. Therefore, the solder material 2 overflows from the concave portion 7 and spreads over the entire die bond surface of the semiconductor element 3. The mount 5 is manufactured as follows. In the case of metal, the concave portion 7 is formed by mechanical processing using a mold, and then the Ni / Au electrode 6 is formed by plating. In the case of manufacturing with a semiconductor such as Si, patterning with a resist and etching with, for example, an HNO 3 system solution are combined to form the recess 7, and then the Ti / Pt / Au electrode 6 is formed by EB evaporation or the like. Form.
【０００７】[0007]
以上説明したように本考案によれば、半田材を介して半導体素子をダイボンド する半導体素子用マウントにおいて、ダイボンド面に前記半田材を載置する凹部 を有し、該凹部の容積は半田材の所望体積より小さく、該凹部の面形状は半導体 素子のダイボンド面で完全に覆うことができるため、ダイボンド時に、半田材の 組成変動を小さくするだけの十分な量の半田材を使用し、かつ、半田材の半導体 素子側面への回り込みを防ぐことができる。従って、放熱特性の良い半導体装置 を歩留まり良く製造することができるという優れた効果がある。 As described above, according to the present invention, in a semiconductor element mount in which a semiconductor element is die-bonded via a solder material, the die-bonding surface has a recess for mounting the solder material, and the volume of the recess is equal to that of the solder material. Since the volume is smaller than the desired volume and the surface shape of the recess can be completely covered by the die-bonding surface of the semiconductor element, use a sufficient amount of solder material to reduce the composition variation of the solder material during die-bonding, and It is possible to prevent the solder material from wrapping around the side surface of the semiconductor element. Therefore, there is an excellent effect that a semiconductor device having excellent heat dissipation characteristics can be manufactured with high yield.
【図１】（ａ）、（ｂ）は本考案に係る半導体素子用マ
ウントの一実施例の斜視図およびＡ−Ａ断面図である。1A and 1B are a perspective view and an AA cross-sectional view of an embodiment of a mount for a semiconductor device according to the present invention.
【図２】（ａ）、（ｂ）は、前記実施例を用いたダイボ
ンドの工程説明図である。2A and 2B are process explanatory diagrams of die bonding using the above-described embodiment.
【図３】従来のダイボンドの工程説明図である。FIG. 3 is a diagram illustrating a conventional die bonding process.
１、５ マウント ２ 半田材 ３ 半導体素子 ４ コレット ６、８ 電極 ７ 凹部 1, 5 Mount 2 Solder material 3 Semiconductor element 4 Collet 6, 8 Electrode 7 Recess
Claims (1)
する半導体素子用マウントにおいて、ダイボンド面に前
記半田材を載置する凹部を有し、該凹部の容積は半田材
の所望体積より小さく、該凹部の面形状は半導体素子の
ダイボンド面で完全に覆うことができることを特徴とす
る半導体素子用マウント。Claims for utility model registration: 1. A semiconductor element mount for die-bonding a semiconductor element through a solder material, comprising a recess for mounting the solder material on a die-bonding surface, and the volume of the recess is solder. A mount for a semiconductor element, which is smaller than a desired volume of the material, and the surface shape of the recess can be completely covered by the die-bonding surface of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5563691U JPH051241U (en) | 1991-06-20 | 1991-06-20 | Mount for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5563691U JPH051241U (en) | 1991-06-20 | 1991-06-20 | Mount for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH051241U true JPH051241U (en) | 1993-01-08 |
Family
ID=13004291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5563691U Pending JPH051241U (en) | 1991-06-20 | 1991-06-20 | Mount for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH051241U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4995055U (en) * | 1972-12-04 | 1974-08-16 |
-
1991
- 1991-06-20 JP JP5563691U patent/JPH051241U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4995055U (en) * | 1972-12-04 | 1974-08-16 |
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