JP3454240B2 - Electronic device and method of manufacturing the same - Google Patents
Electronic device and method of manufacturing the sameInfo
- Publication number
- JP3454240B2 JP3454240B2 JP2000290402A JP2000290402A JP3454240B2 JP 3454240 B2 JP3454240 B2 JP 3454240B2 JP 2000290402 A JP2000290402 A JP 2000290402A JP 2000290402 A JP2000290402 A JP 2000290402A JP 3454240 B2 JP3454240 B2 JP 3454240B2
- Authority
- JP
- Japan
- Prior art keywords
- plate
- position regulating
- opening
- semiconductor element
- outer frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Landscapes
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パッケージ、なら
びに半導体装置およびその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package, a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】まず、従来のパッケージ、半導体装置お
よびその製造方法について図面を用いて説明する。2. Description of the Related Art First, a conventional package, semiconductor device and manufacturing method thereof will be described with reference to the drawings.
【０００３】図６は、従来のパッケージに半導体素子を
形成してなる従来の半導体装置の平面図を示し、図７
は、そのＡ−Ｂ断図を示す。図６および図７において、
銅からなる放熱板１上にセラミックなどの絶縁体で構成
される外枠２が形成されている。入力リード３および出
力リード４はそれぞれ外枠２の内外に貫通しており、放
熱板１とはそれぞれ電気的に分離されている。FIG. 6 shows a plan view of a conventional semiconductor device in which a semiconductor element is formed in a conventional package, and FIG.
Shows the A-B cross section. 6 and 7,
An outer frame 2 made of an insulating material such as ceramic is formed on a heat dissipation plate 1 made of copper. The input lead 3 and the output lead 4 respectively penetrate the inside and outside of the outer frame 2 and are electrically separated from the heat sink 1.
【０００４】以上、放熱板１、外枠２、入力リード３お
よび出力リード４により従来のパッケージが構成されて
いる。As described above, the heat dissipation plate 1, the outer frame 2, the input lead 3 and the output lead 4 constitute a conventional package.
【０００５】次に、従来の半導体装置およびその製造方
法について説明する。放熱板１上であって、外枠２の内
側には、電力増幅器である半導体素子５が形成されてい
る。半導体素子５は、熱抵抗を低減するためにチップ厚
を薄くし、さらに裏面には金等をメッキしている。Next, a conventional semiconductor device and its manufacturing method will be described. A semiconductor element 5, which is a power amplifier, is formed on the heat sink 1 and inside the outer frame 2. The semiconductor element 5 has a thin chip thickness in order to reduce thermal resistance, and the back surface is plated with gold or the like.
【０００６】また、同様に放熱板１上であって、外枠２
の内側には、電力の分配・合成やトランジスタの入出力
インピーダンス整合をとるために設けられ、セラミック
基板と表面配線と裏面電極とで構成されている回路基板
６が形成されている。この回路基板６は、ワイヤー７に
より半導体素子５および入力リード３、または半導体素
子５および出力リード４にそれぞれ接続されている。Similarly, on the heat sink 1, the outer frame 2
A circuit board 6, which is provided for the purpose of distributing / combining power and matching the input / output impedance of the transistor, is formed inside of the, and is composed of a ceramic substrate, a front surface wiring, and a back surface electrode. The circuit board 6 is connected to the semiconductor element 5 and the input lead 3 or the semiconductor element 5 and the output lead 4 by a wire 7, respectively.
【０００７】放熱板１と半導体素子５、放熱板１と回路
基板６の間にはそれぞれＡｕＳｎ合金箔８が設けられて
おり、半導体装置をリフロー炉の中に通すことによりＡ
ｕＳｎ合金箔８を加熱融解し、放熱板１と半導体素子
５、放熱板１と回路基板６とをそれぞれ固着する。AuSn alloy foils 8 are provided between the heat sink 1 and the semiconductor element 5 and between the heat sink 1 and the circuit board 6, respectively. By passing the semiconductor device through a reflow furnace,
The uSn alloy foil 8 is heated and melted to fix the heat sink 1 and the semiconductor element 5, and the heat sink 1 and the circuit board 6 respectively.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、従来の
半導体装置では、ＡｕＳｎ合金箔をリフローにより加熱
融解する際に、融けたＡｕＳｎ合金箔が放熱板の表面上
に拡がり、これにより半導体素子が予定した位置からず
れてしまうという問題があった。However, in the conventional semiconductor device, when the AuSn alloy foil is heated and melted by the reflow, the melted AuSn alloy foil spreads on the surface of the heat dissipation plate, whereby the semiconductor element is designed. There was a problem that it was out of position.
【０００９】本発明は、電子素子を、予定した位置から
ずれることなく放熱板に固着することのできるパッケー
ジならびに半導体装置およびその製造方法を提供するこ
とを目的とする。It is an object of the present invention to provide a package, a semiconductor device and a method for manufacturing the same, in which an electronic element can be fixed to a heat sink without being displaced from a predetermined position.
【００１０】[0010]
【課題を解決するための手段】本発明の電子装置は、素
子保持板と、前記素子保持板上に形成された接着用合金
と、前記素子保持板上に形成され、開口部または切り欠
き部を有する位置規正板と、前記素子保持板に対し前記
位置規正板の位置を規制する外枠と、前記素子保持基板
の前記開口部または切り欠き部に保持された電子素子と
を有し、前記開口部または前記切り欠き部の内側壁に前
記接着用合金を逃がすための窪みが設けられているもの
である。SUMMARY OF THE INVENTION The electronic device of the present invention is
Sub-holding plate and bonding alloy formed on the element holding plate
When formed on the element holding plate, and the position regulating plate having an opening or cutout portion, wherein with respect to the element holding plate
An outer frame for regulating the position of the position regulating plate, and the element holding substrate
An electronic element held in the opening or notch
Has a front surface on the inner wall of the opening or the notch.
The recess is provided for allowing the adhesive alloy to escape .
【００１１】本発明により、素子保持板上における素子
の位置が位置規正板により規正されるために、リフロー
による加熱処理の際に、半導体素子が予定していた位置
からずれてしまうことがない。According to the present invention, since the position of the element on the element holding plate is regulated by the position regulating plate, the semiconductor element does not deviate from the expected position during the heat treatment by reflow.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態におけ
るパッケージならびに半導体装置およびその製造方法に
ついて図面を用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A package, a semiconductor device and a method for manufacturing the same according to the embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は、本発明の実施の形態におけるパッ
ケージに半導体素子を形成してなる従来の半導体装置の
平面図を示し、図２は、そのＡ−Ｂ断面を示す。図１お
よび図２において、銅からなり、素子保持機能を有する
放熱板１上にセラミック等の絶縁体で構成される外枠２
が形成されている。入力リード３および出力リード４は
それぞれ外枠２の内外に貫通しており、それぞれ放熱板
１とは電気的に分離されている。放熱板１上には、金属
またはカーボンで構成された薄板に複数の開口部９を形
成してなる位置規正板１０が、接着部材であるＡｇロウ
板１１を介して固着されている。このＡｇロウ板１１は
位置規正板１０とほぼ同じ形状を有している。開口部９
の四隅の内側壁には、接着剤逃がし用の窪み１３がそれ
ぞれ設けられており、素子を固定するためのやや過剰な
接着剤が使用されても、位置規正板の外部に接着剤が漏
出するのを防止できる。FIG. 1 shows a plan view of a conventional semiconductor device in which a semiconductor element is formed in a package according to an embodiment of the present invention, and FIG. 2 shows an AB cross section thereof. In FIGS. 1 and 2, an outer frame 2 made of copper and made of an insulator such as ceramics is provided on a heat dissipation plate 1 having an element holding function.
Are formed. The input lead 3 and the output lead 4 respectively penetrate the inside and outside of the outer frame 2 and are electrically separated from the heat sink 1. A position regulating plate 10 formed by forming a plurality of openings 9 in a thin plate made of metal or carbon is fixed on the heat dissipation plate 1 via an Ag brazing plate 11 which is an adhesive member. The Ag brazing plate 11 has substantially the same shape as the position regulating plate 10. Opening 9
The inner side walls of the four corners are provided with recesses 13 for releasing the adhesive, and even if a slightly excessive amount of the adhesive for fixing the element is used, the adhesive leaks to the outside of the position regulating plate. Can be prevented.
【００１４】以上、放熱板１、外枠２、入力リード３お
よび出力リード４、位置規正板１０、Ａｇロウ板１１に
より本発明の実施の形態におけるパッケージが構成され
ている。なお、位置規正板１０が十分に大きく、外枠２
に位置規正される状態であれば、必ずしもＡｇロウ板１
１を用いて位置規正板１０を放熱板１に固着する必要は
ない。As described above, the heat dissipation plate 1, the outer frame 2, the input lead 3 and the output lead 4, the position regulating plate 10, and the Ag solder plate 11 constitute a package according to the embodiment of the present invention. In addition, the position regulating plate 10 is sufficiently large, and the outer frame 2
If the position is regulated in
It is not necessary to fix the position regulating plate 10 to the heat radiating plate 1 by using 1.
【００１５】次に、本発明の実施の形態における半導体
装置について説明する。図１および図２において、位置
規正板１０の開口部９内には、電力増幅器である半導体
素子５が、接着用合金であるＡｕＳｎ合金箔８を介して
放熱板１上に形成されている。半導体素子５は、熱抵抗
を低減するためにチップ厚を薄くしてさらに裏面には金
などをメッキしている。Next, a semiconductor device according to an embodiment of the present invention will be described. In FIGS. 1 and 2, a semiconductor element 5 which is a power amplifier is formed in the opening 9 of the position regulating plate 10 on the heat dissipation plate 1 via an AuSn alloy foil 8 which is an adhesive alloy. The semiconductor element 5 has a thin chip thickness in order to reduce thermal resistance, and the back surface is plated with gold or the like.
【００１６】また、位置規正板１０の他の開口部９内に
は、電力の分配・合成やトランジスタの入出力インピー
ダンス整合をとるために設けられ、セラミック基板と表
面配線と裏面電極とで構成されている回路基板６が形成
されている。この回路基板６は、ワイヤー７により入力
リード３および半導体素子５と、または出力リード４お
よび半導体素子５とそれぞれ接続されている。Further, the other opening 9 of the position regulating plate 10 is provided for distributing / combining electric power and for matching the input / output impedance of the transistor, and is composed of a ceramic substrate, a front surface wiring and a back surface electrode. The circuit board 6 is formed. The circuit board 6 is connected to the input lead 3 and the semiconductor element 5 or the output lead 4 and the semiconductor element 5 by a wire 7, respectively.
【００１７】以上のように、半導体素子５は、位置規正
板１０によって規正されているため、放熱板１上での位
置ずれが生じない。なお、位置を規正される対象物は、
半導体素子５に限らず、スイッチ素子等の他の電子素子
であってもよい。As described above, since the semiconductor element 5 is regulated by the position regulating plate 10, the positional displacement on the heat dissipation plate 1 does not occur. In addition, the object whose position is regulated is
The electronic device is not limited to the semiconductor device 5, and may be another electronic device such as a switch device.
【００１８】図３（ａ）は、開口部９を有する位置規正
板１０の平面図である。位置規正板１０は、半導体素子
５を位置規正する機能を有するものであればよく、例え
ば図３（ｂ）に示すように、切り欠き部９ａを有するも
のであっても同様に実施可能である。FIG. 3A is a plan view of the position regulating plate 10 having the opening 9. The position regulating plate 10 only needs to have a function of regulating the position of the semiconductor element 5. For example, as shown in FIG. 3B, even if the position regulating plate 10 has a notch 9a, it can be similarly implemented. .
【００１９】さらに、図４に示すように位置規正板１０
を用いずに、放熱板１の主面に半導体素子５を位置規正
する機能を有する凹部１４を形成しても同様に実施可能
である。Further, as shown in FIG. 4, the position regulating plate 10
It is also possible to form the concave portion 14 having a function of positioning the semiconductor element 5 on the main surface of the heat dissipation plate 1 without using the above.
【００２０】次に、本発明の実施の形態における半導体
装置の製造方法について図５を用いて説明する。まず、
図５（ａ）に示すように、入力リード３および出力リー
ド４を設けた外枠２を放熱板１上に形成する。次に、放
熱板１上にＡｇロウ板１１および位置規正板１０を順次
を設置する。そして、放熱板１を８００度に昇温するこ
とによりＡｇロウ板１１を融解する。その後再び室温に
戻すことによりＡｇロウ板１１を固化し、位置規正板１
０を放熱板１に固着する。この工程をリフローと呼ぶ。
なお、このリフローは、位置規正板１０および外枠２を
放熱板１に固着するために行うリフローと、同時に行っ
てもよい。Next, a method of manufacturing a semiconductor device according to the embodiment of the present invention will be described with reference to FIG. First,
As shown in FIG. 5A, the outer frame 2 provided with the input leads 3 and the output leads 4 is formed on the heat dissipation plate 1. Next, the Ag brazing plate 11 and the position regulating plate 10 are sequentially installed on the heat dissipation plate 1. Then, the Ag brazing plate 11 is melted by raising the temperature of the heat dissipation plate 1 to 800 degrees. Then, by returning to room temperature again, the Ag brazing plate 11 is solidified, and the position regulating plate 1
0 is fixed to the heat sink 1. This process is called reflow.
Note that this reflow may be performed at the same time as the reflow performed to fix the position regulating plate 10 and the outer frame 2 to the heat dissipation plate 1.
【００２１】次に、図５（ｂ）に示すように、位置規正
板１０の開口部９内に、ＡｕＳｎ合金箔８および半導体
素子５を順次載置し、位置規正板１０の他の開口部９内
に、ＡｕＳｎ合金箔８および回路基板６を順次載置す
る。このように、半導体素子５および回路基板６は、位
置規正板１０の開口部９内にはめ込むだけでよく、半導
体素子５および回路基板６の位置決めが容易である。ま
た、この工程で多少の振動があっても、半導体素子５お
よび回路基板６の位置がずれることはない。Next, as shown in FIG. 5B, the AuSn alloy foil 8 and the semiconductor element 5 are sequentially placed in the opening 9 of the position regulating plate 10, and the other opening of the position regulating plate 10 is placed. The AuSn alloy foil 8 and the circuit board 6 are sequentially placed in the substrate 9. As described above, the semiconductor element 5 and the circuit board 6 need only be fitted into the opening 9 of the position regulating plate 10, and the semiconductor element 5 and the circuit board 6 can be easily positioned. Further, even if there is some vibration in this step, the positions of the semiconductor element 5 and the circuit board 6 do not shift.
【００２２】次に、図５（ｃ）に示すように、厚さ約５
０μｍ程度と非常に薄い半導体素子５が、後のリフロー
の工程において凹形状に反ってしまい、両端が放熱板１
から浮いてしまうことを防止する目的で、半導体素子５
および回路基板６に接合し、かつ開口部１１より小さな
突起を有し、カーボンで構成された押圧部材である重し
１２を、半導体素子５および回路基板６上に載置する。
そして、図５（ｄ）に示すような状態で放熱板１を３０
０度でリフローする。このリフローにより、ＡｕＳｎ合
金箔８が融解し、半導体素子５が反ることなく、半導体
素子５および回路基板６が放熱板１に密着性よく固着す
る。このとき、Ａｇロウ板１１の融点は、ＡｕＳｎ合金
箔８の融点よりも高いため、ＡｕＳｎ合金箔８を融解さ
せるときにＡｇロウ板１１が融解して位置規正板１０自
体の位置がずれてしまうことはない。Next, as shown in FIG. 5C, the thickness is about 5
The semiconductor element 5 having a very thin thickness of about 0 μm is warped into a concave shape in the subsequent reflow process, and both ends of the heat sink 1
For the purpose of preventing the semiconductor element 5 from floating,
The weight 12, which is a pressing member made of carbon and bonded to the circuit board 6 and having a projection smaller than the opening 11, is placed on the semiconductor element 5 and the circuit board 6.
Then, in the state shown in FIG.
Reflow at 0 degrees. Due to this reflow, the AuSn alloy foil 8 is melted, the semiconductor element 5 is not warped, and the semiconductor element 5 and the circuit board 6 are firmly attached to the heat dissipation plate 1. At this time, since the melting point of the Ag solder plate 11 is higher than that of the AuSn alloy foil 8, when the AuSn alloy foil 8 is melted, the Ag solder plate 11 melts and the position of the position regulating plate 10 itself shifts. There is no such thing.
【００２３】最後に、図５（ｅ）に示すように、重し１
２を取り外し、入力リード３および出力リード４の外枠
２の内側部分と回路基板６、また、半導体素子５と回路
基板６とをそれぞれワイヤー７で電気的に接続して半導
体装置が完成する。Finally, as shown in FIG. 5 (e), the weight 1
2 is removed, and the inner portions of the outer frame 2 of the input leads 3 and the output leads 4 and the circuit board 6, and the semiconductor element 5 and the circuit board 6 are electrically connected by wires 7, respectively, to complete the semiconductor device.
【００２４】本実施の形態における半導体装置の製造方
法は、リフローによる加熱処理を行う際、半導体素子５
および回路基板６が、位置規正板１０により、位置が規
正されているため、ＡｕＳｎ合金箔８が融解したとき半
導体素子５および回路基板６が位置ずれを起こさないと
いう効果を有する。In the method of manufacturing the semiconductor device according to the present embodiment, the semiconductor element 5 is used when the heat treatment by reflow is performed.
Further, since the position of the circuit board 6 is regulated by the position regulating plate 10, there is an effect that the semiconductor element 5 and the circuit board 6 are not displaced when the AuSn alloy foil 8 is melted.
【００２５】また、本実施の形態における半導体装置の
製造方法は、開口部９の四隅の内側壁に窪み１３を設け
ることにより、リフローの際に融解した余分なＡｕＳｎ
合金８が窪み１３に溜まり、開口部９から融解したＡｕ
Ｓｎ合金箔８が溢れることがないという効果を有する。Further, in the method of manufacturing the semiconductor device according to the present embodiment, the recesses 13 are provided on the inner sidewalls at the four corners of the opening 9 so that excess AuSn melted during reflow is formed.
The alloy 8 was accumulated in the depression 13 and melted from the opening 9
It has an effect that the Sn alloy foil 8 does not overflow.
【００２６】なお、位置規正板１０が外枠２に位置規正
される形状を有していれば、位置規正板１０を放熱板１
に固着する必要がなく、半導体装置の完成後に位置規正
板１０を取り外して、これを繰り返し使用することがで
き、資源の有効利用、コスト削減の面からも有利であ
る。If the position regulating plate 10 has a shape to be regulated in position by the outer frame 2, the position regulating plate 10 is replaced with the heat radiating plate 1.
It is not necessary to fix the semiconductor device to the device, the position regulating plate 10 can be removed after the semiconductor device is completed, and this can be used repeatedly, which is advantageous in terms of effective use of resources and cost reduction.
【００２７】[0027]
【発明の効果】以上のように、本発明のパッケージは、
位置規正板を有するため、半導体素子を容易かつ確実に
放熱板に固着することができ、量産性が大幅に改善され
る。As described above, the package of the present invention is
Since the position regulating plate is provided, the semiconductor element can be easily and reliably fixed to the heat dissipation plate, and mass productivity is greatly improved.
【図１】本発明の実施の形態における半導体装置の平面
図FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
【図２】同半導体装置の断面図FIG. 2 is a sectional view of the semiconductor device.
【図３】本発明の実施の形態における半導体装置におけ
る位置規正板の平面図FIG. 3 is a plan view of the position regulating plate in the semiconductor device according to the embodiment of the present invention.
【図４】本発明の実施の形態におけるパッケージの断面
図FIG. 4 is a sectional view of the package according to the embodiment of the present invention.
【図５】本発明の実施の形態における半導体装置の製造
方法を示す図FIG. 5 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図６】従来の半導体装置の平面図FIG. 6 is a plan view of a conventional semiconductor device.
【図７】同半導体装置の断面図FIG. 7 is a sectional view of the semiconductor device.
１ 放熱板 ２ 外枠 ３ 入力リード ４ 出力リード ５ 半導体素子 ６ 回路基板 ７ ワイヤー ８ ＡｕＳｎ合金箔 ９ 開口部 １０ 位置規正板 １１ Ａｇロウ板 １２ 重し １３ 窪み １４ 凹部 1 heat sink 2 outer frame 3 input leads 4 output leads 5 Semiconductor element 6 circuit board 7 wires 8 AuSn alloy foil 9 openings 10 Position control plate 11 Ag brazing board 12 weights 13 hollow 14 recess
フロントページの続き (56)参考文献 特開 昭62−235759（ＪＰ，Ａ) 特開 平９−139395（ＪＰ，Ａ) 特開 平５−152473（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/52 H01L 23/40 H01L 23/48 H01L 25/00 H01L 23/52 Continuation of front page (56) Reference JP 62-235759 (JP, A) JP 9-139395 (JP, A) JP 5-152473 (JP, A) (58) Fields investigated (Int .Cl. 7 , DB name) H01L 23/12 H01L 21/52 H01L 23/40 H01L 23/48 H01L 25/00 H01L 23/52
Claims (3)
された接着用合金と、前記素子保持板上に形成され、開
口部または切り欠き部を有する位置規正板と、前記素子
保持板に対し前記位置規正板の位置を規制する外枠と、
前記素子保持基板の前記開口部または切り欠き部に保持
された電子素子とを有し、前記開口部または前記切り欠
き部の内側壁に前記接着用合金を逃がすための窪みが設
けられていることを特徴とする電子装置。 And 1. A device holding plate, wherein the bonding alloy which is formed on the element holding plate, is formed on the element holding plate, and the position regulating plate having an opening or cutout portion, wherein the device
An outer frame that regulates the position of the position regulating plate with respect to the holding plate,
Holding in the opening or notch of the element holding substrate
And the opening or the notch.
There is a recess on the inner wall of the opening to allow the adhesive alloy to escape.
An electronic device characterized by being removed.
特徴とする請求項１記載の電子装置。 2. The electronic device is a semiconductor device
The electronic device according to claim 1, which is characterized in that.
程と、前記素子保持板上に、内側壁に窪みを設けた開口
部または切り欠き部を有する位置規正板を、外枠によっ
て前記素子保持板に対し位置を規制しつつ形成する工程
と、前記開口部または切り欠き部に電子素子を配置する
工程と、前記接着用合金を溶融して前記電子素子を、前
記接着用合金を前記窪みに逃がしつつ固着する工程とを
有することを特徴とする電子装置の製造方法。3. A step of forming an adhesive alloy on an element holding plate , and a step of forming a position regulating plate having an opening or a notch having a recess on an inner wall on the element holding plate by an outer frame.
Forming while regulating a position with respect to the element holding plate Te, placing the electronic device in the opening or the cutout portion, the electronic device by melting the bonding alloy, before
Method of manufacturing an electronic device characterized by a step of fixing while Relieve serial bonding alloy in the recess above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000290402A JP3454240B2 (en) | 1998-10-21 | 2000-09-25 | Electronic device and method of manufacturing the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29940298 | 1998-10-21 | ||
| JP10-299402 | 1998-10-21 | ||
| JP2000290402A JP3454240B2 (en) | 1998-10-21 | 2000-09-25 | Electronic device and method of manufacturing the same |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11299683A Division JP2000195981A (en) | 1998-10-21 | 1999-10-21 | Package and semiconductor device, and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001118958A JP2001118958A (en) | 2001-04-27 |
| JP3454240B2 true JP3454240B2 (en) | 2003-10-06 |
Family
ID=26561909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000290402A Expired - Fee Related JP3454240B2 (en) | 1998-10-21 | 2000-09-25 | Electronic device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3454240B2 (en) |
-
2000
- 2000-09-25 JP JP2000290402A patent/JP3454240B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001118958A (en) | 2001-04-27 |
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