JPS6214705Y2 - - Google Patents
Info
- Publication number
- JPS6214705Y2 JPS6214705Y2 JP415280U JP415280U JPS6214705Y2 JP S6214705 Y2 JPS6214705 Y2 JP S6214705Y2 JP 415280 U JP415280 U JP 415280U JP 415280 U JP415280 U JP 415280U JP S6214705 Y2 JPS6214705 Y2 JP S6214705Y2
- Authority
- JP
- Japan
- Prior art keywords
- insulated
- heat sink
- lead
- frame
- insulating plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000008188 pellet Substances 0.000 claims description 17
- 238000000465 moulding Methods 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 8
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000003825 pressing Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案はトランジスタやサイリスタ等の半導体
装置に関するものである。[Detailed Description of the Invention] The present invention relates to semiconductor devices such as transistors and thyristors.
一般に、半導体装置は放熱板上にペレツトを直
接に半田付けした非絶縁型と、放熱板上にリード
を絶縁板を介して半田付けし、このリード上にペ
レツトを半田付けする絶縁型とが多く用いられて
いる。例えば前者非絶縁型半導体装置をサイリス
タを例に説明すると、これは第１図及び第２図に
示すような放熱板フレーム１とリードフレーム２
から複数個が一括して製造されている。即ち、放
熱板フレーム１は複数の放熱板３を一連一体に成
形したものであり、リードフレーム２はアノード
用リード４ａとカソード用リード４ｂ及びゲート
用リード４ｃを１組とするリード部４を複数組一
連一体に成形したものである。又、各放熱板３の
端面にはリードかしめ用の切欠き５が予め形成さ
れ、この切欠き５にリード部４のアノード用リー
ド４ａの先端折曲部６が嵌着されてかしめられる
ことにより、両フレーム１，２を一体化してい
る。そして、この一体化の後に各放熱板３上の定
位置にペレツト７を半田８で固着し、更にペレツ
ト７のカソード電極とリード４ｂを金属細線９
で、ゲート電極とリード４ｃを金属細線１０で
夫々接続してから、鎖線で示す要部を樹脂１１で
モールドして、個々の製品に分割している。尚、
上記放熱板３へのリード４ａのかしめは、例えば
第３図及び第４図に示すように、切欠き５にリー
ド４ａの先端折曲部６を嵌めて切欠き５の両側壁
を切欠き５より幅広で両側先端に切刃１２，１２
を有する押し型１３で押圧して、両側壁を切込
み、続いて内側に押圧変形させて行うようにす
る。この時、リード４ａと放熱板３との電気的接
続を確実にする目的でかしめ部分を半田付けする
場合もある。 In general, there are two types of semiconductor devices: non-insulated type, in which pellets are soldered directly onto a heat sink, and insulated type, in which leads are soldered to the heat sink through an insulating plate, and pellets are soldered onto these leads. It is used. For example, if we explain the former non-insulated semiconductor device using a thyristor as an example, this device has a heat sink frame 1 and a lead frame 2 as shown in FIGS. 1 and 2.
Multiple pieces are manufactured at once. That is, the heat sink frame 1 is formed by integrally molding a plurality of heat sink plates 3, and the lead frame 2 has a plurality of lead portions 4 each including an anode lead 4a, a cathode lead 4b, and a gate lead 4c. The set is molded in one piece. In addition, a notch 5 for lead caulking is formed in advance on the end surface of each heat sink 3, and the tip bent portion 6 of the anode lead 4a of the lead portion 4 is fitted into this notch 5 and caulked. , both frames 1 and 2 are integrated. After this integration, the pellets 7 are fixed at fixed positions on each heat sink 3 with solder 8, and the cathode electrodes and leads 4b of the pellets 7 are connected with thin metal wires 9.
After connecting the gate electrodes and leads 4c with thin metal wires 10, the main parts indicated by chain lines are molded with resin 11, and the product is divided into individual products. still,
To caulk the leads 4a to the heat dissipation plate 3, for example, as shown in FIG. 3 and FIG. Wider with cutting edges 12, 12 on both ends
This is done by pressing with a pressing mold 13 having a shape, cutting both side walls, and then pressing and deforming it inward. At this time, the caulked portions may be soldered to ensure electrical connection between the leads 4a and the heat sink 3.
このような非絶縁型のものは放熱板３自体がア
ノード電極として用いられ、又、放熱性を良くす
るために放熱板３をシヤーシ等に直付けして取付
けられている。又、アノード接地でない回路に使
用する場合は放熱板３とシヤーシ等の間に絶縁シ
ートを介在させて取付けていた。ところが、放熱
板３の底面にメツキバリや、プレス成形時に生じ
る加工バリがあると、このバリが絶縁シートを突
き破つて放熱板３がシヤーシ等にシヨートする恐
れがあり、シヤーシ等との絶縁が不安定になる欠
点があつた。 In such a non-insulated type, the heat sink 3 itself is used as an anode electrode, and the heat sink 3 is directly attached to a chassis or the like to improve heat dissipation. Furthermore, when used in a circuit other than anode grounding, an insulating sheet is interposed between the heat sink 3 and the chassis, etc. However, if there is a metal burr on the bottom surface of the heat sink 3 or a processing burr generated during press molding, there is a risk that the burr will break through the insulating sheet and the heat sink 3 will be shot into the chassis, etc., resulting in poor insulation with the chassis, etc. It had the disadvantage of being unstable.
この非絶縁型の欠点を除去するものとして絶縁
型半導体装置が知られている。これは第５図及び
第６図に示すように、放熱板フレーム１４の各放
熱板１５上にセラミツク等の絶縁板１６を半田１
７で固着し、更に絶縁板１６上にリードフレーム
１８のアノード用リード１９ａを半田２０で固着
して両フレーム１４，１８を半田結合にて一体化
する。その後、リード１９ａ上にペレツト２１を
半田２２でマウントしてから、ペレツト２１の各
電極とリード１９ｂ，１９ｃとを金属細線２３，
２４で接続し、更に鎖線部分を樹脂２５でモール
ドして、個々の製品毎に分割する。このようにす
ると、ペレツト２１のアノード電極はリード１９
ａだけで導出され、放熱板１５とは絶縁板１６で
絶縁されるため、アノード非接地で使用する場合
でも放熱板１５をシヤーシ等に直付けできる。 Insulated semiconductor devices are known as devices that eliminate the drawbacks of non-insulated semiconductor devices. As shown in FIGS. 5 and 6, an insulating plate 16 made of ceramic or the like is soldered onto each heat sink 15 of the heat sink frame 14.
7, and further, the anode lead 19a of the lead frame 18 is fixed on the insulating plate 16 with solder 20, and both frames 14 and 18 are integrated by soldering. After that, the pellet 21 is mounted on the lead 19a with solder 22, and then each electrode of the pellet 21 and the leads 19b, 19c are connected with a thin metal wire 23,
24, and the chain line portions are further molded with resin 25, and each product is divided into individual products. In this way, the anode electrode of the pellet 21 is connected to the lead 19.
Since the heat sink 15 is insulated from the heat sink 15 by the insulating plate 16, the heat sink 15 can be directly attached to a chassis or the like even when the anode is not grounded.
ところが、上記絶縁型のものはペレツトマウン
ト時に半田２２を溶融させるが、その時の加熱温
度で絶縁板１６上下の半田１７，２０も溶融し
て、放熱板１５とリード部１９の相対位置がズレ
ることがあつた。このような位置ズレが生じると
半田１７，２０が絶縁板１６から喰み出してシヨ
ートしたりするトラブルが生じ、不良品の発生率
が高くなる欠点が生じた。又、この位置ズレを防
止する工夫として、前記各半田１７，２０，２２
の融点を変えることが知られている。つまり、半
田１７の融点をT1、半田２０の融点をT2、半田
２２の融点をT3とするとT1＞T2＞T3と設定すれ
ば、ペレツトマウント時にT3まで加熱しても半
田１７，２０が溶融する心配はなく、従つて放熱
板１５とリード部１９の相対位置ズレが防止され
る。しかし、各半田１７，２０，２２の融点を変
えると作業上の処理や管理が繁雑となり、実用的
ではなかつた。 However, in the insulating type, the solder 22 is melted during pellet mounting, but the heating temperature at that time also melts the solder 17, 20 on the upper and lower sides of the insulating plate 16, causing the relative position of the heat sink 15 and the lead portion 19 to shift. Something happened. When such a positional shift occurs, a problem arises in that the solders 17 and 20 protrude from the insulating plate 16 and shoot out, resulting in a disadvantage that the incidence of defective products increases. In addition, as a measure to prevent this positional shift, each of the solders 17, 20, 22
is known to change the melting point of In other words, if the melting point of the solder 17 is T 1 , the melting point of the solder 20 is T 2 , and the melting point of the solder 22 is T 3 , then if you set T 1 > T 2 > T 3 , you can heat up to T 3 during pellet mounting. There is no fear that the solders 17 and 20 will melt, and therefore the relative positional deviation between the heat sink 15 and the lead portion 19 is prevented. However, changing the melting points of each solder 17, 20, and 22 would complicate work processing and management, making it impractical.
又、従来は上記した絶縁型半導体装置を製造す
る場合は絶縁型に応じた製造ラインを設けて行
い、この同じラインをそのまま用いて別の非絶縁
型半導体装置を製造することはできなかつた。
尚、同一ラインで非絶縁型を製造するとなると絶
縁型から非絶縁型の変更に応じた設備の切換えが
必要で、且つこの切換えが非常に手間を要した。 Furthermore, conventionally, when manufacturing the above-mentioned insulated type semiconductor devices, manufacturing lines were set up according to the type of insulation, and it was not possible to use the same line as it was to manufacture other non-insulated type semiconductor devices.
In addition, if non-insulated types are manufactured on the same line, it is necessary to change equipment according to the change from insulated types to non-insulated types, and this changeover requires a lot of effort.
そこで本考案は上記従来の欠点に鑑み、これを
改良・除去するものとして、次の半導体装置を提
供する。即ち、本考案は１つの放熱板フレームと
１つのリードフレームとで絶縁型半導体装置と非
絶縁型半導体装置の２種タイプを同時に形成する
もので、例えばサイリスタの場合は第７図に示す
放熱板フレーム２６とリードフレーム２７を用い
る。 Therefore, in view of the above-mentioned conventional drawbacks, the present invention provides the following semiconductor device to improve and eliminate these drawbacks. That is, the present invention simultaneously forms two types of semiconductor devices, an insulated semiconductor device and a non-insulated semiconductor device, using one heat sink frame and one lead frame. For example, in the case of a thyristor, the heat sink shown in FIG. A frame 26 and a lead frame 27 are used.
上記放熱板フレーム２６は第１図で示した非絶
縁型と同じ放熱板２８と、第５図で示した絶縁型
と同じ放熱板２９とを交互に、且つ夫々を複数枚
並べて一体成形したものである。一方、リードフ
レーム２７は第１図に示した非絶縁型と同じリー
ド部３０と、第５図で示した絶縁型と同じリード
部３１を交互に、且つ夫々を複数組並べて一体成
形したものである。そして、放熱板フレーム２６
の非絶縁型の各放熱板２８にリードフレーム２７
の非絶縁型の各リード部３０のリード３０ａをか
しめて固定すると共に、絶縁型の各放熱板２９上
に絶縁型の各リード部３１のリード３１ａを絶縁
板３２を介して半田付けする。つまり、絶縁板フ
レーム２６とリードフレーム２７は放熱板２８と
リード３０ａとのかしめにより、機械的強固に一
体化される。このように両フレーム２６，２７を
一体化すると、後は従来同様に非絶縁型放熱板２
８上にはペレツト３３を直接マウントして、この
ペレツト３３と各リード３０ｂ，３０ｃを金属細
線３４，３５で接続し、他方、絶縁型リード部３
１のリード３１ａ上にもペレツト３３をマウント
して、各リード３１ｂ，３１ｃと金属細線３４，
３５で接続する。このペレツトマウント時に絶縁
型放熱板２９上の半田が溶融しても、両フレーム
２６，２７がかしめで一体化されているので放熱
板２９とリード部３１の相対位置ズレはなく、従
つて正確なペレツトマウントができる。又、金属
細線３４，３５によるボンデイングが完了すると
第７図鎖線部分を樹脂３６でモールドして分割す
れば、絶縁型サイリスタと非絶縁型サイリスタが
同時に一括して得られる。 The heat sink frame 26 is made by integrally molding heat sinks 28 that are the same as the non-insulated type shown in FIG. 1 and heat sinks 29 that are the same as the insulated type shown in FIG. It is. On the other hand, the lead frame 27 is made by integrally molding the same lead parts 30 as the non-insulated type shown in FIG. 1 and the same lead parts 31 as the insulated type shown in FIG. be. And the heat sink frame 26
A lead frame 27 is attached to each non-insulated heat sink 28 of
The leads 30a of each non-insulated lead part 30 are caulked and fixed, and the leads 31a of each insulated lead part 31 are soldered onto each insulated heat sink 29 via an insulating plate 32. In other words, the insulating plate frame 26 and the lead frame 27 are mechanically strongly integrated by caulking the heat sink 28 and the leads 30a. When both frames 26 and 27 are integrated in this way, the rest is the non-insulated heat sink 2 as in the conventional case.
A pellet 33 is directly mounted on the lead part 8, and the pellet 33 and each lead 30b, 30c are connected with thin metal wires 34, 35.
A pellet 33 is also mounted on the lead 31a of No. 1, and each lead 31b, 31c and the thin metal wire 34,
Connect with 35. Even if the solder on the insulated heat sink 29 melts during pellet mounting, since the frames 26 and 27 are caulked together, there will be no deviation in the relative position of the heat sink 29 and the lead portion 31, thus ensuring accuracy. A pellet mount can be made. Further, when the bonding with the thin metal wires 34 and 35 is completed, the part shown in chain lines in FIG. 7 is molded with resin 36 and divided, thereby obtaining an insulated thyristor and a non-insulated thyristor at the same time.
尚、第７図では絶縁型と非絶縁型とを交互に配
列したが、この例に限らず、例えば非絶縁型を両
端部と中央部の３箇所に設けて他は全て絶縁型で
構成する等の工夫も可能である。又、本考案はサ
イリスタに限らず、トランジスタやIC等の他の
半導体装置にも十分適用し得るものである。 Although the insulated type and the non-insulated type are arranged alternately in Fig. 7, this example is not limited to this example. Other ideas are also possible. Further, the present invention is applicable not only to thyristors but also to other semiconductor devices such as transistors and ICs.
以上説明したように、本考案は１つの放熱板フ
レームと１つのリードフレームで絶縁型と非絶縁
型の半導体装置を複数個一括して形成するように
したから、絶縁型と非絶縁型が同一製造ラインで
でき、異なるタイプへの切換えの手間がなくな
る。又、絶縁型半導体装置のペレツトマウント時
での放熱板とリードの位置ズレによるトラブル
が、非絶縁型半導体装置の放熱板とリードとのか
しめによる一体化によつて完全に解消され、絶縁
型半導体装置の良品率の向上が図れる。 As explained above, in the present invention, multiple insulated and non-insulated semiconductor devices are formed at once using one heat sink frame and one lead frame, so the insulated and non-insulated types are the same. It can be done on the production line, eliminating the hassle of switching to a different type. In addition, troubles caused by misalignment of the heat sink and leads when mounting insulated semiconductor devices in pellets are completely eliminated by integrating the heat sink and leads of non-insulated semiconductor devices by caulking. The yield rate of semiconductor devices can be improved.
第１図は非絶縁型半導体装置の要部平面図、第
２図は第１図Ａ−Ａ線に沿う断面図、第３図及び
第４図は第１図及び第２図装置のかしめ部分での
かしめ要領を説明する斜視図、第５図は絶縁型半
導体装置の要部平面図、第６図は第５図Ｂ−Ｂ線
に沿う拡大断面図、第７図は本考案による半導体
装置の一実施例を示す要部平面図である。
２６……放熱板フレーム、２７……リードフレ
ーム、２８……（非絶縁型）放熱板、２９……
（絶縁型）放熱板、３０……非絶縁型リード部、
３０ａ，３０ｂ，３０ｃ，３１ａ，３１ｂ，３１
ｃ……リード、３１……絶縁型リード部、３２…
…絶縁板、３３……半導体ペレツト、３４，３５
……金属細線、３６……樹脂。
Figure 1 is a plan view of essential parts of a non-insulated semiconductor device, Figure 2 is a sectional view taken along the line A-A in Figure 1, and Figures 3 and 4 are caulking parts of the device shown in Figures 1 and 2. 5 is a plan view of essential parts of an insulated semiconductor device, FIG. 6 is an enlarged sectional view taken along line B-B in FIG. 5, and FIG. 7 is a semiconductor device according to the present invention. FIG. 2 is a plan view of essential parts showing one embodiment of the present invention. 26... Heat sink frame, 27... Lead frame, 28... (non-insulated type) heat sink, 29...
(insulated type) heat sink, 30...non-insulated lead part,
30a, 30b, 30c, 31a, 31b, 31
c...Lead, 31...Insulated lead part, 32...
...Insulating plate, 33...Semiconductor pellet, 34, 35
...Thin metal wire, 36...Resin.
Claims (1)
と、前記放熱板の全数より少ない複数の放熱板に
固定されたリードを有する非絶縁型リード部、及
び残りの放熱板上に絶縁板を介して固定されたリ
ードを有する絶縁型リード部を一体に成形したリ
ードフレームとを備え、前記非絶縁型リード部に
対応する放熱板上および前記絶縁板に固定された
リード上にそれぞれペレツトをマウントしたこと
を特徴とする半導体装置。 A heat sink frame formed by integrally molding a plurality of heat sinks, a non-insulated lead portion having leads fixed to a plurality of heat sinks less than the total number of the heat sinks, and fixed onto the remaining heat sinks via an insulating plate. and a lead frame integrally molded with an insulated lead part having a non-insulated lead part, and pellets are mounted on a heat dissipation plate corresponding to the non-insulated lead part and on a lead fixed to the insulating plate, respectively. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP415280U JPS6214705Y2 (en) | 1980-01-17 | 1980-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP415280U JPS6214705Y2 (en) | 1980-01-17 | 1980-01-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5744556U JPS5744556U (en) | 1982-03-11 |
| JPS6214705Y2 true JPS6214705Y2 (en) | 1987-04-15 |
Family
ID=29434483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP415280U Expired JPS6214705Y2 (en) | 1980-01-17 | 1980-01-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214705Y2 (en) |
-
1980
- 1980-01-17 JP JP415280U patent/JPS6214705Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5744556U (en) | 1982-03-11 |
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