JPH0512196A - Bus controller - Google Patents

Abstract

PURPOSE:To facilitate the development of a data exchange system in future between a central arithmetic processor and a peripheral device by transforming an IC forming a buffer into a single chip. CONSTITUTION:The data buses 11-14 are connected to a multi-port bus control part 10. The bus 11 is used for a CPU 8 and allocated by a single port together with the bus 12 used for a local bus 4 with a single port allocated, and the bus 13 used for a system bus 2 with a single port allocated respectively. A port control part 18 consists of an LSI and produces a control port signal for the part 10 based on an instruction of the CPU 8. Thus the number of working LSIs can be decreased with use of many ports despite the increase of peripheral devices. Furthermore the selection of ports, the direction of data, and the number of data bits can be optionally changed through the part 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller for exchanging data between a central processing unit and its peripherals,
In particular, it relates to a bus control device capable of exchanging data with a large number of peripheral devices.

[0002]

2. Description of the Related Art Transmission and reception of data between a central processing unit and peripheral devices are usually carried out via a bus. A conventional example of a device for controlling this bus is Japanese Patent Laid-Open No. 63-2.
No. 61451 or one shown in FIG. The bus control device shown in FIG. 3 has a buffer 3 for controlling the CPU bus 1 and the system bus 2, and a buffer 5 for controlling the CPU bus 1 and the local bus 4. By using this, more ICs were used, and control was performed by this. In FIG. 3, reference numeral 6 is a system memory for storing data transmitted via the system bus 2, and 7 is a local memory for storing data transmitted via the local bus 4. Reference numerals 6 and 7 also serve as peripheral devices in the system of FIG. Reference numeral 8 is a central processing unit, or CPU, which has various programs and controls the operation of the entire bus control system.

[0003]

However, in such a conventional bus control device, as the number of peripheral devices increases, the number of used buffers becomes very large, and as the number of used buffers increases. The number of places where soldering is required increases in the device manufacturing stage. Therefore, a defect such as a solder bridge is likely to occur, and further, if the system corresponds to the CPU 8 capable of processing many data bits such as 32 bits and 64 bits in the future, the number of ICs used will increase. Therefore, a large number of buffer ICs 3 and 5 are necessary for exchanging information between the CPU 8 and many peripheral devices 6 and 7, and accordingly, the defective rate of the substrate and the ICs used
There is a problem that the substrate occupancy rate becomes large due to.

The present invention has been made in view of the above problems. An object of the present invention is to integrate a buffer IC into a single chip so that a future data exchange system between a central processing unit and peripheral devices can be realized. Is to facilitate the development of.

It is another object of the present invention that even if the number of peripheral devices increases, the number of ICs to be used does not increase so much, and even if the data exchange system between the central processing unit and the peripheral devices develops, the multi-processor is It is an object of the present invention to provide a bus control device which can cope well with a port bus and the like and can perform processing.

[0006]

In order to solve the above problems, the present invention provides a bus control device for controlling a bus between a central processing unit and peripheral devices for exchanging data with the central processing unit. While providing a plurality of ports, it is connected between the bus control unit that controls data transfer in the plurality of ports and the central processing unit and the bus control means, and outputs a control port signal according to the operation content of the central processing unit. And a port control section for operating the bus control means.

[0007]

As described above, the present invention has a large number of ports, so that the number of peripheral devices used and the number of LSIs used can be reduced. Also, by having a port control unit,
The selection of each port, the data direction, and the number of data bits can be arbitrarily changed.

[0008]

1 is a diagram showing a schematic configuration of a multiport bus control device according to an embodiment of the present invention. In this figure,
Reference numeral 10 is a multiport bus control unit as bus control means for controlling the multiport bus. A plurality of data buses are connected to the multiport bus control unit 10. Of these, 11 is a data bus with the CPU 8, and one port is assigned. Further, 12 is a data bus with the local bus 4, and one port is assigned. Further, 13 is a data bus with the system bus, and one port is assigned. A system memory 14 is connected to the system bus 2 by a data bus 15. A local memory 16 is connected to the local bus 4 by a data bus 17. Reference numeral 18 is a port control unit configured by an LSI and generating a control port signal of the multiport bus control unit 10 based on an instruction from the CPU 8. 19 and 20 are C
PU8 is a bus that serves as a path for data transmitted / received, and 21 and 22 are buses that send a control port signal output from the port control unit 18 to the multiport bus control unit 10 (for simplicity, 3 ports are used. , 16-bit data). Further, 23 is the CPU 8 through the buses 21 and 22.
A terminal to which a control signal for switching the transfer direction sent from is input, 24 is the CPU 8 through the buses 21 and 22.
A terminal for inputting a control signal for switching the data width sent from the CPU, and 25 through the buses 21 and 22 for the CPU 8
This is a terminal to which the byte enable signal sent from is input.

FIG. 2 is a diagram for explaining a schematic configuration of a multiport bus control unit 10 composed of an LSI and a connection state with each bus 1, 2, 4. In the figure, 31 is a CPU which temporarily stores the transfer data during the data transfer operation between the CPU bus 1 and the multiport bus control unit 10.
A bus buffer 32 is a system bus buffer 33 for temporarily storing transfer data during a data transfer operation between the system bus 2 and the multiport bus control unit 10.
Is a local bus buffer that temporarily stores transfer data during a data transfer operation between the local bus 4 and the multiport bus control unit 10. Reference numeral 34 is a data control unit that executes control processing operations in the multiport bus control unit 10.

The operation of the multi-port bus control device having the above structure will be described below. First, according to the input signal 23 of FIG. 2, the data width (8 bits, 16
Bit, 32 bits) and input signal 2
4, the data transfer direction is switched. The byte width to be accessed can be easily changed by the input signal 25.

In this embodiment, the number of ports is three and the data width is 16 bits. However, the invention is not limited to the above, and a similar concept can be used for handling several ports and 32 bits or more. It can be easily used for system development.

[0012]

As is apparent from the above description, according to the present invention, it is possible to easily control the switching of the data transfer direction and the data width with a large number of ports. In addition, by making it one chip,
The number of peripheral ICs, which has been large in the past, is small, and a large number of buses can be controlled without complicating the circuit.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a multiport control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an LSI constituting the multiport bus control unit of the above embodiment.

FIG. 3 is a schematic configuration diagram of a conventional multi-bus control device.

[Explanation of symbols]

 1 CPU Bus 2 Local Bus 4 System Bus 10 Multi-Port Bus Control Unit 11, 12, 13, 14 Data Bus 14 System Memory 16 Local Memory 18 Port Control Unit 23, 24, 25 Control Signal Input Terminal 31 CPU Bus Buffer 32 System Bus Buffer 33 Local bus buffer 34 Data control unit

Claims (1)

Claim: What is claimed is: 1. A central processing unit, a peripheral device for exchanging data with the central processing unit, and a plurality of devices for transmitting data between the central processing unit and the peripheral device. Bus, a bus control unit connected to each bus for controlling data transfer in a plurality of ports, and connected between the central processing unit and the bus control unit and controlled according to the operation content of the central processing unit. A bus control device comprising: a port control unit that outputs a port signal to operate a bus control unit.