JP2005284848A - Emulation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of connecting wires connecting between two semiconductor chips in spite of a structure having two semiconductor chips. <P>SOLUTION: An emulation system 1 is used at the time of development using a microcomputer with a single chip having a CPU and a peripheral circuit. The emulation system 1 has a first chip 11 forming a CPU functioning section which emulates functions of the CPU, and also has a second chip 12 forming a peripheral circuit functioning section for emulating functions of the peripheral circuit as a chip independent from the first chip 11. In communication between two chips 11 and 12, address control sections 17 and 22 automatically controlling addresses are arranged on the two chips 11 and 12, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an emulation apparatus used when developing a system or apparatus incorporating a single-chip microcomputer composed of a CPU and peripheral circuits (ROM, RAM, I / O, etc.).

  In a single chip microcomputer, a CPU and peripheral circuits are formed on the same semiconductor chip, and the number of peripheral circuits mounted increases as the processing function increases. Further, the peripheral circuits to be mounted are variously changed according to the use of the microcomputer. When developing hardware and software using a microcomputer, an emulation device (for example, an in-circuit emulator) that emulates the function of the microcomputer is used.

  As for this emulation device, in order to flexibly cope with an increase in peripheral circuits mounted on a microcomputer and variations thereof, a semiconductor part that emulates the function of the CPU and a part that emulates the function of the peripheral circuit are different from each other. It may be configured with a chip. An example of such a configuration is shown in FIG. As shown in FIG. 3, the emulation device 1 includes an emulation board 2 and an external emulation device 3.

  The emulation board 2 includes a CPU variation chip (hereinafter referred to as a CPU evaluation chip) 4 that emulates a CPU function, a peripheral variation chip (hereinafter referred to as a peripheral evaluation chip) 5 that emulates the function of an I / O circuit, and a controller. 6 etc. are mounted, and are composed of multichips. As the CPU evaluation chip 4, a semiconductor chip dedicated for emulation is used. Further, as the peripheral evaluation chip 5, a microcomputer chip of a product is normally used, and the microcomputer chip of this product is configured to operate in an emulation mode.

  Here, the CPU evaluation chip 4 and the peripheral evaluation chip 5 are connected by 42 connection lines 7, through which communication is performed between the two chips. Among these 42 connection lines 7, there are 24 address lines, 16 data lines, one strobe line, and one R / W line. The peripheral evaluation chip 5 needs to be provided with 42 pads (terminals) in order to connect the 42 connection lines 7. Since these 42 pads are originally unnecessary as a microcomputer chip of a product, there is a demand for reducing them as much as possible. This is because if the number of pads for emulation can be reduced, the chip size can be reduced accordingly.

On the other hand, Patent Document 1 is conventionally known as a configuration for reducing the number of communication connection lines between two semiconductor chips. In the configuration of Patent Document 1, information (data) to be communicated is parallel-serial converted and serial communication is performed. As a result, the number of emulation pads provided on the peripheral evaluation chip can be reduced.
JP 2002-132419 A

However, since the configuration of Patent Document 1 is serial communication, if the amount of data to be communicated increases, the speed of communication may slow down, and there may be a situation where it cannot actually be used.
Accordingly, an object of the present invention is an emulation that can reduce the number of connection lines connecting two semiconductor chips and prevent a decrease in communication speed, even though the configuration includes two semiconductor chips. To provide the equipment.

  The emulation device of the present invention is used at the time of development using a single-chip microcomputer including a CPU and peripheral circuits, and includes a first chip constituting a CPU function unit that emulates the function of the CPU. And a second chip that constitutes a peripheral circuit function unit that emulates the function of the peripheral circuit, and automatically addresses in communication between the two chips. It is characterized in that an address control unit for controlling the above is provided in each of the two chips.

  According to the above configuration, when communication is performed between two chips, the address is automatically controlled by the address control unit of each chip. Therefore, the address connection line for connecting the two semiconductor chips Is no longer necessary. Therefore, although the configuration includes two semiconductor chips, the number of connection lines connecting the two semiconductor chips can be reduced, and the number of pads provided on the semiconductor chip can be reduced. And in the case of the said structure, communication speed does not fall.

  In the above structure, the peripheral circuit is preferably an I / O circuit. Furthermore, it is more preferable that a data transmission / reception unit for transmitting and receiving data in a time division manner in communication between the two chips is provided in each of the two chips.

An embodiment of the present invention will be described below with reference to FIGS. In addition, the same code | symbol is attached | subjected to the same part as a conventional structure (refer FIG. 3).
First, FIG. 1 is a block diagram schematically showing the electrical configuration of the emulation apparatus of this embodiment. As shown in FIG. 1, the emulation device 1 includes an emulation board 2 and an external emulation device 3. The external emulation device 3 is composed of a personal computer, for example, and software for controlling the emulation device 1 is installed.

  The emulation board 2 includes a CPU variation chip (hereinafter referred to as a CPU evaluation chip) 11 that emulates a CPU function, a peripheral variation chip (hereinafter referred to as a peripheral evaluation chip) 12 that emulates a function of an I / O circuit, and an emulation. A controller 6 or the like for controlling the entire apparatus 1 is mounted, and is configured by a multichip.

  The CPU evaluation chip 11 corresponds to the first chip of the present invention, and is composed of a semiconductor chip dedicated to emulation. The CPU evaluation chip 11 includes a CPU 13, a ROM 14, a RAM 15, an I / O 16, and a sequencer (address control unit) 17. The configuration of the CPU evaluation chip 11 other than the sequencer 17 is the same as the configuration of the conventional CPU evaluation chip 4.

  The peripheral evaluation chip 12 corresponds to the second chip of the present invention, and is usually composed of a product microcomputer chip, and is configured to operate the product microcomputer chip in an emulation mode. . The peripheral evaluation chip 12 includes a CPU 18, a ROM 19, a RAM 20, an I / O 21, and a sequencer (address control unit) 22.

  In this case, when the peripheral evaluation chip 12 is operated in the emulation mode, the I / O 21 and the sequencer 22 operate effectively, and the CPU 18, ROM 19 and RAM 20 are invalidated (marked with X in FIG. 1). reference). When the peripheral evaluation chip 12 is operated in the product mode, the CPU 18, the ROM 19, the RAM 20, and the I / O 21 are effectively operated and the sequencer 22 is invalidated. The configuration of the peripheral evaluation chip 12 other than the sequencer 22 is the same as the configuration of the conventional peripheral evaluation chip 5.

  In the present embodiment, for example, 18 connection lines 23 are connected between the CPU evaluation chip 11 and the peripheral evaluation chip 12, and communication is performed between the two chips 11 and 12 through this connection. Of these 18 connection lines 23, there are 16 data lines, one strobe line, and one R / W line. The peripheral evaluation chip 12 is provided with 18 pads (terminals) for connecting the 18 connection lines 23 and a necessary number of pads as product chips.

Next, the operation of the sequencers 17 and 22 of the two chips 11 and 12 will be described with reference to FIG. Each of the sequencers 17 and 22 has a function of performing dedicated address / data control (a function of automatically controlling addresses) in communication between the two chips 11 and 12.
Specifically, in the example of the address / data control shown in FIG. 2, at least one data update is synchronized between the CPU evaluation chip 11 and the peripheral evaluation chip 12 at an interval of 1600 ns (10 MHz), for example. Configured to be executed. in this case,
Data whose address is “0x01” is automatically updated at intervals of 200 ns.

Data whose address is “0x02” is automatically updated at 400 ns intervals.
Data whose address is “0x04” is automatically updated at intervals of 800 ns.
Each data whose addresses are “0x08” and “0x10” are automatically updated at intervals of 1600 ns.
That is, in the present embodiment, data transmission / reception between the two chips 11 and 12 is configured to be read / written in order according to the automatic control of the address.

  In other words, with regard to the above address control, in other words, the data with the address “0x04” rewritten by the instruction of the CPU is reflected in the peripheral evaluation chip 12 with a delay of the worst 800 ns. The present embodiment is effective for the control that can tolerate such a delay, and it is necessary to appropriately set the transfer interval of the sequencers 17 and 22 in accordance with the allowable minimum update interval.

Then, in the present embodiment, the sequencer 17 and 22, advance in any order, or, what sets or information updates the address at intervals (written in) is required to put. An example of settings necessary to realize the address control of FIG.
In this case, the total number of packets is 16. And
Packet 1 address: “0x01” address, interval: 2,
Packet 2 address: “0x02” address, interval: 4,
Packet 3 address: “0x04” address, interval: 8
Packet 4 address: “0x08” address, interval: 16,
Packet 5 address: “0x10” address is set to interval: 16.

Such setting examples of the sequencers 17 and 22 are merely examples, and need to be appropriately performed as necessary (when it is necessary to change the address control). The setting (rewriting) of the sequencers 17 and 22 is configured to be executed with the chips 11 and 12 in the sequencer setting mode.
In the present embodiment having such a configuration, the sequencers 17 and 22 for automatically controlling addresses in communication between the CPU evaluation chip (first chip) 11 and the peripheral evaluation chip (second chip) 12 are The two chips 11 and 12 are provided respectively. Therefore, when communication is performed between the two chips 11 and 12, since the address is automatically controlled by the sequencers 17 and 22 of the chips 11 and 12, the two chips 11 and 12 are connected. Address connection lines are not required.

  Therefore, although the configuration includes two semiconductor chips 11 and 12, the number of connection lines connecting the two semiconductor chips 11 and 12 can be reduced. As a result, the number of emulation pads arranged on the peripheral evaluation chip 12 can be reduced, and the chip size can be reduced accordingly. And in the case of the said structure, unlike the conventional structure (patent document 1), communication speed does not fall.

  In the above embodiment, in order to further reduce the number of connection lines 23 between the two chips 11 and 12, data transmission / reception having a function of transmitting and receiving data in a time division manner in communication between the two chips 11 and 12 It is preferable that the circuit of the part is provided in each of the two chips 11 and 12. With this configuration, 16 data lines can be further reduced from the above embodiment.

In the case of the above configuration, since data is transmitted and received in a time-sharing manner, the communication speed may be reduced as compared to the above embodiment, but the address is also configured to be transferred by parallel-serial conversion. Compared with the conventional configuration (Patent Document 1), the communication speed is sufficiently high.
In the above embodiment, the present invention is applied to the communication between the two chips 11 and 12 provided on the emulation board 2. However, the present invention is not limited to this, and the emulation board 2 has three or more chips. And may be configured to be applied to communication between these chips.

The block diagram of the emulation apparatus which shows one Example of this invention Diagram for explaining sequencer address / data control FIG. 1 equivalent diagram showing a conventional configuration

Explanation of symbols

In the drawings, 1 is an emulation device, 2 is an emulation board, 3 is an external emulation device, 11 is a CPU evaluation chip (first chip), 12 is a peripheral evaluation chip (second chip), 13 is a CPU, 14 is a ROM, 15 Is a RAM, 16 is an I / O, 17 is a sequencer (address control unit), 18 is a CPU, 19 is a ROM, 20 is a RAM, 21 is an I / O, 22 is a sequencer (address control unit), and 23 is a connection line. Show.

Claims (3)

An emulation device used during development using a single-chip microcomputer equipped with a CPU and peripheral circuits,
A first chip constituting a CPU function unit that emulates the function of the CPU;
A second chip that is a chip independent of the first chip and that constitutes a peripheral circuit function unit that emulates the function of the peripheral circuit,
An emulation apparatus, wherein an address control unit for automatically controlling an address in communication between the two chips is provided in each of the two chips.   The emulation device according to claim 1, wherein the peripheral circuit is an I / O circuit. 3. The emulation apparatus according to claim 1, wherein a data transmission / reception unit that transmits and receives data in a time division manner in communication between the two chips is provided in each of the two chips.

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