JPH0511833B2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention relates to a teletext CRI (Clock Run In) detection circuit for detecting the start timing of a clock signal for extracting a character signal from a television signal. It is.

"Conventional technology" CRI until the start of the conventional sampling clock signal
Detection is performed at 56Tc (Tc≒175n sec,
In other words, 3.58MHz of color burst is multiplied by 8/5.
The period of 5.73MHz is Tc).

"Problem to be solved by the invention" If the horizontal synchronization signal is set to 56Tc, the horizontal synchronization signal waveform will be distorted due to ghosts and other causes, resulting in CRI.
There was a problem that there was a delay and the text screen contained errors.

The purpose of the present invention is to detect the data itself and completely match the CRI.

"Means for Solving the Problems" The present invention has been made to achieve the above-mentioned objects, and includes a slicing circuit that slices a character video signal and converts it into binary data, and a slicing circuit that slices a character video signal and converts it into binary data. A CRI signal existing within a predetermined interval is detected from the value data and temporarily stored by a latch circuit, and the first half of this stored binary data and the first half of this binary data are An error signal generation circuit generates an error signal by performing an exclusive OR operation on each bit of the binary data in the latter half of a predetermined pulse delay using an exclusive OR circuit, and calculates the value of the error signal for each bit. It consists of an adder circuit that adds sequentially, and a comparison circuit that compares the added value of this adder circuit with a settable reference value.
When an output appears in this comparison circuit,
This is a CRI detection circuit for teletext broadcasting, which is characterized by detecting CRI.

``Operation'' The section from 56Tc to 72Tc, which is the CRI signal, from the horizontal synchronization signal of the character video signal is converted into binary data by the slice circuit, and this data is latched. At this time, data is detected separately into the first 8 bits and the latter 8 bits delayed by 8 pulses. Then, an exclusive OR is performed for each signal of the corresponding first half data and second half data in the error signal generation circuit. When the output of this exclusive OR is inverted, the error signal generating circuit has the maximum addition output when there is no error, and the addition output becomes 0 when the error is maximum. These error signals are added by an adder circuit and compared with a reference value. Then, when the signal from the adder circuit is received, it is detected that it is CRI.

“Embodiment” An embodiment of the present invention will be described below based on the drawings.

1 is the character video signal input terminal, and this input terminal 1
is coupled to a slice circuit 3 together with a slice level reference value signal input terminal 2, and this slice circuit 3 is connected to an error signal generation circuit 4 that takes an exclusive OR with a pulse with a predetermined delay, and sequentially adds the outputs of this exclusive OR. It is coupled to an adder circuit 5. The addition output side of this addition circuit 5 and the settable reference value input terminal 7 are coupled to a comparison circuit 8, to which a CRI output terminal 9 is coupled.

The slice circuit 3 is also coupled to a character data output terminal 11 via a character data delay circuit 10. Further, the adder circuit 5 and the comparator circuit 8 are connected to a clear signal input terminal 6 which uses a horizontal synchronizing signal as a clear signal.

In the above configuration, when the character video signal and the reference signal Ref as shown in FIG.
Converted to binary data with Low as 0. This binary data is sent to the error signal generation circuit 4 and temporarily stored in a latch circuit, and the CRI is detected within the 56 to 72 Tc interval from the horizontal synchronizing signal by the method described below.
Note that Tc has a period of 5.73MHz, which is 8/5 times the color burst frequency of 3.58MHz.

The latched binary data is divided into the first half 8 bits and the second half 8 bits delayed by 8 pulses, and the error signal generation circuit 4 performs an exclusive OR operation on each signal of the corresponding first half data and second half data. Take. When the output of this exclusive OR is inverted, the error signal generating circuit 4 outputs the maximum addition output when there is no error, and the addition output becomes 0 when the error is maximum. These error signals are added by an adding circuit 5 and compared with a reference value. Then, when the signal from the adder circuit 5 is received, it is detected that it is CRI.

In the above embodiment, since an exclusive OR circuit was used as the error signal generating circuit 4, its output was inverted and added. However, if an exclusive OR circuit is used as the error signal generating circuit 4, its output can be inverted and added. If the error is 0, the maximum output value will be obtained, and if the error is the maximum, the output will be 0.

"Effects of the Invention" Since the present invention is configured as described above, even if the horizontal synchronization signal is distorted due to ghosts, noise, etc., the CRI can be accurately detected and a character screen without errors can be obtained. Also, the CRI signal is detected from the binary data and temporarily stored by a latch circuit, and the first half binary data and the second half binary data with a predetermined pulse delay are bit-sequentially processed from the beginning by an exclusive OR circuit. Since the error signal is generated by calculating the exclusive OR of each error signal, the CRI can be detected with almost no time delay using a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a teletext CRI detection circuit according to the present invention, and FIG. 2 is a waveform diagram. DESCRIPTION OF SYMBOLS 1... Character video signal input terminal, 2... Reference signal input terminal, 3... Slice circuit, 4... Error signal generation circuit, 5... Addition circuit, 6... Clear signal input terminal, 7
...Reference signal input terminal, 8...Comparison circuit, 9...CRI output terminal, 10...Delay circuit, 11...Character data output terminal.

Claims (1)

[Claims] 1. A slicing circuit that slices a character video signal and converts it into binary data, and a latch circuit that detects a CRI signal that exists within a predetermined interval from the binary data converted by this slicing circuit and temporarily stores it. Then, the first half of the stored binary data and the second half of the binary data with a predetermined pulse delay from the first half of the binary data are sequentially exclusive bit by bit from the beginning using an exclusive OR circuit. An error signal generation circuit that generates an error signal by ORing a target, an adder circuit that sequentially adds the value of the error signal for each bit, and a comparison that compares the added value of this adder circuit with a settable reference value. for teletext broadcasting, characterized in that the CRI is detected when an output appears in the comparison circuit.
CRI detection circuit.