JPH05108034A - Multi-gradation liquid crystal display device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of a multi-gradation liquid crystal display device by making a gradation display with one source voltage. CONSTITUTION:The voltage from a driving power source 2 is applied to a data line 4 selected by a shift register 20 through an external signal line 1 and electric charges are accumulated in a capacity part 5 connected to the data line 4 through a switching element 3. The switching element 3 has its conduction time controlled according to a gradation signal D and the amount of the charges accumulated in the capacity part is varied according to the gradation signal to control a potential applied to liquid crystal through the data line 4 according to the gradation signal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a TFT for a liquid crystal display device or the like.
The present invention relates to a multi-gradation liquid crystal display device using an active matrix system, and particularly to a structure of a drive circuit for performing multi-gradation display.

[0002]

2. Description of the Related Art In a multi-gradation liquid crystal display device based on a TFT active matrix system, a system called a multi-level drive system has been proposed as a drive system for controlling a liquid crystal orientation to obtain a multi-gradation display. There is. An example of a multi-gradation liquid crystal display device of this system is shown in FIG.
310T)). This multi-gradation display liquid crystal display is provided with a data line 61 for controlling the orientation of the liquid crystal cell Yn, a plurality of switching elements 62 connected in parallel to the data line 61, and these switching elements 62, respectively. Multi-level power source 63,
A control circuit 64 for controlling the switching element 62,
Grayscale signal line 65 input to the control circuit 64 to select a multi-level power supply line connected to the data line.
It consists of and.

The multi-gradation liquid crystal display device has the gradation signal line 6
In response to the signal from the control circuit 5, the control circuit 64 selects one of the plurality of switching elements 62, makes the switching element conductive, and connects one power source voltage of the multi-level power source 63 to the data line 61. To be done. The multi-level power source 63 is composed of a number of power sources according to the required number of gradations, and has a configuration in which the voltage values applied to the respective switching elements are different.

[0004]

However, according to the above drive circuit, the multi-level power source 63 is proportional to the number of gradations.
In particular, the number of power sources required and the number of transistors of the switching element 62 connected to the data line 61 increase, and the circuit becomes complicated, resulting in an increase in size of the liquid crystal display device. In addition, even if the circuit is miniaturized, there is a certain limit, and therefore the increase in the number of power sources and the number of transistors in the switching element 62 limits the number of drive levels for multi-gradation. there were.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multi-grayscale liquid crystal display device which simplifies the circuit structure by enabling grayscale display with one power supply voltage. To do.

[0006]

In order to solve the problems of the above conventional example, a multi-tone liquid crystal display device of the present invention is characterized by having the following constitution. A plurality of data lines are provided to control the alignment of the liquid crystal. A capacitance portion is provided, one end of which is connected to the data line and the other end of which is grounded. An external signal line to which a voltage from the driving power source is applied is provided. A switching element is interposed between the external signal line and each data line. A gradation signal line for outputting a gradation signal of liquid crystal connected to the data line is provided. A selection means for selecting each data line is provided. A control circuit is provided for selecting the data line by the selecting means and controlling the conduction time of each of the switching elements in response to the gradation signal.

[0007]

According to the present invention, the voltage from the driving power source is applied to the data line selected by the selecting means via the external signal line, and the electric charge is applied to the capacitance section connected to the data line via the switching element. Accumulated. Since the conduction time of this switching element is controlled according to the gradation signal, the amount of charge accumulated in the capacitance portion changes according to the gradation signal, and the potential applied to the liquid crystal via the data line is changed. It can be controlled according to the gradation signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the multi-tone liquid crystal display device of the present invention will be described with reference to FIGS. Figure 1
FIG. 3 is a circuit diagram of 3 bits of a multi-tone liquid crystal display device. An external signal line 1 that is common to the liquid crystal of each bit of the multi-tone liquid crystal display device is provided, and a constant voltage from a drive power supply 2 is applied to one end of the external signal line 1. A data line 4 is connected to the external signal line 1 with a complementary switch 3 interposed for each bit. A liquid crystal cell Yn is connected to the end of the data line 4, and the orientation of the liquid crystal cell is controlled by the voltage applied to the data line 4. The data line 4 is provided with a capacitance section 5 having one end connected to the data line 4 and the other end grounded.

That is, when the complementary switch 3 is turned on, a voltage from the driving power supply 2 is applied to the data line 4 via the external signal line 1, and the complementary switch 3 is connected to the capacitor section 5 connected to the data line 4. The electric charge is accumulated via. Therefore, if the conduction time t of the complementary switch 3 is controlled, the amount of accumulated charges can be changed to make the potential of the data line 4 variable. For example, as shown in FIG.
When t8 is set in eight steps, eight levels of potentials V1 to V8 corresponding to it can be obtained.

Each of the complementary switches 3 is controlled by the clocked inverter circuit 10 to be conductive or non-conductive. That is, the output of the clocked inverter circuit 10 is connected to the p side of the complementary switch 3 and also connected to the n side of the complementary switch 3 via the inverter 6. The clocked inverter circuit 10 has a Vdd power supply line 12 for outputting H level to the output line 11 of the clocked inverter circuit 10 which is common to each bit.
Vss power supply line 13 for outputting L level to the output line 11 of the clocked inverter circuit 10 which is common to each bit
And the Vdd power line 12 and the Vss power line 13 for each bit
And p-type transistors 14 and 1 connected in series between
5 and n-type transistors 16 and 17, and an inverter 18 whose output side is connected to the gate part of the p-type transistor 14.
It consists of and. The transistor is of p-type-p-type-n-type from Vdd power line 12 to Vss power line 13.
They are connected in series so as to be n-type.

The gate portions of the p-type transistor 15 and the n-type transistor 16 are connected to a gradation signal line D for outputting the gradation signal of the liquid crystal cell Yn connected to the data line 4. The gradation signal line D is common to each bit. The gate portion of the n-type transistor 17 for each bit has output terminals Q1, Q2, Q3 ... Of the shift register 20 serving as selection means for selecting the data lines 4.
Respectively connected to. In addition, the shift register 20
Output terminals Q1, Q2, Q3 ... Are also connected to the input side of the inverter 18.

Driving of the multi-tone liquid crystal display device for 3 bits will be described with reference to the timing chart of FIG. The clock pulse CLK as shown in FIG. 3 is input to the shift register 20, and the output terminals Q1, Q2,
Pulses q1, q2, q3 having a pulse width Ts are sequentially shifted and output from Q3, and the data line 4 is sequentially selected. During the Ts period in which one data line 4 is selected, the clocked inverter 10 of the selected bit can operate. The gradation signal line D has a pulse width Ts of the pulse.
In, a signal that is at the H level is output during the period corresponding to the grayscale of each liquid crystal cell Yn (for example, the pulse width Tt for the first bit).

When the output terminal Q is at the H level, the clocked inverter 10 is driven so that the signal appearing on the output line 11 with respect to the signal on the gradation signal line D performs the operation of the inverter, and the output terminal Q is driven. At the L level, the output line 11 side is driven to have a high impedance.
Therefore, the clocked inverter 10 can operate during the period when the output terminal Q1 is at the H level, and the n-type transistor 16 and the n-type transistor 17 are conductive only when the gradation signal line D is at the H level during this period (period a). Then, the L level signal is output to the output line 11 and the complementary switch 3
Is made conductive. In other periods, the output line 11 of the clocked inverter 10 is held at H level or high impedance, and the complementary switch 3 is in non-conduction state. When the complementary switch 3 is turned on, a voltage from the driving power supply 2 is applied from the external signal line 1 and electric charge is accumulated in the capacitor 5. Therefore, the gradation signal line D
Is changed to the H level to change the time for which the complementary switch 3 is in the conductive state, and
The charge time is adjusted to control the potential of the data line 4.

FIG. 4 shows another embodiment of the present invention.
Portions having the same configurations as those of the embodiment of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted, and different configurations will be mainly described. In this embodiment, the data line 4 corresponding to n bits is connected to the output Q of one stage of the shift register 20. That is, the output Q1 of the shift register
Are connected to the gates of the p-type transistors 14 of the n clocked inverters 10 via the inverter 18, and to the gates of the n-type transistors 17. Further, n gradation signal lines Dn are provided, and each of these gradation signal lines Dn is connected to the data line 4 of each bit of n bits. That is, each grayscale signal corresponds to the p-type transistor 1 of the clocked inverter 10 for each bit.
5 and the gate of the n-type transistor 16.

Driving of the multi-tone liquid crystal display device according to this embodiment will be described with reference to the timing chart of FIG. A clock pulse CLK as shown in FIG. 5 is input to the shift register 20, and pulses q1, q2, ... With a pulse width Ts are sequentially shifted and output from the output terminals Q1, Q2 ,. 4 groups of data lines to be selected are sequentially selected. That is, in the first stage of the shift register 20, the data line 4 including the n data lines 4 is formed.
During the Ts period in which the group (connected to the liquid crystal cells Y11 to Y1n) is selected, the clocked inverter 10 in the selected n bits can be operated. Each gradation signal line Dn has a period corresponding to the gradation of each liquid crystal cell Y11 to Y1n in the pulse width Ts of the pulse (for example,
The first bit outputs a signal having an H level with a pulse width Tt).

Therefore, similarly to the first embodiment, the clocked inverter 10 has the output terminal Q1 at the H level and the gradation signal line Dn at the H level (the output terminal Q1 of the first stage of the shift register 20 is In the period of H level, period a,
The n-type transistor 16 and the n-type transistor 1 only during the period b) when the second-stage output terminal Q2 is at the H level.
7 becomes conductive, an L level signal is output to the output line 11, and the complementary switch 3 is made conductive. In other periods, the output line 11 of the clocked inverter 10
Is held at the H level, and the complementary switch 3 is in the non-conducting state. When the complementary switch 3 becomes conductive,
The driving power supply 2 is applied from the external signal line 1 and electric charges are accumulated in the capacitance section 5. Therefore, the complementary switch 3 is changed by changing the period during which each gradation signal line Dn is at the H level.
Is changed to a conductive state and the charging time of the capacitor 5 is adjusted to simultaneously control the potentials of the data lines 4 for n bits.

According to the above embodiment, the shift register 20
In a period in which the output of each stage is at the H level, n bits can be driven by parallel processing, so that the clock frequency can be lowered, and when the clock frequency is the same, display processing of each bit is performed. The speed can be increased.

The circuits of the two embodiments described above can be formed as an LSI chip as a driver circuit. In addition, a polysilicon TFT can be used to form a monolithic circuit on the liquid crystal substrate.

[0019]

As described above, according to the present invention, the multi-level potential required for the gray scale of the multi-gradation liquid crystal display device is controlled by controlling the conduction time of the switching element, so that one power source can be connected to the capacitor section. It is obtained by changing the amount of charge accumulated in the. Therefore, the number of levels in the multi-level drive system can be increased without increasing the number of power sources or the number of transistors, and the size of the multi-tone liquid crystal display device can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of 3 bits of a multi-tone liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between conduction time and applied voltage of a complementary switch in an example.

FIG. 3 is a timing chart when driving the circuit of FIG.

FIG. 4 is a circuit diagram for 3 bits of a multi-tone liquid crystal display device according to another embodiment of the present invention.

5 is a timing chart when driving the circuit of FIG. 4. FIG.

FIG. 6 is a 1-bit circuit diagram of a conventional multi-gradation liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... External signal line, 2 ... Driving power supply, 3 ... Complementary switch, 4 ... Data signal line, 5 ... Capacitance part, 10 ... Clocked inverter, 20 ... Shift register, D ... Gradation signal line, Y ... Liquid crystal cell

Claims (1)

[Claims] 1. A plurality of data lines for controlling the orientation of liquid crystals, a capacitor section having one end connected to the data line and the other end grounded, an external signal line to which a voltage from a driving power source is applied, and the external signal line. A switching element interposed between the signal line and each data line, a gradation signal line for outputting a gradation signal of liquid crystal connected to the data line, and a selection means for selecting each data line,
A multi-gradation liquid crystal display device comprising: a control circuit that selects a data line by the selection means and controls the conduction time of each of the switching elements in response to the gradation signal.