JP2003044020A - Decoder circuit, decoder circuit driving method, and liquid crystal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a decoder not much increased in a circuit scale even if data bits are increased in number, in a decoder used for a data driver or the like of a liquid crystal display device. SOLUTION: When N pieces of binary data are converted to 2N pieces of data, electric charges stored in N pieces of capacitors having a capacitance ratio of 1, 2, 4, 8,..., 2(N<-1)> are selectively outputted according to the N pieces of the binary data. Since there are 2N possible combinations for selections of capacitors and there are also 2N possible combinations of total quantities of electric charges stored in the selected capacitors, N pieces of the binary data can be converted to 2N pieces of data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit for converting ^N binary data into 2 ^N data. In particular, it relates to the configuration of a data driver of a liquid crystal display device.

[0002]

2. Description of the Related Art As a conventional application example of a decoder circuit for converting ^N binary data into 2 ^N data, "1.
991 International Display Research Conference, p. 111-114, Okada and others ”. FIG. 2 shows an example of a typical decoder circuit for converting 3 inputs to 8 outputs. In the figure, DATA1- is DAT
This is the inverted data of A1 +, and the same applies to DATA2 and DATA3. Since there are eight types of combinations of three binary input data, one of the eight AND gates in the decoder section becomes the selection level and the switch in the buffer section is turned on.
Let N. Therefore, the output terminal VOUT has eight voltages V
Any one of 1 to V8 will be output.

[0003]

However, the above-mentioned prior art has the following problems.

Generally, when an image signal is formed by digital input like a data driver of a full-color liquid crystal display device, a multi-gradation signal of 7 bits or 8 bits is required. However, if an 8-bit input decoder is constructed by the method of FIG. 2, the number of AND gates is 256.
You need one. This leads to a drastic increase in the number of elements and the circuit area, resulting in an extremely expensive circuit, and also in the size and weight of the entire display device.

The decoder circuit of the present invention solves such a problem, and an object thereof is to realize a decoder circuit whose circuit scale does not increase much even if the number of input bits increases.

[0006]

The decoder circuit of the present invention has a capacitance ratio of 1, 2, 4, 8. ． ． It is characterized in that it has N capacitors of 2 ^(N-1) and N switches, and the gates of the N switches are respectively connected to N binary data.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment will be described below with reference to the drawings. FIG. 1 is an example of a circuit diagram of a decoder circuit of the present invention. In this figure, the sizes of the capacitors C1, C2, and C3 are C1,
Given that C2 and C3 and the load capacitance connected to the output terminal OUT are C0, this decoder circuit changes the input signal of 3 bits from 0 volt to VDD. (C1 + C2 + C3) /
It can be converted to a voltage up to (C0 + C1 + C2 + C3) volts. If C1 = 4Cz, C2 = 2C
If z and C3 = Cz, then 0 volt to VDD.7Cz
It can be converted into 8 divided voltages up to / (C0 + 7Cz) volts.

Next, the operation of this circuit will be described.
First, when the output reset terminal RSET goes high, the output terminal OUT becomes 0V. At this time, if the write terminal SET is set to the low level, all the switches are turned off. Next, set RSET to low level, and S
Set ET to high level. Then, the transistor whose output terminal is reset to 0V is in the OFF state, and among the three switches, the one in which the + side of DATA is high level and the one in which the − side is low level are in ON state. Therefore, by combining ON and OFF of the three switches, eight kinds of voltages are given to the output terminal OUT. here,
Since the three switches are analog switches, V
By changing DD, an arbitrary output voltage range can be selected, but these switches can be digital type.

FIG. 3 shows an example in which the decoder circuit of the present invention is applied to a liquid crystal display device. In general, liquid crystal display devices other than segment display use the dot matrix method,
The pixel matrix section includes a data driver section and a scan driver section for driving the pixel matrix section.

In the case of the TFT method in which a thin film transistor (hereinafter abbreviated as TFT) is arranged in each pixel, the pixel matrix portion is composed of signal lines 33 and scanning lines 34 which are orthogonal to each other, and TFTs 31 and liquid crystals 32 which are arranged at their intersections. The output of each data driver is connected to the signal line 33, and the output of the scan driver is connected to the scan line 34. When a selection pulse is applied to the scan line, the TFT becomes conductive and the data of the signal line is written in the liquid crystal. The data driver unit includes a shift register, data lines DATA1 to DATA3, sampling latches A1 to B3, hold latches B1 to B3 and a decoder circuit.
The decoder circuit shown in FIG. 1 is used.

Next, the operation of the data driver section will be described. The shift register shifts the start pulse SP one stage at a time to the subsequent stage in synchronization with the internal clock. The sampling latches A1, A2, and A3 are two of the data lines DATA1, DATA2, and DATA3, respectively.
Value data is fetched in synchronization with the output of the shift register. After all the sampling is completed, the latch pulse LP transfers the data in the sampling latches A1, A2, and A3 to the hold latches B1, B2, and B3, respectively. The decoder section includes hold latches B1, B2,
Based on the data of B3 and its inverted data, the charge accumulated in the capacitor is discharged to the signal line as described above. In general, the variation in the wiring capacitance of the signal lines of the liquid crystal display device is extremely small, and thus accurate gradation display can be performed by this method.

In this figure, a thin film transistor (hereinafter referred to as a TFT
Is shown in each pixel, but a non-linear element such as a thin film diode is used instead of the TFT, and a simple matrix liquid crystal display device without a switching element is also applicable. .
Further, in the case of a liquid crystal display device using a TFT having a relatively high mobility such as polycrystalline silicon, it is possible to fabricate the scan driver and the data driver on the same substrate by the TFT. In particular, TFTs have a large variation in characteristics as compared with transistors on a semiconductor substrate, and it is extremely difficult to configure an analog line sequential data driver using an analog buffer circuit. Therefore, a simple circuit configuration as in the present invention is used. The method by which a multi-bit digital line sequential data driver can be constructed is very practical.

[0013]

As described above, in the decoder circuit of the present invention, the circuit scale does not increase so much even if the number of bits of the input signal increases, so that a multi-bit decoder can be realized in a small area and at low cost. In particular, since the data driver of the liquid crystal display device can be interfaced with only digital signals, the scale of the external circuit is reduced in the display for computers and aircraft, and it is less susceptible to noise, and the screen is uniform. The property is improved. Also,
Since a digital line-sequential data driver using TFTs can be easily constructed, an ultra-small and highly reliable liquid crystal display device can be realized.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a decoder.

FIG. 2 is an equivalent circuit diagram of a conventional decoder.

FIG. 3 is an equivalent circuit diagram of a liquid crystal display device.

[Explanation of symbols]

31 TFT 32 liquid crystal 33 signal line 34 scan lines

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[Procedure amendment]

[Submission date] June 12, 2002 (2002.6.1)
2)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Decoder circuit, method of driving decoder circuit, and liquid crystal device

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

A first decoder circuit of the present invention comprises a plurality of first switches controlled according to binary data and a plurality of switches provided corresponding to the plurality of switches. A capacitance, and by turning on the plurality of first switches according to the binary data, an output obtained by converting the charges accumulated in the plurality of capacitors into a voltage,
It is characterized by giving to an output terminal. A second decoder circuit of the present invention is a decoder circuit including a plurality of first switches controlled according to binary data and a plurality of capacitors provided corresponding to the plurality of switches. hand,
The capacity ratio of the plurality of capacities is a ratio of a multiplier of 2,
By turning on the plurality of first switches according to the binary data, an output obtained by converting the charges accumulated in the plurality of capacitors into a voltage is given to an output terminal. . The third decoder circuit of the present invention has 2
A plurality of first switches that are controlled according to the value data, a plurality of capacitors provided corresponding to the plurality of switches, and a plurality of capacitors provided corresponding to the plurality of capacitors and connected to the power supply potential. A plurality of second switches to be controlled, the plurality of second switches are turned on, the power supply potential and the plurality of capacitors are connected, and then the second switches are turned off, Turning on the plurality of first switches in accordance with binary data to give an output obtained by converting the charges into a voltage to an output terminal,
Is characterized by. The above decoder circuit preferably further includes a transistor that resets the potential of the output terminal to a predetermined potential when the plurality of capacitors and the output terminal are not connected. In the above decoder circuit, it is preferable that the second switch is in an ON state when the output terminal and the capacitor are not connected. A liquid crystal device of the present invention includes a data driver unit having the above decoder circuit, and a pixel matrix unit having signal lines and scanning lines intersecting with each other, and the signal lines are output from the output terminals. The voltage is supplied as a signal. A driving method of a decoder circuit of the present invention corresponds to a plurality of first switches controlled according to binary data, a plurality of capacitors provided corresponding to the plurality of switches, and a plurality of capacitors. And a plurality of second switches for controlling connection with a power supply potential, the method comprising: driving the plurality of second switches in an ON state to supply the power supply potential and the plurality of capacitors. And a second step of connecting the second switch to an off state, and turning on the plurality of first switches according to the binary data to convert the electric charge into a voltage. And a third step of resetting the potential of the output terminal to a predetermined potential when the output terminal and the plurality of capacitors are not connected. It is. In the above method of driving the decoder circuit, it is preferable that the first step and the third step be performed at the same time.

Continued front page    F term (reference) 2H093 NA16 NA43 NC16 NC22 NC26                       NC34 ND49                 5C006 AA22 BB12 BB16 BC12 BC20                       BF03 BF04 BF24 BF26 BF37                       FA43 FA56 GA03                 5C080 AA10 BB05 DD22 EE28 FF09                       GG11 JJ02 JJ03

Claims (2)

[Claims] 1. A decoder circuit for converting ^N binary data into 2 ^N data, wherein a capacitance ratio is 1, 2, 4,
8. ． ． A decoder circuit comprising N capacitors of 2 ^(N-1) and N switches, wherein the gates of the N switches are respectively connected to the N binary data. . 2. A dot matrix type liquid crystal display device driven by a data driver and a scan driver, wherein the data driver includes an N-bit shift register, N data lines, and M × N-bit two-stage latches.
The output of the shift register is connected to the gate of an N-bit first latch, and the input portion of the first latch is connected to the N data lines. The output section is connected to the N-bit second latch of the next stage, and the output of the second latch is connected to the N switches and capacitors, and the ratio of the sizes of the N capacitors is determined. Is 1, 2, 4, 8. ． ． A display device characterized in that it is 2 ^(N-1) .