JP4339828B2 - Semiconductor device - Google Patents

Description

The present invention relates to a pulse output circuit, a shift register, and a display device. Note that in this specification, a display device includes a liquid crystal display device using a liquid crystal element for a pixel and a self-light emitting display device using a self-light emitting element such as an electroluminescence (EL) element. The driving circuit of the display device refers to a circuit that inputs a video signal to a pixel arranged in the display device and performs processing for displaying a video, a pulse output circuit including a shift register, an inverter, and the like, An amplifier circuit including an amplifier is included.

  In recent years, a display device in which a semiconductor thin film is formed over an insulator such as a glass substrate, in particular, an active matrix display device using a thin film transistor (hereinafter referred to as TFT) has been used and spread in many products. An active matrix display device using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and displays the image by controlling the charge of each pixel by the TFT arranged in each pixel. It is carried out.

  Furthermore, as a recent technology, in addition to the pixel TFT that constitutes the pixel, a technology related to a polysilicon TFT that simultaneously forms a drive circuit on a substrate by using a TFT in the peripheral region of the pixel portion has been developed. As a result, display devices have become an indispensable device for display units and the like of mobile information terminals, which have greatly contributed to lower power consumption, and whose application fields have been remarkably expanding in recent years.

  In general, a CMOS circuit in which an N-channel TFT and a P-channel TFT are combined is generally used as a circuit constituting a driving circuit of a display device. As an example of this CMOS circuit, a shift register is taken as an example. FIG. 11A illustrates an example of a shift register, and a portion surrounded by a dotted frame 1100 is a circuit that outputs a pulse for one stage. FIG. 11A shows three stages extracted. A circuit for one stage includes clocked inverters 1101 and 1103 and an inverter 1102. FIG. 11B shows a detailed circuit structure. In FIG. 11B, a clocked inverter 1101 is constituted by TFTs 1104 to 1107, an inverter 1102 is constituted by TFTs 1108 and 1109, and a clocked inverter 1103 is constituted by TFTs 1110 to 1113.

  A TFT constituting a circuit has three electrodes, a gate electrode, a source electrode, and a drain electrode, but the source region and the drain region cannot be distinguished from each other due to the structure of the TFT. In a general CMOS circuit, for an N-channel TFT, the lower potential of the source region and the drain region is used as a source electrode, and the higher potential is used as a drain electrode, and for the P-channel TFT, the higher potential is used. Are often used as the source electrode and the one with the lower potential as the drain electrode. However, in describing the connection of the TFT in this specification, in order to avoid confusion between the source electrode and the drain electrode, either one is used as the first electrode. The other is shown as a second electrode.

  The operation of the circuit will be described. As for the operation of the TFT, a potential is applied to the gate electrode to form a channel between the impurity regions, and the conductive state is ON. The channel in the impurity region disappears and the non-conductive state is OFF. write.

Reference is made to the timing charts shown in FIGS. 11A and 11B and FIG. A clock signal (hereinafter referred to as CK) and a clock inversion signal (hereinafter referred to as CKB) are input to the TFTs 1107 and 1104, respectively. A start pulse (hereinafter referred to as SP) is input to the TFTs 1105 and 1106. When CK is at H level, CKB is at L level, and SP is at H level, the TFTs 1106 and 1107 are turned on, and the L level is output and input to the inverter constituted by the TFTs 1108 and 1109, inverted, and output node (SRout1 ) Is output at H level. Thereafter, when SP is at the H level and CK is at the L level and CKB is at the H level, the holding operation is performed in the loop constituted by the inverter 1102 and the clocked inverter 1103. Therefore, the H level continues to be output to the output node. Next, when CK becomes H level and CKB becomes L level, the clocked inverter 1101 performs the writing operation again. At this time, since the SP is already at the L level, the L level is output to the output node. Thereafter, when CK becomes L level and CKB becomes H level, the holding operation is performed again, and the L level of the output node at this time is held in the loop constituted by the inverter 1102 and the clocked inverter 1103.

  The above is the operation for one stage. In the next stage, the connections of CK and CKB are reversed, and the same operation is performed in the state where the polarity of the clock signal is reversed. This is repeated alternately, and thereafter, similarly, sampling pulses are sequentially output as shown in FIG.

As a feature of the CMOS circuit, current flows only at the moment when the logic changes (from H level to L level or from L level to H level), and no current flows while holding a certain logic (actually, it is very small) Because there is a leakage current), the current consumption in the entire circuit can be kept low.

  By the way, the demand for display devices using liquid crystals and self-luminous elements has been increasing rapidly as mobile electronic devices have become smaller and lighter. It is difficult to keep it low. It is easily predicted that future demand will increase more rapidly, and it is therefore desirable to be able to supply display devices at a lower cost.

  As a method of manufacturing a driver circuit on an insulator, a method of using a plurality of photomasks to expose and etch patterns of active layers, wirings, etc. is generally used. Since the number of processes directly affects the manufacturing cost, it is ideal that the manufacturing can be performed with as few processes as possible. Therefore, if a driving circuit that has been configured by a conventional CMOS circuit can be configured by using only an N-channel type or P-channel type TFT, a part of the ion doping process is omitted. In addition, the number of photomasks can be reduced.

  FIG. 9A shows an example of a commonly used CMOS inverter (I) and inverters (II) and (III) configured using TFTs having only one polarity. (II) is an inverter using a TFT as a load, and (III) is an inverter using a resistor as a load. Each operation will be described below.

  FIG. 9B shows a waveform of a signal input to the inverter. Here, the input signal amplitude is L level / H level = VSS / VDD (VSS <VDD). Here, VSS = 0 [V] is considered.

  The circuit operation will be described. For clarity and simplicity of explanation, the threshold voltage of the N-channel TFT constituting the circuit is assumed to be uniform (VthN) assuming that there is no variation. Similarly, the P-channel TFT is set to be uniform (VthP).

  When a signal as shown in FIG. 9B is input to the CMOS inverter, when the potential of the input signal is H level, the P-channel TFT 901 is turned off and the N-channel TFT 902 is turned on, whereby the potential of the output node Becomes L level. On the other hand, when the potential of the input signal is L level, the P-channel TFT 901 is turned ON and the N-channel TFT 902 is turned OFF, so that the potential of the output node becomes H level (FIG. 9C).

  Next, the operation of the inverter (II) using the TFT as a load will be described. Consider the case where a signal as shown in FIG. First, when the input signal is at L level, the N-channel TFT 904 is turned OFF. On the other hand, since the load TFT 903 always operates in saturation, the potential of the output node is raised in the H level direction. On the other hand, when the input signal is at the H level, the N-channel TFT 904 is turned on. Here, by making the current capability of the N-channel TFT 904 sufficiently higher than the current capability of the load TFT 903, the potential of the output node is lowered in the L level direction.

  Similarly, for the inverter (III) using a resistor as a load, the ON resistance value of the N-channel TFT 906 is sufficiently lower than the resistance value of the load resistor 905 so that the input signal is at the H level. When the N-channel TFT 906 is turned on, the output node is pulled down in the L level direction. When the input signal is at the L level, the N-channel TFT 906 is turned off and the output node is pulled up in the H level direction.

  However, when using an inverter using a TFT as a load or an inverter using a resistor as a load, there are the following problems. FIG. 9D shows an output waveform of an inverter using a TFT as a load. When the output is at an H level, the potential is lower than VDD by the amount indicated by 907. In the load TFT 903, assuming that the terminal on the output node side is the source and the terminal on the power supply VDD side is the drain, the gate electrode and the drain region are connected, so the potential of the gate electrode at this time is VDD. Further, since the condition for turning on the load TFT is (the gate-source voltage of the TFT 903> VthN), the potential of the output node rises only to (VDD−VthN) at the maximum. That is, 907 is equal to VthN. Further, depending on the ratio of the current capability between the load TFT 903 and the N-channel TFT 904, when the output potential is L level, the potential becomes higher than VSS by the amount indicated by 908. In order to make this sufficiently close to VSS, it is necessary to sufficiently increase the current capability of the N-channel TFT 904 with respect to the load TFT 903. Similarly, FIG. 9E shows an output waveform of an inverter using a resistor as a load. Depending on the ratio between the resistance value of the load resistor 905 and the ON resistance of the N-channel TFT 906, the waveform indicated by 909 can be obtained. Only the potential becomes higher. In other words, when an inverter configured using only one polarity TFT shown here is used, the amplitude of the output signal is attenuated with respect to the amplitude of the input signal.

  The present invention has been made in view of the problems as described above, and by constructing a circuit using TFTs having only one polarity, the manufacturing process can be reduced at a low cost, and the amplitude can be reduced. An object of the present invention is to provide a pulse output circuit and a shift register which can obtain an output without attenuation.

  In the inverter using the TFT shown in FIG. 9 (A) (II) as a load, a condition for the output signal amplitude to normally take L level / H level = VSS / VDD is considered. First, in the circuit as shown in FIG. 10A, when the potential of the output signal becomes L level, the resistance value between the power supply VDD and the output node (Out) is sufficient to bring the potential sufficiently close to VSS. On the other hand, the resistance value between the power source VSS and the output node (Out) only needs to be sufficiently low. That is, it is only necessary that the N-channel TFT 1001 is OFF while the N-channel TFT 1002 is ON.

Second, when the potential of the output signal becomes H level, in order for the potential to be equal to VDD, the absolute value of the gate-source voltage of the N-channel TFT 1001 always exceeds VthN, and the TFT 1002 is surely turned off. Just do it. That is, in order to satisfy the condition that the H level of the output node is VDD, the potential of the gate electrode of the N-channel TFT 1001 needs to be higher than (VDD + VthN).

  Therefore, the following measures are taken in the present invention. As shown in FIG. 10B, a capacitor 1003 is provided between the gate and source of an N-channel TFT 1001. When the potential of the output node is raised when the gate electrode of the N-channel TFT 1001 is in a floating state with a certain potential, the capacitive coupling by the capacitor 1003 causes the increase in the potential of the output node to increase the potential of the N-channel TFT 1001. The potential of the gate electrode is also raised. By utilizing this effect, the potential of the gate electrode of the N-channel TFT 1001 can be made higher than VDD (more precisely, higher than (VDD + VthN)). Therefore, the potential of the output node can be sufficiently raised to VDD.

  Note that as the capacitor 1003 shown in FIG. 10B, a parasitic capacitance between the gate and the source of the TFT 1001 may be used, or a capacitor portion may be actually manufactured. In the case where the capacitor portion is manufactured independently, it is simple and desirable that the insulating layer is sandwiched between any two of the active layer material, the gate material, and the wiring material. Alternatively, other materials may be used. At this time, when an active layer is used, it is desirable to reduce the resistance by adding impurities into the active layer.

  The configuration of the present invention is shown below.

The pulse output circuit of the present invention is
A pulse output circuit having a first transistor to a third transistor, a first signal input unit to a third signal input unit, a signal output unit, and a power source, wherein the first to third transistors Are of the same conductivity type,
A gate electrode of the first transistor is electrically connected to the first signal input unit;
A first electrode of the first transistor is electrically connected to the second signal input unit;
A second electrode of the first transistor is electrically connected to a gate electrode of the second transistor;
A first electrode of the second transistor is electrically connected to the third signal input unit;
A second electrode of the second transistor is electrically connected to the signal output unit;
A gate electrode of the third transistor is electrically connected to the first signal input unit;
A first electrode of the third transistor is electrically connected to the power source;
A second electrode of the third transistor is electrically connected to the signal output unit;
A capacitor means is provided between the gate electrode and the first electrode of the second transistor or between the gate electrode and the second electrode of the second transistor.

The pulse output circuit of the present invention is
A pulse output circuit having a first transistor to a third transistor, a first signal input unit to a fourth signal input unit, a signal output unit, a power source, and an input switching circuit,
The first to third transistors are all of the same conductivity type,
A gate electrode of the first transistor is electrically connected to the first signal input unit;
A first electrode of the first transistor is electrically connected to the input switching circuit;
The input switching circuit is electrically connected to the second signal input unit and the third signal input unit,
A second electrode of the first transistor is electrically connected to a gate electrode of the second transistor;
A first electrode of the second transistor is electrically connected to the fourth signal input unit;
A second electrode of the second transistor is electrically connected to the signal output unit;
A gate electrode of the third transistor is electrically connected to the first signal input unit;
A first electrode of the third transistor is electrically connected to the power source;
A second electrode of the third transistor is electrically connected to the signal output unit;
A capacitor means is provided between the gate electrode and the first electrode of the second transistor or between the gate electrode and the second electrode of the second transistor.

The pulse output circuit of the present invention is
A pulse output circuit having a first transistor to a third transistor, a first signal input unit to a fourth signal input unit, a signal output unit, a power source, and an input switching circuit,
The first to third transistors are all of the same conductivity type,
A gate electrode of the first transistor is electrically connected to the first signal input unit;
A first electrode of the first transistor is electrically connected to the input switching circuit;
The input switching circuit is electrically connected to the second signal input unit and the third signal input unit,
A second electrode of the first transistor is electrically connected to a gate electrode of the second transistor;
A first electrode of the second transistor is electrically connected to the fourth signal input unit;
A second electrode of the second transistor is electrically connected to the signal output unit;
A gate electrode of the third transistor is electrically connected to the first signal input unit;
A first electrode of the third transistor is electrically connected to the power source;
A second electrode of the third transistor is electrically connected to the signal output unit;
Capacitive means between the gate electrode and the first electrode of the second transistor, or between the gate electrode and the second electrode of the second transistor,
When the input switching circuit is in the first state, the first electrode of the first transistor is conductive with the second signal input unit and is non-conductive with the third signal input unit,
When the input switching circuit is in the second state, the first electrode of the first transistor is electrically connected to the third signal input portion and is not electrically connected to the second signal input portion. It is a feature.

In the pulse output circuit of the present invention,
The input switching circuit is
A fourth transistor, a fifth transistor, a fifth signal input unit, and a sixth signal input unit;
The fourth transistor and the fifth transistor are both of the same conductivity type as the first transistor to the third transistor,
A gate electrode of the fourth transistor is electrically connected to the fifth signal input unit;
A first electrode of the fourth transistor is electrically connected to the second signal input unit;
A second electrode of the fourth transistor is electrically connected to a first electrode of the first transistor;
A gate electrode of the fifth transistor is electrically connected to the sixth signal input portion;
A first electrode of the fifth transistor is electrically connected to the third signal input unit;
A second electrode of the fifth transistor is electrically connected to a first electrode of the first transistor;
When the input switching signal is input to the fifth signal input unit and the input switching inversion signal is input to the sixth signal input unit, the fourth transistor becomes conductive, and the fifth signal input unit The transistor becomes non-conductive,
When the polarity of the input switching signal is inverted and the polarity of the input switching inverted signal is inverted, the fourth transistor is turned off and the fifth transistor is turned on.

In the pulse output circuit of the present invention,
The capacitor means may be formed between the gate electrode of the second transistor and the active layer of the second transistor, or may be made of an active layer material, a material forming the gate electrode, or a wiring material. It may be formed between any two materials.

Using the pulse output circuit of the present invention,
A shift register is provided that sequentially outputs sampling pulses in accordance with the first to fourth clock signals and a start pulse.

The shift register of the present invention is
A first clock signal line to a fourth clock signal line, and a start pulse input line;
In the pulse output circuit of the 4n-3rd stage (n is a natural number, 1 ≦ n),
The first signal input unit is electrically connected to the first clock signal line,
The second signal input unit is electrically connected to the start pulse input line when n = 1, and when n ≠ 1, the signal output of the pulse output circuit at the 4 (n−1) th stage. Electrically connected to the
The third signal input unit is electrically connected to the third clock signal line;
In the pulse output circuit at the 4n-2 stage,
The first signal input unit is electrically connected to the second clock signal line,
The second signal input unit is electrically connected to the previous signal output unit of the 4n-3 stage first pulse output circuit,
The third signal input unit is electrically connected to the fourth clock signal line;
In the pulse output circuit at the 4n-1 stage,
The first signal input unit is electrically connected to the third clock signal line,
The second signal input unit is electrically connected to the first signal output unit of the 4n-2 stage first pulse output circuit,
The third signal input unit is electrically connected to the first clock signal line;
In the 4n stage pulse output circuit,
The first signal input unit is electrically connected to the fourth clock signal line,
The second signal input unit is electrically connected to the previous signal output unit of the 4n-1 stage previous pulse output circuit,
The third signal input unit is electrically connected to the second clock signal line;
A sampling pulse is sequentially output in accordance with the first to fourth clock signals and the start pulse.

The shift register of the present invention is
A first clock signal line to a fourth clock signal line, and a start pulse input line;
In the pulse output circuit of the 4n-3rd stage (n is a natural number, 1 ≦ n),
The first signal input unit is electrically connected to the first clock signal line,
The second signal input unit is electrically connected to the start pulse input line when n = 1, and when n ≠ 1, the signal output of the pulse output circuit at the 4 (n−1) th stage. Electrically connected to the
The third signal input unit is electrically connected to either the start pulse input line or the signal output unit of the 4n-2 stage pulse output circuit,
The fourth signal input unit is electrically connected to the third clock signal line;
In the pulse output circuit at the 4n-2 stage,
The first signal input unit is electrically connected to the second clock signal line,
The second signal input unit is electrically connected to the previous signal output unit of the 4n-3 stage first pulse output circuit,
The third signal input unit is electrically connected to either the start pulse input line or the signal output unit of the 4n-1 stage pulse output circuit,
The fourth signal input unit is electrically connected to the fourth clock signal line;
In the pulse output circuit at the 4n-1 stage,
The first signal input unit is electrically connected to the third clock signal line,
The second signal input unit is electrically connected to the first signal output unit of the 4n-2 stage first pulse output circuit,
The third signal input unit is electrically connected to either the start pulse input line or the signal output unit of the 4n-th stage pulse output circuit,
The fourth signal input unit is electrically connected to the first clock signal line;
In the 4n stage pulse output circuit,
The first signal input unit is electrically connected to the fourth clock signal line,
The second signal input unit is electrically connected to the previous signal output unit of the 4n-1 stage previous pulse output circuit,
The third signal input unit is electrically connected to either the start pulse input line or the signal output unit of the 4n + 1 stage pulse output circuit,
The fourth signal input unit is electrically connected to the second clock signal line;
A sampling pulse is sequentially output in accordance with the first to fourth clock signals and the start pulse.

  The pulse output circuit of the present invention may be configured using only N-channel type transistors or may be configured using only P-channel type transistors.

  The shift register of the present invention may be configured using only N-channel transistors, or may be configured using only P-channel transistors.

  According to the present invention, even when the driving circuit and the pixel portion of the display device are configured by only one-conductivity type TFT, the output of the normal amplitude can be output without causing the amplitude attenuation of the output pulse due to the TFT threshold value. Pulses can be obtained and the number of manufacturing steps of the display device can be reduced, which contributes to cost reduction and improvement in yield, and enables the display device to be supplied at a lower cost.

  FIG. 1A is a schematic diagram of a shift register of the present invention. In the block diagram of FIG. 1A, a block denoted by 100 is a pulse output circuit that outputs a sampling pulse for one stage. This pulse output circuit is connected in a plurality of stages, and FIG. The shift register shown is configured. The shift register illustrated in FIG. 1A includes a first clock signal line to a fourth clock signal line, and a start pulse input line. The first clock signal to the fourth clock signal (CK1 to CK4) are input from the first clock signal line to the fourth clock signal line, respectively, and the start pulse (SP) is input from the start pulse input line. The

  FIG. 1B shows a detailed circuit configuration of the block 100. The gate electrode of the TFT 101 and the gate electrode of the TFT 103 are connected to the first signal input portion (CKA). The input electrode of the TFT 101 is connected to the second signal input portion (In), and the output electrode is connected to the gate electrode of the TFT 102 and one end of the electrode of the capacitor 104. The input electrode of the TFT 102 is connected to the third signal input unit (CKB). The output electrode of the TFT 102, the output electrode of the TFT 103, and the other end of the capacitor 104 are connected to a signal output unit (Out). The input electrode of the TFT 103 is connected to a low potential side power supply (VSS).

  The circuit shown in this embodiment is as follows. Although it is configured using only N-channel TFTs, a similar circuit can be configured using only P-channel TFTs.

  The clock signal input to the first signal input unit (CKA) and the clock signal input to the third signal input unit (CKB) are signals whose polarities are inverted. Further, the phase of the second clock signal is delayed by ¼ period with respect to the first clock signal, and the phase of the third clock signal is further ¼ with respect to the second clock signal. The cycle is delayed. The phase of the fourth clock signal is further delayed by a quarter cycle with respect to the third clock signal. That is, the third clock signal has a ½ cycle delay with respect to the first clock signal, and is just equal to the polarity inverted. Similarly, the fourth clock signal has a delay of ½ period with respect to the second clock signal, and is equivalent to a signal whose polarity is just inverted.

  In the shift register using the pulse output circuit illustrated in FIG. 1B in a plurality of stages in succession, an output pulse from the previous stage is input to the second signal input portion (In). Here, at the first stage, a start pulse is input to the second signal input unit (In).

  As shown in Table 1, in the 4n-3rd stage (n is a natural number, 1 ≦ n), the first clock signal is input to the first signal input unit (CKA), and the third signal The third clock signal is input to the input unit (CKB). In the 4n-2 stage (n is a natural number, 1 ≦ n), the second signal is input to the first signal input unit (CKA), and the second signal input unit (CKB) is connected to the second clock signal. 4 clock signals are input. In the 4n-1 stage, the third clock signal is input to the first signal input unit (CKA), and the first clock signal is input to the third signal input unit (CKB). In the 4n-th stage, the fourth clock signal is input to the first signal input unit (CKA), and the first clock signal is input to the third signal input unit (CKB).

  That is, the shift register of the present embodiment has a portion including a continuous four-stage pulse output circuit as a constituent unit, and this constituent unit is repeated. Even if the number of connection stages of the pulse output circuit is 4 or less, the input order of the clock signals follows Table 1.

  The operation of the circuit will be described with reference to the circuit diagram shown in FIG. 1 and the timing chart shown in FIG. Here, the voltage amplitude of the clock signal and the start pulse is assumed to be L level / H level = VSS / VDD, and at this time, VSS <VDD will be described.

<1> In the first-stage pulse output circuit, the first clock signal (CK1) is input to the gate electrodes of the TFTs 101 and 103 to be H level, and the TFTs 101 and 103 are turned on. At this time, since the start pulse (SP) has not been inputted yet, the potential of the gate electrode of the TFT 102 is at the L level. Therefore, the potential of the signal output unit (Out) is fixed at the L level.

  <2> Next, when the start pulse (SP) input from the signal input unit (In) becomes H level, the potential of the gate electrode of the TFT 102 rises to (VDD−VthN) and then enters a floating state. Accordingly, the TFT 102 is turned on, but the third clock signal (CK3) input to the signal input unit (CKB) is at the L level at this time, and the potential of the signal output unit (Out) does not change.

  <3> Next, the first clock signal (CK1) becomes L level, and the TFTs 101 and 103 are turned OFF. At the same time, the third clock signal (CK3) becomes H level. Since the TFT 102 is already ON, the potential of the signal output unit (Out) rises. Here, since the TFT 101 is already OFF, the gate electrode of the TFT 102 is in a floating state with the potential being (VDD−VthN), but the potential of the signal output portion (Out) is increased. Accordingly, the potential of the gate electrode of the TFT 102 further rises from (VDD−VthN) and takes a potential higher than (VDD + VthN) by the function of the capacitor 104. Therefore, when the signal output portion (Out) becomes H level, the potential becomes equal to VDD.

  <4> Eventually, the start pulse (SP) becomes L level. Subsequently, when the first clock signal (CK1) becomes H level again, the TFTs 101 and 103 are turned ON, and the potential of the gate electrode of the TFT 102 is L level and turned OFF. On the other hand, since the TFT 103 is ON, the potential of the signal output portion (Out) becomes L level.

  The above operation is performed up to the final stage, and sampling pulses are sequentially output. The shift register configured using the pulse output circuit of the present invention is configured by only one-conductivity type TFT, but has a normal amplitude without causing amplitude attenuation of the output pulse due to the threshold value of the TFT. An output pulse can be obtained. Even during the period when the sampling pulse is not output, every time the clock signal input from the signal input portion (CKA) becomes H level, the TFT 103 is turned on, and the potential of the signal output portion (Out) is determined at L level. Therefore, since the signal output portion does not float for a long time, it can be used in a circuit having a relatively low operating frequency, such as a gate signal line driver circuit.

  Examples of the present invention will be described below.

  FIG. 3A shows an example in which a scan direction inversion function is added to the shift register described in the embodiment of the present invention. Compared with the circuit shown in FIG. 1A, an input switching signal (LR) and an input switching inversion signal (RL) are added.

  FIG. 3B shows in detail the configuration of the pulse output circuit for one stage indicated by the block 300 in FIG. The pulse output circuit including the TFTs 301 to 303 and the capacitor 304 is the same as that shown in FIG. 1B, but the switch including the TFTs 305 and 306, the fifth signal input unit, and the sixth signal input. The input switching circuit 310 is configured by using the unit.

  The output electrodes of the TFTs 305 and 306 are both connected to the input electrode of the TFT 301. The input electrode of the TFT 305 is connected to the second signal input portion (InL), and the gate electrode is electrically connected to the fifth signal input portion (L). The input electrode of the TFT 306 is connected to the third signal input portion (InR), and the gate electrode is electrically connected to the sixth signal input portion (R). An input switching signal (LR) is input to the fifth signal input unit (L), and an input switching inversion signal (RL) is input to the sixth signal input unit (R). LR and RL take H level or L level exclusively from each other, and therefore the input switching circuit 310 of this embodiment takes the following two states.

  First, when LR is at the H level and RL is at the L level, the TFT 305 is turned on and the TFT 306 is turned off. Therefore, the previous sampling pulse is input to the input electrode of the TFT 301 from the second signal input portion (InL). Second, when LR is at L level and RL is at H level, TFT 305 is turned off and TFT 306 is turned on. Therefore, the previous sampling pulse is input to the input electrode of the TFT 301 from the third signal input portion (InR).

  In the shift register of FIG. 3A, when LR is at H level and RL is at L level, the output of the sampling pulse is in the order of the first stage, the second stage,..., And LR is at the L level. When RL is at the H level, the sampling pulse is output in the order of the last stage,..., The second stage, and the first stage.

  Further, when switching the scanning direction, it is necessary to change the input timing of the clock signal. The timing chart shown in FIG. 2 is for forward scanning. FIG. 4 shows a timing chart at the time of backward scanning. In contrast to the case of FIG. 2, each clock signal is inputted with a third clock signal delayed by a quarter cycle from the fourth clock signal, and further inputted with a second clock signal after a quarter cycle delay. Then, the first clock signal is input with a delay of 1/4 cycle. At this time, the input timing of the start pulse is determined by the number of stages of the pulse output circuit used for the shift register, that is, by which clock signal the pulse output circuit that should output the sampling pulse first is driven. FIG. 4 shows an example in which the fourth clock signal is input to the signal input portion (CKA) and the second clock signal is input to the signal input portion (CKB) in the end pulse output circuit.

  In this embodiment, an example in which a display device is manufactured using TFTs having only one polarity will be described.

  FIG. 12 is an overall schematic diagram of the display device. A source signal line driver circuit 1201, a gate signal line driver circuit 1202, and a pixel portion 1203 are integrally formed over a substrate 1200. In the pixel portion 1203, a portion surrounded by a dotted line frame 1210 is one pixel. The example of FIG. 12 shows a pixel of a liquid crystal display device, and ON / OFF control is performed when a charge is applied to one electrode of a liquid crystal element by one TFT (hereinafter referred to as a pixel TFT). Yes. Signals (clock signal, start pulse, etc.) for driving the source signal line driver circuit 1201 and the gate signal line driver circuit 1202 are input from the outside through a flexible printed circuit (FPC) 1204.

  FIG. 5 is a diagram showing an overall configuration of the source signal line driver circuit 1201 in the display device shown in FIG. This source signal line driver circuit has a clock signal level shifter 501, a start pulse level shifter 502, a pulse output circuit 503 constituting a shift register, a NAND circuit 504, a buffer 505, and a sampling switch 506, which are inputted from the outside. These signals are the first to fourth clock signals (CK1 to CK4), the start pulse (SP), the input switching signal (LR), the input switching inversion signal (RL), and the analog video signal (Video1 to Video12). Among these, the first to fourth clock signals (CK1 to CK4) and the start pulse (SP) are subjected to amplitude conversion by a level shifter immediately after being input as a low voltage amplitude signal from the outside, A signal is input to the drive circuit. Further, in the source signal line driving circuit in the display device of this embodiment, the sampling pulse output from the one-stage pulse output circuit in the shift register drives the sampling switch 506, so that the source signal line driving circuit has 12 columns of source signal lines. Sampling analog video signals simultaneously.

  FIG. 6A shows the configuration of the clock signal level shifter 501. This is because one set of clock signals (CK1 and CK3 or CK2 and CK4) having opposite polarities are arranged in parallel and one-input type level shifter circuit is arranged in parallel (Stage 1). In (Stage2 to Stage4), the output of each other is used as each inverting input.

  An operation of the circuit illustrated in FIG. 6A will be described. Note that the potential of the power supply used here is three potentials of VSS, VDD1, and VDD2, and VSS <VDD1 <VDD2. In this embodiment, VSS = 0 [V], VDD1 = 5 [V], and VDD2 = 16 [V]. In FIG. 6A, the TFTs 601, 603, 606, and 608 have a double gate structure; however, these may be a single gate or a multi-gate structure having three or more gate electrodes. . For other TFTs, there is no particular limitation due to the number of gate electrodes.

A first clock signal (CK1) having an amplitude of L level / H level = VSS / VDD1 is input from the signal input unit (CK in1). When CK1 is at the H level, the TFTs 602 and 604 are turned on, and the potential of the gate electrode of the TFT 603 is turned to the L level and turned off. Here, the ON resistance of the TFT 602 is designed to be sufficiently lower than that of the TFT 601. Therefore, the L level appears at the node α. When CK1 is at L level, the TFTs 602 and 604 are turned off. Therefore, the potential of the gate electrode of the TFT 603 is raised to the VDD2 side through the TFT 601 which is operating in saturation, and when the potential becomes (VDD2-VthN), the TFT 601 is turned off and the gate electrode of the TFT 603 is in a floating state. As a result, the TFT 603 is turned on, and the potential of the node α is raised to the VDD2 side. Here, the TFT which is in a floating state as the potential of the node α is increased by the function of the capacitor 605.
When the potential of the gate electrode 603 is raised and the potential is higher than VDD2, and exceeds (VDD2 + VthN), the H level appearing at the node α becomes equal to VDD2. Therefore, the L level of the output signal is VSS and the H level is VDD2, and the amplitude conversion is completed.

  On the other hand, the third clock signal (CK3) having the same amplitude of VSS-VDD1 is input from the signal input unit (CK in2). By the same operation as described above, amplitude conversion is performed by a one-input type level shifter circuit including TFTs 606 to 609 and a capacitor 610, and a signal having an amplitude of VSS-VDD2 is output to the node β. Note that the signal appearing at the node α is inverted in polarity with respect to the input CK1, and the signal appearing at the node β is inverted with respect to the input CK3.

  In the level shifter used in the display device of this embodiment, a buffer stage is provided after the level shifter circuit (Stage 1) in consideration of the load on the pulse after amplitude conversion (Stage 2 to Dtage 4). The inverter circuit constituting this buffer stage is a two-input type and requires an input signal and its inverted signal. The reason for using the two-input type is low power consumption. In the level shifter circuit described above, when the TFT 602 is ON, a through current flows between VSS and VDD2 through the TFT 601 to the TFT 602. By using a two-input type, a through current does not flow during operation.

  In FIG. 6, in the stage 2 inverter circuit, a signal input to the gate electrode of the TFT 611 and a signal input to the gate electrode of the TFT 612 are signals having opposite polarities. Therefore, using the fact that CK1 and CK3 are signals having opposite polarities, the output signal appearing at the node α and the output signal appearing at the node β are used as the inverting inputs of the signals.

  The operation of the inverter circuit will be described. Here, an operation in an inverter circuit including TFTs 611 to 614 and a capacitor 615, which is one of Stage2, will be described. The operation is the same for other inverter circuits.

When the signal input to the gate electrode of the TFT 611 is at the H level, the TFT 611 is turned on, the potential of the gate electrode of the TFT 613 is raised to the VDD2 side, and when the potential becomes (VDD2-VthN), the TFT 611 is turned off. The gate electrode of the TFT 613 is in a floating state. On the other hand, since the signal input to the gate electrodes of the TFTs 612 and 614 is L level, the TFTs 612 and 614 are turned off. Since the potential of the gate electrode of the TFT 613 has increased to (VDD2-VthN), the TFT 613 is turned on, and the potential of the node γ is raised to the VDD2 side. Here, similarly to the operation of the level shifter circuit described above, the potential of the gate electrode of the TFT 613 which is in a floating state is raised as the potential of the node γ is increased by the action of the capacitor 615, and the potential is higher than VDD2. By taking the potential and exceeding (VDD2 + VthN), the H level appearing at the node γ becomes equal to VDD2.

On the other hand, when the signal input to the gate electrode of the TFT 611 is L level, the TFT 611 is turned OFF, and the H level is input to the gate electrodes of the TFTs 612 and 614 and turned ON. Accordingly, the potential of the gate electrode of the TFT 613 becomes L level, and the L level appears at the node γ.

By a similar operation, a pulse is also output to the node δ. At this time, a pulse whose polarity is inverted from that of the pulse appearing at the node γ is output to the node δ.

  Thereafter, the pulse is finally output to the signal output unit (3) and the signal output unit (4) by the same operation in Stage3 and Stage4.

  FIG. 6B shows a state of amplitude conversion of the clock signal. The amplitude of the input signal is L level / H level = VSS / VDD1 (0V / 5V), and the amplitude of the output signal is L level / H level = VSS / VDD2 (0V / 16V).

  FIG. 6C shows a level shifter for the start pulse (SP). In the case of the start pulse, since it does not have its inverted signal, the output of the one-input type level shifter circuit (Stage 1) is input to the one-input type inverter circuit (Stage 2), and the output of Stage 1 and the output of Stage 2 are Use to continue to a two-input inverter circuit (Stage 3). Regarding the circuit operation, the one-input type level shifter circuit is the same as that of the clock signal. Also with respect to the 1-input type inverter circuit, the amplitude of the input signal is L level / H level = VSS / VDD2 and there is no amplitude conversion between input and output pulses as compared to the 1-input type level shifter circuit. Since the operation in the circuit is the same, the description is omitted here.

  FIG. 6D shows the state of amplitude conversion of the start pulse (SP). As with the clock signal, the amplitude of the input signal is L level / H level = VSS / VDD1 (0V / 5V), and the amplitude of the output signal is L level / H level = VSS / VDD2 (0V / 16V). .

  FIG. 7A shows a two-input NAND circuit. The configuration is similar to the one-input inverter circuit, and the only difference is that the signal input section in the one-input inverter circuit has two inputs and the TFTs 702 and 703 and the TFTs 705 and 706 are arranged in series.

When the H level is input to both the signal input unit (In1) and the signal input unit (In2), the TFTs 702, 703, 705, and 706 are turned on, and the potential of the gate electrode of the TFT 704 is turned to the L level and turned off. The L level appears in the signal output part (Out). When the L level is input to one or both of the signal input portion (In1) and the signal input portion (In2), the gate electrode of the TFT 704 and the power supply VSS are not electrically connected, so the potential of the gate electrode of the TFT 704 is on the VDD2 side. Then, the capacitor 707 takes on a potential higher than (VDD2 + VthN), and an H level of the potential VDD2 appears in the signal output portion (Out).

  FIG. 7B shows the configuration of the buffer, which is composed of a one-input inverter circuit (Stage 1) and a two-input inverter circuit (Stage 2 to Stage 4). Since the operation of both the 1-input type inverter circuit and the 2-input type inverter circuit has been described in the section of the level shifter, the description thereof is omitted here.

  FIG. 7C shows the configuration of the sampling switch. A sampling pulse is input from the signal input section (25), and twelve TFTs 731 arranged in parallel are controlled simultaneously. The analog video signal is input to the input electrodes (1) to (12) of the twelve TFTs 731, and the potential of the video signal when the sampling pulse is input is written to the source signal line.

  Among the circuits constituting the driving circuit of the display device shown in this embodiment, the inverter circuit and the level shifter circuit are described in the invention filed in Japanese Patent Application No. 2001-133431 by the same inventors. The same thing is used.

  In the display device shown in this embodiment, a driver circuit included in the entire display device including a pixel portion is manufactured using only a unipolar TFT (for example, an N-channel TFT) having the same polarity as the pixel TFT. ing. As a result, an ion doping step for imparting P-type to the semiconductor layer can be omitted, which can contribute to reduction in manufacturing cost and improvement in yield.

  In addition, although the polarity of the TFT constituting the display device of this embodiment is an N-channel type, it is possible to configure the drive circuit and the pixel TFT using only the P-channel type TFT according to the present invention. In this case, it is noted that the omitted ion doping step is a step of imparting N-type to the semiconductor layer. The present invention can be applied not only to a liquid crystal display device but also to any semiconductor device manufactured by integrally forming a drive circuit on an insulator.

  In the embodiments and the examples so far, an example in which a circuit is configured using only N-channel TFTs has been described. However, the same applies to the case where only P-channel TFTs are used by replacing the level of the power supply potential. A circuit can be configured.

  FIGS. 13A and 13B show examples of shift registers configured using only P-channel TFTs. The block diagram shown in FIG. 13A has the same configuration as the shift register configured using only the N-channel TFT shown in FIG. 1, and the block 1300 outputs a sampling pulse for one stage. This is a pulse output circuit. As shown in FIG. 13B, the power supply potential is reversed as a difference from a shift register including N-channel TFTs.

  FIG. 14 shows a timing chart and output pulses. Since the operation of each part has been described with reference to FIGS. 1 and 2 in the embodiment, detailed description thereof is omitted here. The one shown in FIG. 2 is a form in which the H level and the L level are reversed.

  This time, a test piece of a shif and a register as shown in FIG. 15 was produced. The configuration has nine stages of pulse output circuits, and the channel length / channel width and capacitance value of each TFT are as shown in FIG.

  A circuit simulation result of this shift register is shown in FIG. As operating conditions, the amplitude of the input signal was L level / H level = 0 V / 10 V, and the power supply potential of the circuit was the same. The outputs of FIG. 16 are the first clock signal (CK1), the start pulse (SP), the shift register first stage output (SROut1), the shift register second stage output (SROut2), and the shift register third stage from the graph. Output (SROout3), shift register fourth stage output (SROut4).

  FIG. 17 shows the operation verification result of the test piece of the shift register actually manufactured. FIG. 17A shows a first clock signal (CK1), a start pulse (SP), a shift register first stage output (SROut1), a shift register second stage output (SROut2), and a shift register third from the graph. FIG. 17B shows the first clock signal (CK1), the start pulse (SP), the shift register No. 6 from the graph, and shows the stage output (SROout3) and the shift register fourth stage output (SROut4). A stage output (SROut6), a shift register seventh stage output (SROut7), a shift register eighth stage output (SROut8), and a shift register final stage output (SROut9) are shown. According to FIGS. 17A and 17B, normal operation was confirmed at a power supply voltage of 10 V and a drive frequency of about 5 MHz.

  The present invention can be applied to manufacture of display devices used in various electronic devices. Examples of such electronic devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, televisions, mobile phones, and the like. An example of them is shown in FIG.

  FIG. 8A illustrates a liquid crystal display (LCD), which includes a housing 3001, a support base 3002, a display portion 3003, and the like. The present invention can be applied to the display portion 3003.

FIG. 8B illustrates a video camera, which includes a main body 3011, a display portion 3012, an audio input portion 3013, operation switches 3014, a battery 3015, an image receiving portion 3016, and the like. The present invention can be applied to the display portion 3012.

  FIG. 8C illustrates a laptop personal computer, which includes a main body 3021, a housing 3022, a display portion 3023, a keyboard 3024, and the like. The present invention can be applied to the display portion 3023.

  FIG. 8D illustrates a portable information terminal, which includes a main body 3031, a stylus 3032, a display portion 3033, operation buttons 3034, an external interface 3035, and the like. The present invention can be applied to the display portion 3033.

  FIG. 8E illustrates a sound reproducing device, specifically an in-vehicle audio device, which includes a main body 3041, a display portion 3042, operation switches 3043 and 3044, and the like. The present invention can be applied to the display portion 3042. In this embodiment, the in-vehicle audio device is taken as an example, but it may be used for a portable or home audio device.

  FIG. 8F illustrates a digital camera, which includes a main body 3051, a display portion (A) 3052, an eyepiece portion 3053, operation switches 3054, a display portion (B) 3055, a battery 3056, and the like. The present invention can be applied to the display portion (A) 3052 and the display portion (B) 3055.

  FIG. 8G illustrates a mobile phone, which includes a main body 3061, an audio output portion 3062, an audio input portion 3063, a display portion 3064, operation switches 3065, an antenna 3066, and the like. The present invention can be applied to the display portion 3064.

  It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

FIG. 5 is a diagram showing one mode of a shift register configured using a pulse output circuit of the present invention. FIG. 3 is a diagram showing a timing chart for driving the shift register shown in FIG. 1. The figure which shows the shift register which added the scanning direction switching function which is one Example of this invention. FIG. 4 is a diagram illustrating an example of a timing chart for driving the shift register illustrated in FIG. 3. FIG. 11 illustrates a configuration example of a source signal line driver circuit in a display device provided by the present invention. FIG. 4 is a detailed diagram of a circuit configuration of a level shifter in the display device provided by the present invention. 4 is a detailed diagram of a circuit configuration of a NAND circuit, a buffer, and a sampling switch in a display device provided by the present invention. FIG. FIG. 11 illustrates an example of an electronic device to which the present invention can be applied. The figure which shows the structure of a conventional CMOS inverter and a load type inverter, and the waveform of each input-output signal. 4A and 4B illustrate an operation principle of a pulse output circuit of the present invention. The figure which shows the circuit structure and timing chart of a conventional shift register. The figure which shows the whole external appearance of the display apparatus provided by this invention. FIG. 5 is a diagram showing a shift register using a pulse output circuit configured by transistors of different conductivity types from the embodiment. FIG. 14 is a timing chart for driving the shift register shown in FIG. 13. The figure which shows TFT size and the capacitance value in the test piece of the produced shift register. The figure which shows the simulation result of the shift register shown in FIG. The figure which shows the result of actually producing and measuring the shift register shown in FIG.

Claims (22)

A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The buffer has a first inverter circuit and a second inverter circuit,
The output of the level shifter circuit is input to the first inverter circuit,
The output of the level shifter circuit and the output of the first inverter circuit are input to the second inverter circuit,
The level shifter circuit includes first to fourth transistors,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The buffer included in the start pulse level shifter includes a first inverter circuit and a second inverter circuit;
The output of the level shifter circuit included in the start pulse level shifter is input to the first inverter circuit,
The output of the level shifter circuit and the output of the first inverter circuit that the start pulse level shifter has are input to the second inverter circuit,
The level shifter circuit includes first to fourth transistors,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The level shifter circuit includes a first level shifter circuit and a second level shifter circuit,
The buffer includes a first inverter circuit and a second inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The level shifter circuit includes a first level shifter circuit and a second level shifter circuit,
The buffer includes a first inverter circuit to a fourth inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The level shifter circuit includes a first level shifter circuit and a second level shifter circuit,
The buffer includes a first inverter circuit to a sixth inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fifth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
The sixth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The level shifter circuit included in the clock pulse level shifter includes a first level shifter circuit and a second level shifter circuit,
The buffer included in the clock pulse level shifter includes a first inverter circuit and a second inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The level shifter circuit included in the clock pulse level shifter includes a first level shifter circuit and a second level shifter circuit,
The buffer included in the clock pulse level shifter includes a first inverter circuit to a fourth inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The level shifter circuit included in the clock pulse level shifter includes a first level shifter circuit and a second level shifter circuit,
The buffer included in the clock pulse level shifter includes first to sixth inverter circuits,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fifth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
The sixth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor,
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of a source and a drain of the third transistor is electrically connected to the first wiring;
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The buffer has a first inverter circuit and a second inverter circuit,
The output of the level shifter circuit is input to the first inverter circuit,
The output of the level shifter circuit and the output of the first inverter circuit are input to the second inverter circuit,
The level shifter circuit includes first to fourth transistors, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The buffer included in the start pulse level shifter includes a first inverter circuit and a second inverter circuit;
The output of the level shifter circuit included in the start pulse level shifter is input to the first inverter circuit,
The output of the level shifter circuit and the output of the first inverter circuit that the start pulse level shifter has are input to the second inverter circuit,
The level shifter circuit includes first to fourth transistors, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The level shifter circuit includes a first level shifter circuit and a second level shifter circuit,
The buffer includes a first inverter circuit and a second inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The level shifter circuit includes a first level shifter circuit and a second level shifter circuit,
The buffer includes a first inverter circuit to a fourth inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A level shifter circuit, a buffer to which the output of the level shifter circuit is input, and a shift register to which the output of the buffer is input,
The transistors constituting the level shifter circuit, the transistors constituting the buffer, and the transistors constituting the shift register are of the same conductivity type,
The level shifter circuit includes a first level shifter circuit and a second level shifter circuit,
The buffer includes a first inverter circuit to a sixth inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fifth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
The sixth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . In any one of Claims 3 to 5 and Claims 11 to 13,
The semiconductor device according to claim 1, wherein the first level shifter circuit and the second level shifter circuit are one-input type level shifter circuits. A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The level shifter circuit included in the clock pulse level shifter includes a first level shifter circuit and a second level shifter circuit,
The buffer included in the clock pulse level shifter includes a first inverter circuit and a second inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The level shifter circuit included in the clock pulse level shifter includes a first level shifter circuit and a second level shifter circuit,
The buffer included in the clock pulse level shifter includes a first inverter circuit to a fourth inverter circuit,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . A start pulse level shifter, a clock pulse level shifter, and an output of the start pulse level shifter and a shift register to which the output of the clock pulse level shifter is input,
Each of the start pulse level shifter and the clock pulse level shifter includes a level shifter circuit and a buffer to which the output of the level shifter circuit is input,
The transistor constituting the start pulse level shifter, the transistor constituting the clock pulse level shifter, and the transistor constituting the shift register are of the same conductivity type,
The level shifter circuit included in the clock pulse level shifter includes a first level shifter circuit and a second level shifter circuit,
The buffer included in the clock pulse level shifter includes first to sixth inverter circuits,
The output of the first level shifter circuit and the output of the second level shifter circuit are input to the first inverter circuit,
The second inverter circuit receives the output of the first level shifter circuit and the output of the second level shifter circuit,
The third inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fourth inverter circuit receives the output of the first inverter circuit and the output of the second inverter circuit,
The fifth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
The sixth inverter circuit receives the output of the third inverter circuit and the output of the fourth inverter circuit,
Each of the first level shifter circuit and the second level shifter circuit includes a first transistor to a fourth transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the first transistor and electrically connected to a first wiring, and the other of the source and the drain of the first transistor Is electrically connected to one of a source and a drain of the second transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, and the other of the source and the drain of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to the third wiring;
One of the source and the drain of the third transistor is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is the gate of the third transistor through the capacitor. Electrically connected with
One of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor is connected to the second wiring. Electrically connected, and the gate of the fourth transistor is electrically connected to the third wiring ;
The semiconductor device, wherein the first transistor and the third transistor are a double gate type or a multi gate type . In any one of Claim 6 thru | or Claim 8, Claim 15 thru | or 17,
The semiconductor device according to claim 1, wherein the first level shifter circuit and the second level shifter circuit are one-input type level shifter circuits. In any one of Claims 1 thru / or Claim 18 ,
A drive circuit having the shift register; and a plurality of pixels to which signals are input from the drive circuit;
The transistors included in the plurality of pixels and the transistors included in the driver circuit are
A semiconductor device having the same conductivity type. In any one of Claims 1 thru / or Claim 18 ,
A drive circuit having the shift register; and a plurality of pixels to which signals are input from the drive circuit;
The transistors included in the plurality of pixels and the transistors included in the driver circuit are
A semiconductor device which is a thin film transistor of the same conductivity type and is formed over the same insulator. In claim 19 or claim 20 ,
The semiconductor device, wherein the drive circuit is a gate signal line drive circuit. In claim 19 or claim 20 ,
The semiconductor device, wherein the driving circuit is a source signal line driving circuit.

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