JPH05167434A - Multilevel output circuit and multi-gradation display device - Google Patents

Abstract

PURPOSE:To provide the multilevel output circuit and the multi-gradation display device in which the reproducibility of the characteristic is improved, the limitation from a leakage current is reduced and the yield is enhanced. CONSTITUTION:This display device consists of a P-channel transistor(TR) TFTO connected between a power supply VDD and an output terminal OP, N-channel TRs TRT11-TFT44 of plural switching circuit cells S11-S44 decreasing a voltage outputted at an output terminal OP respectively in the ON operation, a selection circuit applying selective ON/OFF drive to the N-channel TRs TRT11-TFT44 corresponding to an input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-value output circuit which can be applied to a multi-tone driving unit of a liquid crystal display device and a multi-tone display device using this multi-value output circuit.

[0002]

2. Description of the Related Art Conventionally, polysilicon TF for liquid crystal display devices has been used.
In a multi-valued output circuit using T (thin film transistor), a so-called sample and hold circuit is usually applied. However, the sample and hold circuit needs to form a large capacity (capacitor), and the leakage current of the transistor must be suppressed to a very small level.
It is difficult to obtain a stable operation with a TFT having a large leak current and large characteristic variations, such as a polysilicon TFT, and there is a yield problem in forming a large capacitance. Further, in a dynamic circuit such as a sample and hold circuit, there is a problem that the reproducibility of the characteristics deteriorates due to the variation of the holding voltage caused by the leak current.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to improve the reproducibility of the characteristics and reduce the restriction from the leak current to improve the manufacturing yield. An object is to provide a circuit and a multi-gradation display device using this multi-value output circuit.

[0004]

In order to solve the above-mentioned problems, the present invention provides an electronic element connected between a power source and an output terminal and a parallel connection between the output terminal and a ground potential. A multi-valued static circuit comprising a plurality of switching transistors each of which lowers the voltage output to the output terminal by an ON operation, and a selection circuit which selectively drives the switching transistors ON / OFF in response to an input signal. By configuring the output circuit, it is possible to improve the reproducibility of the characteristics, reduce the restriction from the leakage current, and improve the manufacturing yield.

[0005]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 to 4 are views for explaining an embodiment of a multi-value output circuit of the present invention. FIG. 1 is a circuit diagram of a multi-value output circuit capable of outputting 16 levels, and FIG. 2 is a diagram. 1 is a circuit diagram of a multi-switching circuit cell S _ij arranged in a matrix part of 1.
3 is an explanatory diagram showing the relationship between the input code and the output voltage of the multilevel output circuit of FIG. 1, and FIG. 4 is a circuit diagram showing the operating principle of FIG. That is, as shown in FIG. 1, the input terminals A ₀ , A ₁ ,
A ₂ and A ₃ are connected to the input terminal of the AND gate AND1, and the output terminal of the AND gate AND1 is connected to the gate of the P-channel transistor TFT0. The P-channel transistor TFT0 has a source connected to the power supply V _DD and a drain connected to the output terminal OP. The input terminals A ₂ and A ₃ are connected to the input terminal of the OR gate OR1 and the input terminal of the AND gate AND2, and the output terminal of the AND gate AND2 is connected to the terminals Y _b3 and Y _a4. Output terminals are terminals Y _b1 , Y _a2
Connected to. The input terminal A ₃ is connected to the terminals Y _b2 and Y _a3 , the terminal Y _a1 is connected to the power source V _DD , and the terminal Y _b4 is connected to the power source V _DD via the inverter I. The input terminals A ₀ and A ₁ are connected to the input terminal of the OR gate OR2 and the input terminal of the AND gate AND3. The output terminal of the AND gate AND3 is connected to a terminal X _4,
The output terminal of the OR gate OR2 is connected to the terminal X ₂ . The input terminal A ₁ is connected to the terminal X ₃ , and the terminal X ₁
Is connected to the power supply V _DD . The output terminal O ₁ ~ O _4, terminal X ₁ to X _4, terminal Y _a1 to Y _a4, terminal Y _b1 to Y _b4 not constitute the matrix portion MX, the output terminal O ₁ ~ O _4,
The terminals X _{1 to} X ₄ are connected to the column lines of the matrix part MX, and the terminals Y _{a1 to} Y _a4 and the terminals Y _{b1 to} Y _b4 are connected to the row lines of the matrix part MX, and further, the column lines and the row lines. The switching circuit cells S11 to S are provided at each intersection of
44 are arranged in a matrix and connected.

Each of the switching circuit cells S11 to S4
2, terminals Y _aj and Y _bj are connected to the input ends of the AND gates AND4, and the output ends of the AND gates AND4 are connected to the input ends of the OR gate OR3. The terminals Y _aj and X _i are connected to the input terminal of the AND gate AND5, and the output terminal of the AND gate AND5 is connected to the input terminal of the OR gate OR3. The output terminal I _ij of this OR gate OR3 is an N-channel transistor TFT.
This N-channel transistor T connected to the gate of _ij
The drain of FT _ij is connected to the output terminal O _i , and the source is grounded.

That is, the switching circuit cells S11 to S44 arranged in each matrix are connected to the terminals Y _aj ,
When the following signals are input to Y _bj and X _i , 1 is output to the terminal I _ij , and the N-channel transistor TFT _ij is selected and turned on.

Thus, the input terminals A ₀ , A ₁ ,
Input codes as shown in FIG. 3 are input to A ₂ and A ₃ . As shown in FIG. 3, the input code "0,0,0,0"
When "0" is input, "0,0" is input to the OR gate OR1, the output becomes "0", and the terminals Y _b1 and Y _a2 become "0". "0,0" is input to the AND gate AND2, the output becomes "0", and the terminals Y _b3 and Y _a4 become "0".
OR gate OR2 is output is input is "0, 0" is "0", the terminal X ₂ is "0". Output AND gate AND3 is input is "0, 0" is "0", the terminal X ₄ is "0". The terminal Y _a1 is connected to the power supply V _DD and becomes “1”. The terminals Y _b2 and Y _a3 are connected to the input terminal A ₃ and become “0”. The terminal Y _b4 is connected to the power source V _DD through the inverter I and becomes “0”. Terminal X ₁ is power supply V
Connected to _DD and becomes "1". The terminal X ₃ is connected to the input terminal A ₁ and becomes “0”. Therefore, only the switching TFT ₁₁ of the switching circuit cell S _ij is turned on,
TFTs _{12 of} other switching circuit cells S12 to S44
All TFTs ₄₄ are turned off. Similarly, when the input code “1,0,0,0” is input, the TFTs ₁₁ and _{21 of} the switching circuit cells S11 and S21 are turned on, and the TFTs of the other switching circuit cells are turned off.
Similarly, when the input code “0,1,0,0” is input, the TFTs ₁₁ , T of the circuit cells S11, S21, S31 are input.
FT ₂₁ and TFT ₃₁ are turned on, and TFTs of other circuit cells
Turns off. Similarly, input code "1, 1, 0,
When "0" is input, the circuit cells S11, S21, S3
1, S41 TFT ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁
Is turned on, and the TFTs of other circuit cells are turned off. Similarly, when the input code “0,0,1,0” is input, each circuit cell S11, S21, S31, S41,
The TFT included in S12 is turned on, and the TFTs of other circuit cells are turned off. In addition, input code “1, 0, 1,
When "0" is input, the circuit cells S11, S21, S3
Each TFT of 1, S41, S12, S22 is turned on,
The TFTs of other circuit cells are turned off. When the input code “0,1,1,0” is input, the circuit cell S11,
The TFTs of S21, S31, S41, S12, S22 and S32 are turned on, and the TFTs of other circuit cells are turned off. When the input code “1,1,1,0” is input, the circuit cells S11, S21, S31, S41, S1 are input.
Each TFT of 2, S22, S32, S42 is turned on,
The TFTs of other circuit cells are turned off. When the input code “0,0,0,1” is input, the circuit cell S11,
S21, S31, S41, S12, S22, S32, S
42, TFT of S13 is turned on, and T of other circuit cells
FT is turned off. Similarly, input code "1, 0,
0, 1 ”is input, the circuit cells S11, S21, S
31, S41, S12, S22, S32, S42, S1
The TFTs of S3 and S23 are turned on, and the T of other circuit cells are turned on.
FT is turned off. In addition, input code “0, 1, 0,
1 "is input, circuit cells S11, S21, S3
1, S41, S12, S22, S32, S42, S1
The TFTs of S3, S23, and S33 are turned on, and the TFTs of other circuit cells are turned off. In addition, input code “1,
1, 0, 1 "is input, the circuit cells S11, S2
1, S31, S41, S12, S22, S32, S4
The TFTs of 2, S13, S23, S33, and S43 are turned on, and the TFTs of other circuit cells are turned off. When the input code “0,0,1,1” is input, the circuit cells S11, S21, S31, S41, S12, S22, S are added.
32, S42, S13, S23, S33, S43, S1
The TFTs of No. 4 are turned on, and the TFTs of other circuit cells are turned off. When the input code “1,0,1,1” is input, the circuit cells S11, S21, S31, S41,
S12, S22, S32, S42, S13, S23, S
The TFTs of 33, S43, S14 and S24 are turned on,
The TFTs of other circuit cells are turned off. When the input code “0, 1, 1, 1” is input, the circuit cell S11,
S21, S31, S41, S12, S22, S32, S
42, S13, S23, S33, S43, S14, S2
The TFTs of S4 and S34 are turned on, and the T of other circuit cells are turned on.
FT turns off. In addition, input code “1, 1, 1,
When "1" is input, the TFTs ₁₁ to ₄₄ included in all the circuit cells S11 to S44 are turned on. Only when the input code "1, 1, 1, 1" is input, the output of the AND gate AND1 becomes "1", and the P-channel transistor TFT0 is turned off.

FIG. 4 is a circuit diagram showing the operating principle of the multilevel output circuit of FIG. 1, in which P is provided between the power supply V _DD and the output terminal OP.
With channel transistor TFT0 are connected, the N-channel transistor TFT ₁₁ ~TFT ₄₄ conductive (ON) current of the P-channel transistor TFT0 smaller plurality is between the output terminal OP and the ground potential are connected in parallel It Each N-channel transistor TFT _{11 to} T
Terminals I _{11 to} I ₄₄ are connected to the respective gates of the FT ₄₄ . Each of the N-channel transistors TFT _{11 to} TFT ₄₄
Respectively constitute the switching circuit cells S11 to S44. Therefore, the P-channel transistor TFT
0 and the conduction current is the P-channel transistor TFT0
Less than the plurality of N-channel transistors TFT ₁₁ ~
Each dimension W of TFT ₄₄ (pattern width)
If / L (pattern length) is set to a predetermined value,
As shown in, the output voltage can be linearly changed with respect to the input code input to the input terminals A ₀ , A ₁ , A ₂ , and A ₃ . That is, when the input code "0,0,0,0" is input and only the N-channel transistor TFT ₁₁ is turned on, the P-channel transistor TFT0 and the P-channel transistor TFT0 are output so that the output voltage 15 / 16V _DD is output to the output terminal OP. The dimension W / L of each N-channel transistor TFT ₁₁ is determined. By keeping decide each dimension W / L of the P-channel transistor TFT0 and N-channel transistor TFT ₁₁ Thus, the output from the conduction current of the N-channel transistor TFT ₁₁ for conducting current of the P-channel transistor TFT0 to the output terminal OP The voltage of 15 / 16V _DD is output. Similarly, when the input code “1,0,0,0” is input, the N-channel transistors TFT ₁₁ and TFT ₂₁ are turned on, and the output voltage OP of 16/16 V _DD is output to the output terminal OP. Similarly, input code "0,1,0,0"
Is input, N-channel transistors TFT ₁₁ and T
The FT ₂₁ and the TFT ₃₁ are turned on, and the output voltage 13 / 16V _DD is output to the output terminal OP. Similarly, when the input code “1,1,0,0” is input, the N-channel transistors TFT ₁₁ , TFT ₂₁ , TFT ₃₁ , and TFT ₄₁ are turned on, and the output voltage OP is 12 / 16V. _DD
Is output. Similarly, input code "0, 0, 1,
When "0" is input, the N-channel transistor TF
T ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , and TFT ₁₂ are turned on, and an output voltage 11 / 16V _DD is output to the output terminal OP. Similarly, input code "1,0,1,0"
Is input, N-channel transistors TFT ₁₁ and T
The FT ₂₁ , TFT ₃₁ , TFT ₄₁ , TFT ₁₂ , and TFT ₂₂ are turned on, and an output voltage 10/16 V _DD is output to the output terminal OP. Similarly, input code "0, 1, 1,
When "0" is input, the N-channel transistor TF
T ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TFT ₁₂ , TF
The T ₂₂ and the TFT ₃₂ are turned on, and the output voltage 9 / 16V _DD is output to the output terminal OP. Similarly, when the input code "1, 1, 1, 0" is input, the N-channel transistors TFT ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TF.
The T ₁₂ , TFT ₂₂ , TFT ₃₂ , and TFT ₄₂ are turned on, and the output voltage OP of 16/16 V _DD is output. Similarly, when the input code “0,0,0,1” is input, the N-channel transistors TFT ₁₁ , TFT ₂₁ , TF
T ₃₁ , TFT ₄₁ , TFT ₁₂ , TFT ₂₂ , TFT ₃₂ , TF
T ₄₂ and TFT ₁₃ are turned on, and the output voltage 7 / 16V _DD is output to the output terminal OP. Similarly, when the input code “1,0,0,1” is input, the N-channel transistors TFT ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TF.
T ₁₂ , TFT ₂₂ , TFT ₃₂ , TFT ₄₂ , TFT ₁₃ , TF
T ₂₃ is turned on, and the output voltage OP is 6/16
V _DD is output. Similarly, input code "0, 1,
0,1 ”is input, the N-channel transistor TF
T ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TFT ₁₂ , TF
T ₂₂ , TFT ₃₂ , TFT ₄₂ , TFT ₁₃ , TFT ₂₃ , TF
T ₃₃ turns on, and the output voltage OP is 5/16
V _DD is output. Similarly, input code "1, 1,
0,1 ”is input, the N-channel transistor TF
T ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TFT ₁₂ , TF
T ₂₂ , TFT ₃₂ , TFT ₄₂ , TFT ₁₃ , TFT ₂₃ , TF
The T ₃₃ and the TFT ₄₃ are turned on, and the output voltage 4 / 16V _DD is output to the output terminal OP. Similarly, when the input code "0,0,1,1" is input, N-channel transistors TFT ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TF
T ₁₂ , TFT ₂₂ , TFT ₃₂ , TFT ₄₂ , TFT ₁₃ , TF
T ₂₃ , TFT ₃₃ , TFT ₄₃ , and TFT ₁₄ are turned on, and the output voltage 3/16 V _DD is output to the output terminal OP. Similarly, when the input code “1,0,1,1” is input, the N-channel transistors TFT ₁₁ , TFT ₂₁ , TF
T ₃₁ , TFT ₄₁ , TFT _{12, TFT 22} , TFT ₃₂ , TF
T ₄₂ , TFT ₁₃ , TFT ₂₃ , TFT ₃₃ , TFT ₄₃ , TF
The T ₁₄ and TFT ₂₄ are turned on, and the output voltage 2 / 16V _DD is output to the output terminal OP. Similarly, when the input code “0, 1, 1, 1” is input, N-channel transistors TFT ₁₁ , TFT ₂₁ , TFT ₃₁ , TFT ₄₁ , TF.
T ₁₂ , TFT ₂₂ , TFT ₃₂ , TFT ₄₂ , TFT ₁₃ , TF
T ₂₃ , TFT ₃₃ , TFT ₄₃ , TFT ₁₄ , TFT ₂₄ , TF
T ₃₄ turns on, and the output voltage OP is 1/16
V _DD is output. Similarly, input code "1, 1,
1, 1 ”is input, all the N-channel transistors TFT _{11 to} TFT ₄₄ are turned on, and the output terminal OP becomes the ground potential GND. Only when the input code "1, 1, 1, 1" is input, the output of the AND gate AND1 becomes "1" and the P-channel transistor TFT0 is turned off.

In the above embodiment, the case of 16-value output has been described. However, by enlarging the matrix part and adding a peripheral decoder circuit corresponding thereto, it is possible to realize a multi-value output circuit having more output values. Is. Further, in the above embodiment, the P-channel transistor TFT0 is connected between the power source and the output terminal, but the P-channel transistor TFT0 may be another electronic element such as a resistor. Next, a multi-gradation display device using the above multi-value output circuit will be described.

FIG. 5 shows a drive circuit of an active matrix liquid crystal display panel integrated with a drive circuit according to the present invention. That is,
The active matrix section 5 includes data lines L201, L
202 ... And a power supply voltage V _COM , a thin film transistor TFT and a load capacitor LC are connected in series, and the gate of each thin film transistor TFT has a gate line L301,
Connected to L302 .... This gate line L30
1, L 302 ... Are connected to the address bus drive unit 4, and a horizontal synchronizing signal φ _H is applied to the address bus drive unit 4 from an external circuit.

On the other hand, the video signal is input from the external circuit to the input end of the 4-bit A / D conversion circuit 7 of the data bus driving unit 1, and the output end of the 4-bit A / D conversion circuit 7 is supplied with each signal. Bit lines are connected. Each bit line is connected to the data lines L201, L202, ... Through the latch circuit LA and the multi-value output circuit R in series.

Further, the clock signal φ _S is inputted from the external circuit to the data shift register 6 of the data bus driving unit 1, and the strobe signal is added from the data shift register 6 to each of the latch circuits LA. The multi-value output circuit R and the latch circuit LA each form a 4-bit DA conversion circuit.

That is, the DA conversion circuit weights the voltage of each bit of data through the multi-valued output circuit R, and outputs GND, 1/1 as a pixel signal which is an output.
16V _DD to 15 / 16V _DD can be obtained, and the resolution becomes 1/16.

Then, first, the video signal is converted into a digital signal by the AD conversion circuit 7 and output to the DA conversion circuit. The DA conversion circuit is an active matrix as a pixel signal of an analog signal by a circuit in which the digital signal input from the AD conversion circuit 7 is connected to each latch circuit LA and its output and the multilevel output circuit R correspondingly. The data is output to the respective data lines L201, L202, ... Of the unit 5, and the address bus drive unit 4 outputs the gate lines L301, L302.
Is controlled to transmit a pixel signal to the selected pixel, that is, the thin film transistor TFT. In order to increase the resolution, the number of bits of the AD conversion circuit 7 and the DA conversion circuit may be increased.

[0017]

As described above, according to the present invention, the electronic element connected between the power source and the output terminal and the electronic element connected in parallel between the output terminal and the ground potential are turned on to output the respective output signals. A multi-value output circuit of a static circuit is configured by a plurality of switching transistors that drop the voltage output to the end and a selection circuit that selectively turns on and off the switching transistors in response to an input signal. As a result, the reproducibility of the characteristics can be improved, the restriction from the leakage current can be reduced, and the manufacturing yield can be improved. Therefore, it is possible to obtain a multi-valued output circuit that can easily obtain a desired multi-valued output even with a transistor such as a polysilicon TFT having a relatively large variation in characteristics and a large leak current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a multilevel output circuit of the present invention.

FIG. 2 is a circuit diagram of each switching circuit cell S _ij arranged in the matrix section of FIG.

FIG. 3 is an explanatory diagram showing a relationship between an input code and an output voltage of the multilevel output circuit of FIG.

FIG. 4 is an equivalent circuit diagram showing the operating principle of the multilevel output circuit of FIG.

5 is a configuration explanatory view showing an embodiment of a multi-gradation display device of the present invention using the multi-value output circuit of FIG.

[Explanation of symbols]

AND1-AND5 ... AND gate, OR1-OR3 ...
OR gate, I ... inverter, S11～S44 ... switching circuit cell, TFT ₁₁ ~TFT ₄₄ ... N-channel transistor, TFT0 ... P-channel transistor, 1 ... data bus driver, 4 ... address bus driver, 5 ... active matrix unit.

Claims (2)

[Claims] 1. An electronic element connected between a power source and an output terminal, and a plurality of electronic elements connected in parallel between the output terminal and a ground potential and each of which drops a voltage output to the output terminal by an ON operation. A multilevel output circuit comprising a switching transistor and a selection circuit for selectively turning on and off the switching transistor in response to an input signal. 2. A data bus driver having a multi-value output circuit according to claim 1, which converts a digital signal converted from a video signal into a voltage-weighted multi-gradation analog pixel signal, and the data bus. A multi-gray scale display device comprising: an active matrix section in which a multi-gray scale analog pixel signal from a drive section is applied to a data line and driven by an address bus drive section.