JPH11266151A - Potential conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a potential conversion circuit for having a signal processing circuit, which is operated by a rocking power source controlled by a logical signal of the signal processing circuit which is operated by a constant potential power source. SOLUTION: This device is equipped with a first MOS transistor 1, a second MOS transistor 2, a first load element 3 and a second load element 4. The gate terminal of this first MOS transistor 1 is connected to the source terminal of the second MOS transistor 2, the drain terminal is connected to a rocking power source through the first load element 3, the source terminal is connected to the gate terminal of the second MOS transistor 2, and the gate terminal of the second MOS transistor 2 is connected to the source terminal of the first MOS transistor 1. Then, the drain terminal is connected to the rocking power source through the second load element 3, the source terminal is connected to the gate terminal of the first MOS transistor 1, and the gate terminals of the first MOS transistor 1 and the second MOS transistor 2 are set as input for a potential conversion circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit which operates with a fluctuation power supply whose potential fluctuates with respect to the ground, and which operates with a more gradual change or a steady potential with respect to the ground. The configuration and use of a potential conversion circuit or a level shifter circuit for exchanging logic signals between signal processing circuits, and particularly to a method of propagating a logic signal for controlling a scanning line driver of a liquid crystal display device performing time-division matrix display. .

[0002]

2. Description of the Related Art Hitherto, a high driving voltage of 50 V to 150 V has been required for driving a display element or an actuator element, which makes it difficult to integrate a driving circuit into an integrated circuit or increases the cost due to an increase in chip area. I was However, adopting the oscillating power supply driving method has developed a technology for lowering the operating voltage of the semiconductor integrated circuit to about half, thereby facilitating integration into an integrated circuit and reducing the cost. Here, it is desirable to use a control signal generated by a low-voltage logic circuit as a control signal for controlling the drive circuit using the oscillating power supply in terms of ease of use. Here, in order to control a signal processing circuit using an oscillating power supply with a low-voltage control signal, it is necessary to use a potential conversion circuit corresponding to the oscillating power supply. First, an oscillating power supply will be described, and then a conventional example of a potential conversion circuit will be described.

FIG. 2 is a timing chart of a scanning line driver of a liquid crystal display device for performing a matrix display of a time division number n. The scanning line driver uses a row scanning clock LP (Line
Pulse) and a control signal FLM (F
(first line marker), the scanning signals are sequentially output to the scanning line outputs S1 to Sn for n rows. In general, an alternating drive in which the pulse polarity of the output scanning signal is inverted for each row in order to prevent polarization due to application of a direct current component to the liquid crystal element. Here, the potential of the positive pulse is V1, the potential of the negative pulse is V4, and the scanning line potential at the time of selecting the ratio is VM. A positive pulse is always output when an odd scan line is selected, and a negative pulse V4 is output when an even scan line is selected. In the case of a liquid crystal display device of about 640 divisions, about 50 V is applied between V1 and V4, and VM is 25
Since the voltage is normally set to about V, the maximum voltage handled by the scanning line driver is required to be as high as 50 V, which is a considerably high withstand voltage. However, looking closely at the period in which the odd-numbered scanning lines are selected, the highest potential of all the scanning line outputs is V1 and the lowest potential is VM. On the other hand, the maximum potential is VM and the minimum potential is V4 also during the period in which the even-numbered scanning line is selected. Therefore, it can be seen that the withstand voltage that the drive circuit itself really needs can operate at a potential between V1 and VM or a potential between VM and V4. Therefore, power supplies VDD and VSS that swing in a rectangular or trapezoidal shape with respect to the ground potential are used. Shaking power supply V
In the period during which a positive pulse is required for the scanning line output, DD swings the swing power supply to the high potential side, and becomes equal to V1. On the other hand, during the period in which a negative pulse is required,
To match. At this time, the potential between VDD and VSS is always kept constant, and the high potential level of the logic signal for controlling the row driver is V2, the constant potential level is V3, and the VSS when swinging to the high potential side is V3. VDD when swinging to the low potential side is made equal to V2. Such fluctuation power supplies VDD and VSS are prepared, and the scanning line driver operates using the fluctuation power supplies VDD and VSS as power supplies.
That is, VDD is output to the scanning line output during the odd scanning line selection period requiring a positive pulse, VSS is output to the scanning line output during the even scanning line selection period requiring a negative pulse, and VM is output during the other non-selection periods. The scanning line driver itself handles the potentials of V1 to V3 or V2 to V4, and the scanning line driver outputs V1 to V1.
V4 potential can be supplied. By using such a swing power supply, the withstand voltage required for the drive circuit can be reduced to about half.

FIG. 3 shows a potential relationship required for a potential conversion circuit corresponding to an oscillating power supply. The line pulse LP and the first line marker are control signals for externally controlling the scanning line driver, and have logical levels of a high potential side V2 and a low potential side V3. In contrast, the swing power supply VD
LP and LPM need to be converted to LP 'and FLM', respectively, inside the scanning line driver operating at D and VSS. During the period when the oscillating power supply oscillates to the high potential side, the high potential side level V2 of the control signal is changed to V1, and conversely, during the period when the oscillating power supply oscillates to the low potential side, the low potential side level V3 of the control signal is used.
Needs to be changed to V4 depending on the rocking state.

[0005]

In order to input a control signal to the logic circuit of the swing power supply operation, a large amplitude signal having the same maximum potential and the lowest potential of the logic circuit as viewed from the ground level of the swing power supply operation is used. It is technically possible to create a fixed power supply circuit outside the swing power supply circuit and connect it to the input terminal of the swing power supply current circuit. However, in the structure of a normal IC, if the output signal potential of the external level conversion circuit is not between the power supply potentials of the integrated circuit of the swing power supply operation, the protection circuit of the swing power supply operation IC is activated, and the current consumption increases. Is generated. High voltage power supply and high voltage operation logic amplitude amplification that output the logic amplitude from the highest power supply to the lowest power supply of the oscillating power supply even if the current increase in the protection circuit is prevented by addressing the protection circuit current increase problem Circuits are required, which results in increased power consumption and increased circuit costs. When the oscillating potential changes in a pulsed or trapezoidal shape, a method of forming a logic potential level conversion circuit of a constant potential power supply operation at a high potential phase or a low potential phase where the logic value potential does not change can be used. However, it is not easy to configure a simple circuit for transmitting information from the logic level of the fixed potential system to the logic level of the fluctuating potential system or transmitting without noise in the reverse direction during the phase in which the oscillating potential is fluctuating.

[0006]

In order to achieve the above object, a potential conversion circuit according to the present invention comprises a swing power supply circuit in which a ground potential fluctuates while maintaining a constant potential difference, and a constant potential power supply circuit in which a ground potential is constant. A first signal processing circuit for dual power supply operation and a second signal processing circuit for operation with a constant potential power supply having a constant ground potential, wherein the second signal processing circuit is provided with a constant potential power supply. The first logic information consisting of the ground potential is transmitted to the first signal processing circuit, and the first dual power supply signal processing circuit is provided with a first MOS transistor and a second M transistor.
An OS transistor, a first load element, and a second load element, wherein a gate terminal of the first MOS transistor is connected to a source terminal of the second MOS transistor, and a drain terminal is connected through the first load element. A source terminal connected to the gate terminal of the second MOS transistor, a gate terminal of the second MOS transistor connected to a source terminal of the first MOS transistor, and a drain terminal connected to the source terminal of the first MOS transistor. A source terminal connected to the gate terminal of the first MOS transistor, and a logic information signal input to the second signal processing circuit is connected to the gate terminal of the first MOS transistor. A logic information signal having a logic opposite to that of the logic information signal is applied to the gate terminal of the second MOS transistor, The potential generated in the load element or said second load element and the logic signal output of the first signal processing circuit,
The logic signal output is controlled by a logic signal of the second signal processing circuit at an arbitrary phase.

Further, the potential conversion circuit of the present invention is a first signal of a dual power supply operation having both a fluctuation power supply circuit in which a ground potential fluctuates while maintaining a constant potential difference and a constant potential power supply circuit having a constant ground potential. Processing circuit, and a second signal processing circuit that operates with a constant potential power supply having a constant ground potential, wherein the second signal processing circuit transmits first logic information consisting of a constant potential power supply and a ground potential to the first logic information. The logic information is transmitted to one signal processing circuit, and the first dual power supply signal processing circuit includes a first MOS transistor, a second MOS transistor, a first load element, and a second load element. , A gate terminal of the first MOS transistor is connected to a source terminal of the second MOS transistor, a drain terminal is connected to an oscillating power supply through the first load element, and a source terminal is connected to the second MOS transistor. Gate edge , The gate terminal of the second MOS transistor is connected to the source terminal of the first MOS transistor, the drain terminal is connected to the oscillating power supply through the second load element, the source terminal is the first MO
The logic information signal connected to the gate terminal of the S transistor and input to the second signal processing circuit is applied to the gate terminal of the first MOS transistor, and the potential when the logic information signal is true logic and the potential A potential corresponding to the middle of the potential at the time of logic is applied to the gate terminal of the second MOS transistor, and the potential generated at the first load element or the second load element is determined by the logic of the first signal processing circuit. A signal output, wherein the logic signal output is controlled at an arbitrary phase by a logic signal of the second signal processing circuit.

Further, in the potential conversion circuit according to the present invention, the first load element and the second load element may be connected to a third MOS transistor provided on a substrate having a polarity opposite to that of the first MOS transistor. Four MOS transistors, and the gate terminal of the third MOS transistor is connected to the second MOS transistor.
The drain terminal of the S transistor is connected, the drain terminal is connected to the drain terminal of the first MOS transistor, the source terminal is connected to the oscillation power supply, and the gate terminal of the fourth MOS transistor is connected to the first MOS transistor. Connected to the drain terminal of the second MO.
The drain terminal of the S transistor is connected, and the source terminal is connected to an oscillating power supply.

Further, in the potential conversion circuit according to the present invention, the first signal processing circuit is formed on the same semiconductor integrated circuit chip, and information from the second signal processing circuit provided outside is input to the power conversion circuit. It is characterized in that the potential is converted into logic information consisting of a potential and the first signal processing circuit is controlled.

[0010] Depending on the level of the potential of the input signal and the level of the potential of the inverted input signal, a current flows on either side of the two load elements, causing a voltage drop. This voltage drop can be used as a logic signal. Even if the fluctuating power supply itself fluctuates, the level of the potential of the input signal and the level of the potential of the inverted input signal do not change, so that it is possible to cope with the fluctuation power supply. By using the intermediate potential of the logical amplitude of the input signal instead of the inverted input signal, it is possible to substitute for the inverted signal. In addition, by using a cross circuit of a MOS transistor as a load element, higher-speed operation can be performed.

[0011]

FIG. 1 shows an embodiment of a potential conversion circuit according to the present invention. N-type MOS (Metal Oxi
de Semiconductor) transistor 1,
2 and a resistance element is used as a load element.
The high-potential-side variable power supply VDD is 25 when it swings to a high potential.
V, 5 V when swinging to the low potential side, and the low potential side fluctuation power supply VSS is 0 V when swinging at the high potential, and −2 when swinging at the constant potential.
0V. The oscillation amplitude itself is 20V. A logic signal operating with a constant potential power supply of a constant potential is 5 at a high level.
V, 0 V at low level. A logic signal IN externally supplied to control the signal processing circuit of the oscillation power supply operation is supplied to the gate terminal G of the transistor 1 and the source terminal S of the transistor 2 at the same time. INB is the gate terminal G of transistor 1.
To the source terminal S of the transistor 1 at the same time. When the logic signal 5 has a higher potential than the inverted logic signal 6, the transistor 1 is kept at a higher potential than the gate potential and the source potential, so that the transistor is turned on.
A current flows from the variable power supply to the load resistance 2, and a potential drop occurs in the load resistance element. On the other hand, since the gate potential of the transistor 2 is lower than the source potential, the transistor remains off and no current flows to the load element. Since the circuit configuration is symmetrical with respect to the input signal and the inverted input signal, when the inverted logic signal 6 has a higher potential than the logic signal 5, the transistor 2 is turned on, and a current flows through the load resistance element 1. Flows. By appropriately setting the resistance value of the load resistance element, a logic signal having a potential amplitude from the fluctuation power supply VDD to the low-level logic signal potential 0 V can be obtained at the output terminals 7 and 8. As described above, the potential conversion circuit of the present invention is configured to perform the potential conversion by comparing the potentials of the logic signal and the inverted logic signal.

FIG. 2 shows a P-type MOS in place of a resistance load element.
An example in which cross loads 12 and 13 of transistors are used is shown. Further, when the swing power source swings to the lower potential side, it is not possible to cope with the situation as it is. Therefore, the amplitude of the logic signal may be expanded from VDD to VSS by using the second potential conversion circuit 9 having a cross configuration which is generally used. It is possible. Output terminals 14 and 15 have logic amplitude VDD.
~ VSS logic signal is obtained, and the CM
It is possible to directly drive the signal processing circuit having the OS configuration.

FIG. 3 shows an operation timing chart. When the logic signal 5 and the inverted logic signal 6 are given, logic signals 7 and 8 having an amplitude between VDD and V3 are obtained, and a logic signal having an amplitude from VDD to VSS is obtained by the second potential conversion circuit.

When applied to a scanning line driver, it is possible to use an intermediate potential power supply VM which is the output potential of the scanning line when not selected, instead of using the inverted logic signal. In the scanning line driver, the intermediate potential power supply is used in accordance with the intermediate voltage of the logic amplitude of the control signal. Therefore, the potential of the logic signal can be converted by comparing the potential with the logic signal potential. .

[0015]

The potential conversion circuit of the present invention can transmit data at an arbitrary phase to the swing power supply operation logic circuit. This makes it possible to arbitrarily control and create the drive waveform of the high-voltage output drive circuit of the swing power supply operation according to the drive information of the external low-constant voltage circuit. With the oscillating power supply configuration, it is possible to obtain a voltage amplitude output larger than the power supply voltage amplitude of the oscillating operation integrated circuit. For example, assuming that the low constant voltage circuit voltage is a logic circuit of 5 V, the swing power supply voltage is 25 V, the swing voltage is 20 V, the minimum swing positive potential is +5 V, and the maximum swing negative potential is 0 V. , 25V operation, it is possible to output a drive signal having a logic amplitude of 45V from -20V to + 25V. By controlling the output phase at an arbitrary phase, a complex drive waveform can be output.

Further, since the potential conversion circuit of the present invention can be realized with a small number of elements, the area of the semiconductor integrated circuit is reduced and the cost is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a potential conversion circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a potential conversion circuit when a MOS transistor is used as a load element.

FIG. 3 is a timing chart of the potential conversion circuit in the embodiment of the present invention.

FIG. 4 is a timing chart illustrating the operation of a scanning line driver.

FIG. 5 is a diagram illustrating a conversion level required for a potential conversion circuit.

[Explanation of symbols]

1, 2 First and second MOS transistors 3, 4 First and second load elements 5, 6 Logical input signal and inverted logical input signal 7, 8 Output of potential conversion circuit 9 Second potential conversion circuit 10, 11 MOS transistor constituting a second potential conversion circuit 12, 13 Load MOS constituting a second potential conversion circuit
Transistors 14 and 15 Output of second potential conversion circuit VDD High-potential-side fluctuation power supply VSS Low-potential-side fluctuation power supply LP, FLM Control signal for driving scan line driver VM Scan line output potential when VM is not selected V1 High-potential fluctuation High potential side power supply potential V2 High potential side power supply potential at low potential fluctuation V3 Low potential side power supply potential at high potential fluctuation V4 Low potential side power supply potential at low potential fluctuation

Claims (4)

[Claims] 1. A first signal processing circuit of a dual power supply operation, comprising both a swing power supply circuit in which a ground potential fluctuates while maintaining a constant potential difference, and a constant potential power supply circuit having a constant ground potential, and a ground potential. Comprises a second signal processing circuit operable with a constant constant-potential power supply, wherein the second signal processing circuit logically transmits first logic information comprising a constant-potential power supply and a ground potential to the first signal processing circuit. A first MOS transistor, a second MOS transistor, a first load element, and a second load element, wherein the signal processing circuit has a first MOS transistor; The gate terminal of the second MOS transistor is connected to the source terminal of the second MOS transistor, the drain terminal is connected to the oscillating power supply through the first load element, the source terminal is connected to the gate terminal of the second MOS transistor, Second MOS A gate terminal of the transistor is connected to a source terminal of the first MOS transistor, a drain terminal is connected to an oscillating power supply through the second load element,
The source terminal is connected to the gate terminal of the first MOS transistor, and the logical information signal input to the second signal processing circuit is applied to the gate terminal of the first MOS transistor. A logic information signal of reverse logic is applied to the gate terminal of the second MOS transistor, and a potential generated in the first load element or the second load element is used as a logic signal output of a first signal processing circuit. A potential conversion circuit for a logic circuit signal having a structure for controlling a logic signal output at an arbitrary phase by a logic signal of the second signal processing circuit. 2. A first signal processing circuit for dual power supply operation, comprising both a swing power supply circuit in which a ground potential fluctuates while maintaining a constant potential difference and a constant potential power supply circuit having a constant ground potential, and a ground potential. Comprises a second signal processing circuit operable with a constant constant-potential power supply, wherein the second signal processing circuit logically transmits first logic information comprising a constant-potential power supply and a ground potential to the first signal processing circuit. A first MOS transistor, a second MOS transistor, a first load element, and a second load element, wherein the signal processing circuit has a first MOS transistor; The gate terminal of the second MOS transistor is connected to the source terminal of the second MOS transistor, the drain terminal is connected to the oscillating power supply through the first load element, the source terminal is connected to the gate terminal of the second MOS transistor, Second MOS A gate terminal of the transistor is connected to a source terminal of the first MOS transistor, a drain terminal is connected to an oscillating power supply through the second load element,
The source terminal is connected to the gate terminal of the first MOS transistor, the logical information signal input to the second signal processing circuit is applied to the gate terminal of the first MOS transistor, and the logical information signal is set to true. A potential corresponding to an intermediate between the potential at the time of logic and the potential at the time of false logic is applied to the gate terminal of the second MOS transistor, and the potential generated at the first load element or the second load element is reduced to the first load element. A potential conversion circuit for a logic circuit signal, comprising: a logic signal output of one signal processing circuit, wherein the logic signal output is controlled at an arbitrary phase by a logic signal of the second signal processing circuit. 3. The first load element and the second load element include a third MOS transistor and a fourth MOS transistor provided on a substrate having a polarity opposite to that of the first MOS transistor. The gate terminal of the third MOS transistor is connected to the drain terminal of the second MOS transistor, the drain terminal is connected to the drain terminal of the first MOS transistor, the source terminal is connected to the oscillation power supply, The gate terminal of the fourth MOS transistor is connected to the drain terminal of the first MOS transistor, the drain terminal is connected to the drain terminal of the second MOS transistor, and the source terminal is connected to an oscillating power supply. The potential conversion circuit according to claim 2 or claim 2. 4. The first signal processing circuit is formed on the same semiconductor integrated circuit chip, and information from the second signal processing circuit provided externally is input to generate logical information consisting of an oscillating power supply potential. 3. The potential conversion circuit according to claim 1, wherein the potential conversion circuit converts the potential and controls the first signal processing circuit.