JPH05102857A - D/a converter - Google Patents

Abstract

PURPOSE:To provide the digital/analog (D/A) converter which can obtain high resolution while maintaining monotonicity without using the resistor of a high resistance ratio. CONSTITUTION:A second D/A circuit to be driven based on the digital data of high-order bits is equipped with a 2R circuit 8 composed of plural resistors. Each of resistors is a resistor in which two second resistance elements rMOa and rMOb (rM1a and rM1b, rM2a and rM2b) symmetrically arranged with a reference line RL as a center are connected in series. Therefore, the error of the resistance element is canceled at the 2R circuit 8. Thus, the high resolution can be obtained while maintaining monotonousness without using the resistor of the high resistance ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter for converting a binary digital signal into an analog signal.

[0002]

2. Description of the Related Art As a voltage-applying digital-analog converter, an R-2R system is conventionally known. FIG. 15 shows an 8-bit digital-analog converter adopting such an R-2R system.

As shown in FIG. 1, this digital-analog converter has eight changeover switches S _{0 to} S corresponding to each bit of an 8-bit digital signal to be DA converted.
₇ are provided respectively. Each changeover switch S _{0 to} S
One switching contact _7, together with the reference voltage V _REF is connected to the first input terminal 1 is applied, the other switching contact is connected to the second input terminal 2 to the ground potential GND is applied ing. Between the second input terminal 2 and the output terminal 3, one resistor having a resistance value of 2R and seven resistors having a resistance value of R are connected in series. Further, the node between the resistors and the changeover switch S _0.
Between the common contact of to S _7, 8 single resistor having a resistance value of 2R are connected.

In this digital-analog converter, each of the changeover switches S _{0 to} S ₇ has a first changeover contact to which a reference voltage V _REF is applied and a ground potential GND according to the state of the corresponding bit of the digital signal. Is switched between the second switching contacts to which is applied, and an analog signal having a voltage value corresponding to the digital signal is output from the output terminal 3.

[0005]

As described above, the conventional R
-The digital-analog converter adopting the -2R system is
It has an advantage that the number of elements such as resistors and changeover switches S _{0 to} S ₇ is small and control is simple. But,
On the other hand, it has the following drawbacks. That is, in reality, the resistance values of the resistors vary, and the output change of the analog signal with respect to the change of the digital data includes an error. In the conventional digital-analog converter, the error included in the output change of the analog signal has a large effect on the change of the digital data for the most significant bit.
In order to obtain high resolution while maintaining monotonicity, very high resistance ratio accuracy is required.

The present invention has been made to solve the above problems, and provides a digital-analog converter that can obtain high resolution while maintaining monotonicity without using a resistor having a high resistance ratio. With the goal.

[0007]

The invention according to claim 1 is the first
A plurality of first resistance elements, which are formed in the conductive type semiconductor region in the first direction and have the same shape and the same size as each other, are electrically connected to form an R-2R circuit. And a first digital / analog circuit, which are connected in series and are driven based on digital data of lower bits, and have the same shape and the same size as the first resistance element in the semiconductor region in the first direction. A plurality of second resistance elements formed of the second conductivity type semiconductor diffusion layer formed in
A second digital / analog circuit that is electrically connected to form a circuit and that is driven based on digital data of upper bits, and outputs a binary digital signal composed of the upper bits and the lower bits. A digital-to-analog converter for converting into an analog signal, wherein, in order to achieve the above object, the second digital-to-analog conversion circuit has a reference line extending in a second direction perpendicular to the first direction. Is the center of symmetry, and the two second resistance elements symmetrically arranged are connected in series to form a plurality of resistors.

According to a second aspect of the invention, in addition to the first aspect of the invention, at least one or more resistance element pairs among the plurality of first resistance elements are symmetrically arranged with respect to the reference line.

According to a third aspect of the present invention, a plurality of resistors, each of which is made of a semiconductor layer and whose resistance value is set to R, are arranged at predetermined intervals in the first direction, and the plurality of resistors are electrically connected. The R-2R circuit is configured by being connected to
At least the resistor connected to the output terminal is arranged in the first region of the semiconductor substrate, and the remaining resistors are arranged in the second region of the semiconductor substrate and driven based on the lower bit digital data. A plurality of first digital / analog circuits and a resistor made of a semiconductor layer whose resistance value is set to R are arranged in the first direction with a predetermined space between them, and the plurality of resistors are electrically connected to each other. The two resistors, which are connected to each other to form a 2R circuit and are connected in series, are arranged symmetrically with a reference line extending in a second direction perpendicular to the first direction as a center of symmetry, and A second digital-analog circuit is provided in which a plurality of resistors are arranged in a third region of the semiconductor substrate located between the first and second regions and which is driven based on digital data of upper bits. That.

[0010]

According to the first aspect of the invention, the second digital-analog circuit driven on the basis of the higher-order bit digital data has two second resistance elements connected symmetrically with respect to the reference line as the center of symmetry. Since the second digital / analog circuit is composed of a plurality of resistors, the error of the resistance element is canceled. Therefore, high resolution can be obtained while maintaining monotonicity without using a resistor having a high resistance ratio.

According to the invention of claim 2, in addition to the invention of claim 1, at least one or more resistance element pairs among the plurality of first resistance elements are arranged symmetrically with respect to the reference line. Therefore, even in the first digital / analog circuit, the error of the resistance element is partially canceled, and a higher resolution can be obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The circuit configuration of a digital-analog converter according to the present invention and the layout of the constituent elements (resistive elements) of the circuit will be disclosed below, and the details of the present invention will be described.

A. Circuit Configuration of Digital-Analog Converter and Its Effect FIG. 1 shows an 8-bit digital-analog converter according to an embodiment of the present invention.

This digital-to-analog converter converts a binary digital signal consisting of a lower bit having a bit number "6" and an upper bit having a bit number "2" into an analog signal. It comprises a first digital-analog conversion circuit 4 driven on the basis of bit digital data, and a second digital-analog conversion circuit 5 driven on the basis of upper 2-bit digital data.

The first digital-analog conversion circuit 4 is provided with six changeover switches S _{0 to} S ₅ which can be changed over according to the state of the lower 6-bit digital data. One of the switching contacts of each of the changeover switches S _{0 to} S ₅ is connected to the first input terminal 1 to which the reference voltage V _REF is applied, and the other switching contact of the second input to which the ground potential GND is applied. Each is connected to the input terminal 2. Further, between the second input terminal 2 and the output terminal 3, one resistor R ₁ having a resistance value of 2R and R
Six resistors R _{2 to} R ₇ having the resistance value of are connected in series. Then, 2R is provided between one end side of the resistors R _{2 to} R ₇ and the common contact of the changeover switches S _{0 to} S _5.
The six resistors R _{8 to} R ₁₃ having the resistance value of are respectively connected. Thus, the resistors R _{2 to} R ₁₃ cause R-2R.
The circuit 6 is configured and the changeover switches S _{0 to} S ₅
The first switch group 7 is configured by.

On the other hand, the second digital-analog conversion circuit 5 has three change-over switches S _M0 , which can be changed over in accordance with the state of the upper 2-bit digital data.
S _M1 and S _M2 are provided. Each changeover switch S _M0 , S
One of the switching contacts of _M1 and S _M2 is connected to the first input terminal 1 to which the reference voltage V _REF is applied, and the other switching contact is connected to the second input terminal GND to which the ground potential GND is applied. To be done. Then, each changeover switch S _M0 , S
Three resistors R _M0 , R _M1 , and R _M2 each having a resistance value of 2R are connected between the common contact of _M1 and S _M2 and the output terminal V _OUT . Thus, the resistors R _M0 , R _M1 , and R _{M2 form the} 2R circuit 8, and the changeover switch S
The second switch group 9 is composed of _M0 , S _M1 and S _M2 .

In each of the changeover switches S _{0 to} S ₅ of the first switch group 7, the corresponding lower 6 bits are "1".
In the case of, while being switched to the reference voltage V _REF side,
When it is "0", it is switched to the ground potential GND side.
Further, the changeover switches S _M0 , S _M1 ,
S _M2 is switched as shown in the table below according to the state of the upper 2 bits.

[0018]

[Table 1]

In the table, B ₇ represents the most significant bit, and B ₆
Represents the next significant bit. Further, GND denotes changeover switch S _M0, S _M1, S _M2 is switched to the ground potential GND side, V _{RE F} is that is switched to the reference voltage V _REF side.

The operation of this digital-analog converter will be described below in comparison with the conventional digital-analog converter shown in FIG.

Now, in the digital-analog converter shown in FIG. 15, for example, the changeover switch S ₃ has a reference voltage V.
Switched to the _REF side and the other changeover switches S _{0 to} S ₂ , S
Consider a case where _{4 to} S ₇ are switched to the ground potential GND side. In this case, since the combined resistance value on the left side of point C in FIG. 15 is R, the combined resistance value on the left side of point D is 2
It becomes R. On the other hand, the resistance value above the point D is also 2R.
Therefore, the combined resistance value becomes R when viewing both the upper side and the left side of the point D. As a result, the voltage at point D becomes half the voltage at point E. The above relationships are established at all points A to H in FIG.

Therefore, the output voltage V _OUT of the analog-to-digital converter is generally expressed by the following equation.

[0023]

[Equation 1]

Here, b _{0 to} b ₇ are respective changeover switches S
_The numbers _{0 to} S ₇ are “1” when connected to the reference voltage V _REF side and “0” when connected to the ground potential GND side.

In this way, an 8-bit digital-analog converter is realized by switching each of the changeover switches S _{0 to} S ₇ according to the state of the corresponding bit of the digital signal.

On the other hand, the digital-analog converter of the present embodiment shown in FIG. 1 can be rewritten as shown in FIG. Here, V ₁ represents the voltage on the left side of point G in FIG.
Similarly, ₂ represents the voltage on the right side of point G.

The voltage V ₁ is obtained by the same method as the equation 1, and is represented by the following equation.

[0028]

[Equation 2]

V ₂ is represented by the following equation.

[0030]

[Equation 3]

Here, b _M0 , b _M1 and b _M2 are connected to "1" when the changeover switches S _M0 , S _M1 and S _M2 are connected to the reference voltage V _REF side and are connected to the ground potential GND side. Sometimes it is set to "0".

Therefore, the output voltage V _OUT is expressed by the following equation using Thevenin's theorem.

[0033]

[Equation 4]

Substituting equations 2 and 3 into equation 4,

[0035]

[Equation 5]

B ₆ and b ₇ of the _{equation 1} and b _M0 , b _{M1 of} the _equation 5
b The following table _shows the relationship of _M2 .

[0037]

[Table 2]

That is, 2 ⁶ · b ₆ +2 ⁷ · b ₇ = 2 ⁶ · (b _M0 + b _M1 + b _M2 )

Next, the point where the monotonicity is improved by the digital-analog converter of the present embodiment will be described.
FIG. 3 shows the resistance value R of each resistor in the conventional circuit of FIG.
2R is shifted by (1 + δ), and FIG. 4 shows the resistors R _{1 to} R ₁₃ , R in the circuit of the present embodiment shown in FIG.
Shows a state where the resistance value of the _{M0 ~R M2} R, 2R are shifted by (1 + δ).

In the conventional circuit of FIG. 3, the point where monotonicity is most likely to be disturbed is when the changeover switch S ₇ having the largest weight is changed over. That is, b ₇
= 0, b ₆ = b ₅ = b ₄ = b ₃ = b ₂ = b ₁ = b ₀ = 1
From the state of, b ₇ = 1, b ₆ = b ₅ = b ₄ = b ₃ = b ₂
= B ₁ = b ₀ = 0.

Digital signals (b ₇ , b ₆ , b ₅ ,
b ₄ , b ₃ , b ₂ , b ₁ , b ₀ ) is (1,0,0,0,0,0,0,0)
The circuit of FIG. 3 is represented as in FIG.

Impedance Z seen from point A to the left
_If we ask for _A, we get:

[0043]

[Equation 6]

Here, when δ ₂ and δ ₁ << 1 and the terms of the second or higher order are ignored (Newton's first-order approximation), Z _A is as follows.

[0045]

[Equation 7]

Similarly, the impedance Z _B as seen from the point B to the left is as follows.

[0047]

[Equation 8]

Similarly, the impedance Z _C viewed from the point C to the left is as follows.

[0049]

[Equation 9]

This equation is initially 1/2 for the resistance of 2R (contact-to-ground resistance), and decreases 1/4 as it goes to the lower bit side of the first stage. On the other hand, with respect to the resistance of R (resistance between nodes), it is 1/4 at first and decreases by 1/4 as it goes to the lower bit of one stage.

Therefore, the impedance Z _G viewed from the point G to the left is as follows.

[0052]

[Equation 10]

Therefore, the impedance Z _H viewed from the point H to the left is as follows.

[0054]

[Equation 11]

Therefore, the digital signal (1,0,0,0,0,
Output voltage V _OUT (1,0,0,0,0, when 0,0,0) is given
0,0,0) is as follows.

[0056]

[Equation 12]

On the other hand, the digital signal is (0,1,1,1,1,1,1,
When given in 1), the circuit of FIG. 3 is represented as in FIG.

Using the principle of superposition, the output voltage of the circuit of FIG. 6 is the output voltage V _OUT7 of the circuit of FIG. 7 minus the output voltage V _OUT8 of the circuit of FIG.

Then, the output voltage V _OUT7 of FIG. 7 is _calculated as follows.

V _OUT7 = V _REF −V _OUT (1,0,0,0,0,0,0,0) Substituting equation 12 into this,

[0061]

[Equation 13]

Further, when the output voltage V _OUT8 in FIG. 8 is obtained,
It looks like this: In this case, the circuit of FIG.
With respect to the grounded state of (1 + δ _i ) (i = 1,2,4,6,8,10,12,14,16), the resistor 2R (1 + δ ₁ ) corresponding to 1 bit is connected to V _REF. Equivalent to. Therefore,

[0063]

[Equation 14]

It becomes However, δ _error is an error component caused by δ ₀ to δ ₁₅ .

Therefore, the output voltage of the circuit of FIG. 6, that is, the output voltage V _OUT (0,1,1) when the digital signal is given by (0,1,1,1,1,1,1,1) , 1,1,1,1,1,1) is the number 1
It can be expressed as follows using 3 and Equation 14.

[0066]

[Equation 15]

Therefore, V _OUT (1,0,0,0,0,0,0,0) and V _OUT
The difference voltage ΔV _OUT from _OUT (0,1,1,1,1,1,1,1,1) is
When calculated using 2 and Equation 15, the result is as follows.

[0068]

[Equation 16]

Here, δ _error is an extremely small value and can be ignored, and can be expressed as follows.

[0070]

[Equation 17]

Equation 17 shows that the digital signal is (0, 1, 1, 1, 1,
In order to show the change amount of the output voltage V _OUT when changing from (1,1,1) to (1,0,0,0,0,0,0), in the case of the conventional circuit of FIG.
It can be seen that monotonicity is hindered when δ ₁₆ becomes 1/2 ⁷ or more.

On the other hand, in the circuit of the embodiment of the present invention shown in FIG. 4, the point that monotonicity is most likely to be disturbed is when the changeover switches S _M0 , S _M1 and S _M2 having the largest weight are changed over. Is. That is, there are the following three cases.

(I) b _M2 = 0, b _M1 = 0, b _M0 = 0, b
_{From the state of 5} = b ₄ = b ₃ = b ₂ = b ₁ = 1, b _M2 =
0, b _M1 = 0, b _M0 = 1, b ₅ = b ₄ = b ₃ = b ₂ = b
_When changing to the state of ₁ = b ₀ = 0.

(Ii) b _M2 = 0, b _M1 = 0, b _M0 = 1, b
_{From the state of 5} = b ₄ = b ₃ = b ₂ = b ₁ = b ₀ = 1
_{M2 = 0, b M1 = 1} , b M0 = 1, b 5 = b 4 = b 3 = b 2
= B ₁ = b ₀ = 0.

(Iii) b _M2 = 0, b _M1 = 1 and b _M0 = 1 and b
_{From the state of 5} = b ₄ = b ₃ = b ₂ = b ₁ = b ₀ = 1
_{M2 = 1, b M1 = 1} , b M0 = 1, b 5 = b 4 = b 3 = b 2
= B ₁ = b ₀ = 0.

The amount of change in the output electrode V _{OUT in} these cases is approximately given by the following equations when obtained using the same method as that obtained in the conventional circuit of FIG.

In the case of (i):

[0078]

[Equation 18]

In case of (ii):

[0080]

[Formula 19]

In the case of (iii):

[0082]

[Equation 20]

As can be seen from Eqs. 18 to 20, in the circuit of the present embodiment, δ _M0 , δ _M1 , and δ _M2 are approximately 1
Monotonicity is hindered when the value exceeds / ²⁶ .

That is, the circuit of the embodiment of the present invention shown in FIG. 4 shows that the resistance ratio may be doubled in order to maintain monotonicity as compared with the conventional circuit of FIG.

As described above, the circuit of the present embodiment of FIG.
The monotonicity is easier to maintain as compared with the conventional circuit of FIG. 15. The reason is that in the circuit of FIG. 15, the change amount of the output voltage V _OUT due to the changeover of the changeover switch S ₇ is larger than that of the changeover switch S _0. In the circuit of FIG. 1, the output voltage V by switching the changeover switches S _M0 , S _M1 , S _M2 is 2 ⁷ times.
The change amount of _OUT is 2 ⁶ compared to those of the changeover switch S _0.
This is because it stays double.

Therefore, the changeover switches S _{0 to} S ₅ and the resistors R _{2 to} R of the first digital-analog conversion circuit 4 are arranged.
The number of ₁₃ is fixed according to the number of lower bits, and the changeover switch S _{M0 of} the second digital-analog conversion circuit 5 is set.
By increasing the numbers of ˜S _M2 and resistors R _Mo ˜R _M2 beyond the number of upper bits, monotonicity can be maintained without improving the resistance ratio accuracy.

Although the case of converting an 8-bit digital signal into an analog signal has been described above, in general,
When converting a digital signal in which the number of lower bits is N _L and the number of upper bits is N _U into an analog signal, the changeover switch of the first switch group 7 and the R-2R circuit 6 in the circuit of FIG. of R, resistor together with N _L pieces provided each 2R, respectively 2 ^Nu resistance of 2R of the switch and the 2R circuit 8 of the second switch group 9 -1
You only have to provide one. Then, the selector switches in the first switch group 7, in accordance with the state of a corresponding bit of the lower bits, respectively with is switched to the reference voltage V _{RE F} side and the ground potential GND side, is switched to the reference voltage V _REF side The number of changeover switches of the second switch group 9 may be determined according to the state of the upper bits.

In this way, the digital signal is converted to the lower N _L
When generally represented by bits and upper N _U bits, the circuit corresponding to FIG. 2 of the digital-analog converter can be represented as shown in FIG. In the figure, point N is the connection point between the first digital-analog conversion circuit 4 and the second digital-analog conversion circuit 5, V ₁ is the voltage when the first digital-analog conversion circuit 4 side is viewed from the point N, V ₂ represents the voltage when the second digital-analog conversion circuit 5 side is viewed from the N point.

At this time, V ₁ and V ₂ are expressed as follows.

[0090]

[Equation 21]

[0091]

[Equation 22]

Therefore, the output voltage V _OUT is

[0093]

[Equation 23]

It is represented by

For reference, a digital-analog converter for converting a 9-bit digital signal into an analog signal is shown in FIG. However, the bit number N _L of the lower bits is set to “6” and the bit number N _U of the upper bits is set to “3”. In this case, the number of changeover switches and resistors provided in the second digital-analog conversion circuit 5 is 7 from 2 ^Nu −1 = 2 ³ −1 = 7.

Then, the changeover switches S _{M0 to} S _{M6 of} the second switch group 9 are changed over according to the state of the upper 3 bits as shown in the table below.

[0097]

[Table 3]

In the table, B ₆ , B ₇ , and B ₈ represent the upper 3 bits. Further, in the GND, the changeover switches S _{M0 to} S _M6 are switched to the ground potential GND side, and V _REF is the reference voltage V
_It shows that it can be switched to the _REF side.

The output voltage V _OUT of this digital-analog converter is expressed as follows by substituting N _L = 6 and N _U = 3 into the equation 23.

[0100]

[Equation 24]

With this digital-to-analog converter, the same effect as that of the above embodiment can be obtained.

In the above embodiment, the reference voltage V _REF is applied to the first input terminal 1 and the ground potential GN is applied to the second input terminal 2.
Although each D is applied, the magnitude of the applied voltage is not particularly limited. In short, it is only necessary to apply the first reference potential and the second reference potential having different voltage values to the first input terminal 1 and the second input terminal 2, respectively.

B. Layout of Resistive Elements and Their Effects The digital-analog converter of FIG. 1 is formed by forming a plurality of resistive elements on a semiconductor wafer and electrically connecting the resistive elements appropriately. That is, each resistance element is formed as a band-shaped semiconductor layer of the second conductivity type by diffusing impurities or implanting appropriate ions into a predetermined region of a semiconductor wafer of the first conductivity type. A plurality of elements are arranged in parallel on a semiconductor wafer so as to have the same shape and the same size so that each element has a resistance value R. Then, a resistor having a resistance value of R is formed by one resistance element, and a resistor having a resistance value of 2R is formed by connecting two resistance elements in series.

By the way, when the resistance elements are formed as described above, it is necessary to set the resistance value of all the resistance elements to a constant value R. However, in the central portion and the peripheral portion of the semiconductor wafer, diffusion or ion implantation is not required. Since the conditions are slightly different, it is practically difficult to make the resistance values of all the resistance elements equal to the constant value R. In general, the resistance value of each resistance element often changes linearly along the arrangement direction. Further, if the heat generated by each element arranged around the resistance element is not uniform, the temperature distribution in the region where the resistance elements are arranged becomes non-uniform, and the variation in the resistance value of each resistance element varies. Occurs. Therefore, the resistors R _{1 to} R ₇ and R _M0 are simply included.
When the resistance elements forming the R _M2 are arranged in a line in such a manner that the resistance elements for the lower bits are adjacent to the resistance elements for the higher bits, the resistance elements are monotonic due to deterioration in accuracy of the resistance value. It may not be able to be maintained.

Therefore, in the present invention, the resistance element is arranged as described below to maintain the monotonicity of the digital-analog converter.

FIG. 11 is a plan view showing a first embodiment of the layout of the resistance elements which form the digital-analog converter of FIG. As shown in FIG.
_M0a , r _M1a ,. ． Are arranged in a line in the X direction at regular intervals, and the resistance elements forming the 2R circuit 8 are arranged symmetrically with respect to the reference line RL. That is, the resistance element r _M0a constituting the resistance R _M0, r _M0b is also resistive element r _M1a constituting the resistance R _M1, r _M1b is also resistive element r _M2a constituting the resistance R _M2, r _M2b Are arranged symmetrically with respect to the reference line RL. On the other hand, R-2R
In the circuit 6, the resistive elements r ₇ , r _13b , r _13a , r ₆ , r _12b , which form the resistors R ₇ , R ₁₃ , R ₆ , R ₁₂ ,.
r _12a. .. they are arranged in a row in this order. In this embodiment, the distance from the reference line RL to the resistance element is X.
The direction is positive and the (-X) direction is negative.

As described above, in this embodiment, 2R which seriously affects the monotonicity of the digital-analog converter.
Resistor elements r _M0a and r _M0b , r in which the circuit 8 is symmetrically arranged
Since it is composed of _M1a and r _M1b and r _M2a and r _M2b , the error of the resistance value due to the difference in the formation position of the resistance element in the 2R circuit 8 is offset, and the monotonicity of the digital-analog converter is maintained. be able to. The quantitative description will be given later.

FIG. 12 is a plan view showing a second embodiment of the layout of the resistance elements which form the digital-analog converter of FIG. As shown in the figure, in this second embodiment, not only the 2R circuit 8 but also a part of the R-2R circuit 6, the resistance elements are arranged symmetrically with respect to the reference line RL. That is, one set of resistance element pair r ₇ and r _13b is symmetrical with respect to the reference line RL. The other configurations are the same as those in the first embodiment.

By arranging the resistance elements symmetrically in a part of the R-2R circuit 6 as described above, the error of the resistance value of the R-2R circuit 6 is reduced and the characteristics of the digital-analog converter are improved. You can

Next, the effects of the first embodiment and the effects of the second embodiment will be described quantitatively while comparing with the first embodiment. Here, the resistance value of the resistance element changes linearly in the direction (X direction) perpendicular to the reference line RL by the proportional constant α, and the reference line R
The resistance value at L is the reference resistance value R. Therefore, the resistance value R _d of the resistance element separated from the reference line RL by the distance d in the X direction is R _d = R (1 + δ _i ) = R (1 + d · α) where δ _i is the error of the resistance element r _i . It is an ingredient.

As described above, the digital signal (0,1,1,1,1,1,1,1,1) is most likely to be impaired in monotonicity when the digital signal (1,0,0,0,0). , 0,0,0). Therefore, when the difference voltage ΔV _OUT is obtained in the same manner as above, the following equation is obtained.

[0112]

[Equation 25]

However, δ _oi is the error of the entire 2R circuit 8. In Expression 25, since the influence of the lower bit is small, the error of the resistance element of the lower bit is ignored.

Taking out the voltage change error V _error from the equation 25,

[0115]

[Equation 26]

However, LSB = V _REF / 2 ⁸ .

As can be seen from equation 26, δ _oi has the greatest effect on the voltage change error V _error , and in general δ _oi
Setting _oi to zero is preferred. 2 as above
When the R circuits 8 are symmetrically arranged, the value δ _oi becomes zero and the voltage change error V _error becomes relatively small. In addition,
The value of V _error at that time is obtained as follows.

As described above, in the first and second embodiments, since the 2R circuit 8 is composed of the resistance elements symmetrically arranged on the reference line RL, the value δ _oi is zero. Since the error component of the resistance element is proportional to the distance d from the reference line RL,

[0119]

[Equation 27] Becomes

As can be seen from FIG. 11, in the first embodiment, the distances d ₇ , d _13b , d _13a , d ₆ , d _12b ,
d _12a and d ₅ are 7, 9, 11, 13, 15, 1 respectively
Since these are 7, 19, these values are substituted into Equation 27,
When the voltage change error V _error is calculated, V _error = 590α · LSB is obtained.

On the other hand, in the second embodiment, as shown in FIG. 12, the distances d ₇ , d _13b , d _13a , d ₆ , d _12b , d _12a ,
d ₅ is -7, 7, 9, 11, 13, 15, 17 respectively.
Is. Therefore, by substituting these values into Equation 27,
When the voltage change error V _error is calculated, V _error = 82α · LSB is obtained.

Thus, not only the 2R circuit 8 but also the R-2
The resistance element pair R ₇ , R _13b of the R circuit 6 is connected to the reference line RL.
By arranging symmetrically with respect to
_error becomes smaller. For example, according to the second embodiment, the voltage change error is 0.14 times that of the first embodiment, and is less susceptible to the deterioration of the accuracy of the resistance element. The characteristics can be improved. As a result, a highly accurate digital-analog converter can be obtained.

FIG. 13 is a plan view showing a third embodiment of the layout of the resistance elements forming the digital-analog converter of FIG. In the third embodiment, as shown in the figure, among the resistance elements constituting the R-2R circuit 6, the number of symmetrically arranged resistance elements is increased. That is, R-
In the 2R circuit 6, the resistance element pair r ₇ and r _13a and the resistance element pair r _13b and r ₆ are symmetrical with respect to the reference line RL. The other configurations are the same as those in the first embodiment.

Next, the voltage change error in the third embodiment is obtained in the same manner as described above, and the effect of the third embodiment will be described. In this embodiment, as shown in the figure, the distance d _{7,
d 13 a, d 13b, d} 6, d 12b, d 12a, d 5 respectively -7,7, since it is -9,9,11,13,15,
Substituting these values into Equation 27, the voltage change error V _{erro r}
Then, V _error = −134α · LSB is obtained.

As described above, by arranging the resistance elements r ₇ and r _13a and the resistance elements r _13b and r ₆ symmetrically with respect to the reference line RL, the voltage change error V is different from that in the first embodiment.
_{The error} is reduced, and the same effect as the second embodiment can be obtained.

FIG. 14 is a plan view showing a fourth embodiment of the layout of the resistance elements which form the digital-analog converter of FIG. In the fourth embodiment, as shown in the figure, among the resistance elements forming the R-2R circuit 6, the number of resistance elements symmetrically arranged is further increased. That is, in the R-2R circuit 6, the resistance element pair r ₇ , r
_13a , the resistance element pair r _13b and r ₆ , and the resistance element pair r _12b r _12a are symmetrical with respect to the reference line RL. The other configurations are the same as those in the first embodiment.

Next, the voltage change error in the fourth embodiment is obtained in the same manner as described above, and the effect of the fourth embodiment will be described. In this embodiment, as shown in the figure, the distance d _7,
Since d _{13 a} , d _13b , d ₆ , d _12b , d _12a and d 5 are -7, 7, -9, 9, -11, 11 and 13, respectively, substituting these values into Equation 27, Voltage change error _{Ver
When ror} is calculated, V _error = -142α · LSB is obtained.

As described above, also in the fourth embodiment, the same effect can be obtained. It should be noted that, of the resistance elements forming the R-2R circuit 6, the combination and the number of combinations of the resistance elements symmetrically arranged are not limited to those in the above second to fourth embodiments, and are arbitrary.

[0129]

As described above, according to the first aspect of the present invention, the second digital-analog circuit driven based on the higher-order digital data is symmetrically arranged about the reference line. Since it is composed of a plurality of resistors formed by connecting two resistance elements in series,
It is possible to cancel the error of the resistance element in the digital / analog circuit, and it is possible to obtain high resolution while maintaining monotonicity without using a resistor having a high resistance ratio.

According to the invention of claim 2, in addition to the invention of claim 1, among the plurality of first resistance elements,
Since at least one resistance element pair is symmetrically arranged with respect to the reference line, even in the first digital / analog circuit, the error of the resistance element can be partially canceled and higher resolution can be obtained. ..

According to the third aspect of the present invention, of the resistors forming the 2R circuit, two resistors connected in series are connected to a reference line extending in a second direction perpendicular to the first direction. Are arranged symmetrically with respect to the center of symmetry, and the plurality of resistors are arranged in the third region of the semiconductor substrate located between the first and second regions. Therefore, the resistance in the second digital / analog circuit is reduced. It is possible to cancel the error of the element and obtain high resolution.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an 8-bit digital-analog converter according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram thereof.

FIG. 3 is a circuit diagram showing a state in which resistance is varied in a conventional circuit.

FIG. 4 is a circuit diagram showing a state in which resistance is varied in the circuit of FIG.

FIG. 5 is a circuit diagram for calculating the amount of change in output voltage.

FIG. 6 is a circuit diagram for calculating the amount of change in output voltage.

FIG. 7 is a circuit diagram for calculating the amount of change in output voltage.

FIG. 8 is a circuit diagram for calculating the amount of change in output voltage.

FIG. 9 is a diagram showing an equivalent circuit of a generalized digital-analog converter.

FIG. 10 is a circuit diagram showing a 9-bit digital-analog converter that is another embodiment of the present invention.

FIG. 11 is a plan view showing a first embodiment of the layout of the resistance elements forming the digital-analog converter of FIG.

FIG. 12 is a plan view showing a second embodiment of the layout of the resistance elements forming the digital-analog converter of FIG.

13 is a plan view showing a third embodiment of the layout of the resistance elements that form the digital-analog converter of FIG. 1. FIG.

FIG. 14 is a plan view showing a fourth embodiment of the layout of the resistance elements that make up the digital-analog converter of FIG.

FIG. 15 is a circuit diagram showing a conventional 8-bit digital-analog converter.

[Explanation of symbols]

4 first digital-to-analog converter 5 second digital-analog converter circuit _{R 1 ~R 7, R M0 ~R} M2 resistor _{(resistor) r 5 ~r 7, r M0a} , r M0b, r M1a, r M1b,
r _M2a , r _M2b Resistance element RL Reference line

Claims (3)

[Claims] 1. An R-2R circuit comprising a plurality of first resistance elements formed of a second conductivity type semiconductor layer formed in the first conductivity type semiconductor region in the first direction and having the same shape and the same size. Are electrically connected to form a first digital signal driven based on the lower bit digital data.
An analog circuit and a plurality of second resistance elements 2R composed of a second conductive type semiconductor layer formed in the semiconductor region in the first direction and having the same shape and size as the first resistance element 2R are provided. Electrically connected to form a circuit,
A second digital-analog circuit driven based on digital data of upper bits, wherein the second digital-analog converter converts a binary digital signal consisting of the upper bits and the lower bits into an analog signal, A plurality of two digital-analog converter circuits are formed by serially connecting two second resistance elements symmetrically arranged with a reference line extending in a second direction perpendicular to the first direction as a symmetry center. A digital-analog converter characterized by being constituted by a resistor. 2. The digital-analog converter according to claim 1, wherein at least one or more pairs of resistance elements among the plurality of first resistance elements are symmetrically arranged with respect to the reference line. 3. A plurality of resistors, each of which is composed of a semiconductor layer whose resistance value is set to R, are arranged in the first direction at predetermined intervals, and the plurality of resistors are electrically connected. And a resistor connected to at least the output terminal is arranged in the first region of the semiconductor substrate, and the remaining resistors are arranged in the second region of the semiconductor substrate. A plurality of first digital / analog circuits driven based on bit digital data, and a plurality of resistors each including a semiconductor layer whose resistance value is set to R are separated by a predetermined distance in a first direction, By electrically connecting these resistors,
Two resistors, which form an R circuit and are connected in series, are arranged symmetrically with a reference line extending in a second direction perpendicular to the first direction as a center of symmetry, and a plurality of resistors. Is arranged in a third region of the semiconductor substrate located between the first and second regions, and is provided with a second digital-analog circuit driven based on digital data of upper bits. .