JPH04352466A - R-2r ladder-type resistor circuit - Google Patents

R-2r ladder-type resistor circuit

Info

Publication number
JPH04352466A
JPH04352466A JP12711791A JP12711791A JPH04352466A JP H04352466 A JPH04352466 A JP H04352466A JP 12711791 A JP12711791 A JP 12711791A JP 12711791 A JP12711791 A JP 12711791A JP H04352466 A JPH04352466 A JP H04352466A
Authority
JP
Japan
Prior art keywords
resistor
resistance
semiconductor diffusion
ladder
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12711791A
Other languages
Japanese (ja)
Inventor
Masao Arimoto
正生 有本
Yusuke Yamada
山田 友右
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12711791A priority Critical patent/JPH04352466A/en
Publication of JPH04352466A publication Critical patent/JPH04352466A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an R-2R ladder-type resistor circuit of a high accuracy easily, as the one to be used in an n-bit digital analog converter, etc. CONSTITUTION:A semiconductor diffusion layer 5 formed on the central part of a resistor island 4 is the one having no range of the width of a resistor, among respective semiconductor diffusion layers 5 formed in parallel with each other on the resistor island 4. This semiconductor diffusion layer 5 is made to be an MSB resistor, to which the highest accuracy of a resistance ratio is required. Therefore, in an n-bit digital analog converter, the accuracy of the analog output when a data is changed over from 2<m-2> to 2<n-1> can be prevented from lowering. Thereby, an R-2R ladder-type resistor circuit 2 of a high accuracy can be obtained easily, without necessity of changing the width and the shape of the resistor in particular.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は第1導電型の半導体領
域上に形成された第2導電型の半導体拡散層からなる複
数個の抵抗により構成されるR−2Rラダー抵抗回路に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an R-2R ladder resistance circuit constituted by a plurality of resistors each consisting of a semiconductor diffusion layer of a second conductivity type formed on a semiconductor region of a first conductivity type.

【0002】0002

【従来の技術】図5は従来のnビットのデジタル・アナ
ログ変換器の結線図であり、図6はこのデジタル・アナ
ログ変換器に用いられるR−2Rラダー抵抗回路の平面
図である。
2. Description of the Related Art FIG. 5 is a wiring diagram of a conventional n-bit digital-to-analog converter, and FIG. 6 is a plan view of an R-2R ladder resistance circuit used in this digital-to-analog converter.

【0003】図5に示すように、基準電圧Vref が
印加される入力端子1及び接地(GND)にそれぞれ一
方,他方の切換端子が接続されたn個の切換スイッチS
1 ,S2 ,…,Sn が設けられると共に、抵抗値
がRの複数個の抵抗からなるR−2Rラダー抵抗回路2
が設けられてnビットのデジタル・アナログ変換器が構
成されており、このときR−2Rラダー抵抗回路2の構
成は以下のようである。
As shown in FIG. 5, there are n changeover switches S, one of which is connected to the input terminal 1 to which a reference voltage Vref is applied, and the other of which is connected to the ground (GND).
1, S2,..., Sn, and an R-2R ladder resistance circuit 2 consisting of a plurality of resistors each having a resistance value of R.
is provided to constitute an n-bit digital-to-analog converter, and the configuration of the R-2R ladder resistance circuit 2 is as follows.

【0004】即ち、図5に示すように、抵抗R01,R
02が直列に接続され、抵抗R02が入力端子1に接続
され、抵抗R01と出力端子3との間に(n−1)個の
抵抗R02,…,R2n−4,R2n−2が接続され、
抵抗R01と抵抗R02の接続点と切換スイッチS1の
共通端子との間に抵抗R11,R12が直列に接続され
て最下位ビット(以下LSBという)の抵抗値2Rの抵
抗ペアが構成され、以下同様にして各ビットの抵抗値2
Rの抵抗ペアが構成され、抵抗R2n−4とR2n−2
の接続点と切換スイッチS1 の共通端子との間に抵抗
R(2n−3)1 ,R(2n−3)2 が直列に接続
されて最上位の1つ下位のビットの抵抗値2Rの抵抗ペ
アが構成され、出力端子3と切換スイッチSnの共通端
子との間に抵抗R(2n−1)1 ,R(2n−1)2
 が直列に接続されて最上位ビット(以下MSBという
)の抵抗値2Rの抵抗ペアが構成され、これら各抵抗に
よりR−2Rラダー抵抗回路2が構成されている。
That is, as shown in FIG.
02 are connected in series, a resistor R02 is connected to the input terminal 1, and (n-1) resistors R02,..., R2n-4, R2n-2 are connected between the resistor R01 and the output terminal 3,
Resistors R11 and R12 are connected in series between the connection point of resistor R01 and resistor R02 and the common terminal of changeover switch S1, forming a resistor pair with a resistance value of 2R for the least significant bit (hereinafter referred to as LSB), and the same applies hereafter. and the resistance value of each bit is 2
A resistor pair of R is configured, resistors R2n-4 and R2n-2
Resistors R(2n-3)1 and R(2n-3)2 are connected in series between the connection point of and the common terminal of the changeover switch S1, and the resistance value of the most significant bit is 2R. A pair is formed, and resistors R(2n-1)1 and R(2n-1)2 are connected between the output terminal 3 and the common terminal of the changeover switch Sn.
are connected in series to form a resistor pair with a resistance value of 2R for the most significant bit (hereinafter referred to as MSB), and an R-2R ladder resistance circuit 2 is formed by each of these resistors.

【0005】そして、図5に示す構成のnビットのデジ
タル・アナログ変換器の各切換スイッチS1 〜Snは
、デジタルデータの各ビットの“1”,“0”のビット
内容にそれぞれ応じて入力端子1側又は接地側に切り換
わり、そのデジタルデータに応じた電圧値のアナログ信
号が出力端子3から出力される。
Each of the changeover switches S1 to Sn of the n-bit digital-to-analog converter having the configuration shown in FIG. 1 side or the ground side, and an analog signal having a voltage value corresponding to the digital data is output from the output terminal 3.

【0006】このとき、各切換スイッチS1 〜切換ス
イッチSnには、2m−1 (m=1,2…,n)の重
みがあり、切換スイッチS1 の重みは1、切換スイッ
チS2 の重みは2、切換スイッチSnの重みは2n−
1 となり、これらの切換スイッチS1 〜切換スイッ
チSnにそれぞれ接続された抵抗R11,R12等の各
抵抗ペアも各切換スイッチS1 〜Snそれぞれと同じ
重みを持つため、デジタル・アナログ変換器の精度はM
SB側の抵抗R(2n−1)1 ,R(2n−1)2 
,切換スイッチSnに依るところが大きい。
At this time, each of the changeover switches S1 to Sn has a weight of 2m-1 (m=1, 2..., n), the weight of the changeover switch S1 is 1, and the weight of the changeover switch S2 is 2. , the weight of the changeover switch Sn is 2n-
1, and each resistor pair such as resistors R11 and R12 connected to these changeover switches S1 to Sn has the same weight as each changeover switch S1 to Sn, so the accuracy of the digital-to-analog converter is M
SB side resistance R(2n-1)1, R(2n-1)2
, depends largely on the changeover switch Sn.

【0007】ところで、上記したR−2Rラダー抵抗回
路2は、図6に示すように構成され、第1導電型の半導
体領域(以下抵抗島という)4上に同一方向に同一形状
,同一の大きさで複数の第2導電型の半導体拡散層5が
形成されて各抵抗が構成され、これらの各抵抗が図5に
示すように接続されているが、この場合抵抗島4の各半
導体拡散層5は、左側から右側に向かって順次に上位ビ
ットとなるように各ビットの抵抗ペアとして用いられる
ため、LSBの抵抗R11,R12のペアは抵抗島4の
左端付近に、MSBの抵抗R(2n−1)1 ,R(2
n−1)2 のペアは抵抗島4の右端に位置する。
By the way, the above-mentioned R-2R ladder resistance circuit 2 is constructed as shown in FIG. Then, a plurality of semiconductor diffusion layers 5 of the second conductivity type are formed to constitute each resistor, and these resistors are connected as shown in FIG. 5. In this case, each semiconductor diffusion layer of the resistor island 4 5 is used as a resistor pair for each bit in order from the left side to the right side, so the pair of LSB resistors R11 and R12 is located near the left end of the resistor island 4, and the MSB resistor R (2n -1)1 ,R(2
The pair n-1)2 is located at the right end of the resistive island 4.

【0008】そして、デジタル・アナログ変換器では一
般にビット数が多くなと、低電流で高い抵抗比精度が要
求されるため、必然的に各抵抗,即ち各半導体拡散層5
の幅は細く長くなる傾向にあり、ビット数の増大に伴い
、それまでは無視できる程度であった各抵抗それぞれの
幅の較差や拡散較差が次第にデジタル・アナログ変換器
の精度に影響を及ぼすようになる。
[0008] In general, in a digital-to-analog converter, when the number of bits is large, low current and high resistance ratio accuracy are required, so each resistor, that is, each semiconductor diffusion layer 5
The width of the resistor tends to become narrower and longer, and as the number of bits increases, the width difference and diffusion difference of each resistor, which had been negligible until then, gradually begins to affect the accuracy of the digital-to-analog converter. become.

【0009】また、図6に示すように、各抵抗としての
半導体拡散層5は、抵抗島4上に近接して並んで形成さ
れるため、抵抗島4の中央部における半導体拡散層5と
端に位置する半導体拡散層5とを比べた場合、端や端に
近い半導体拡散層5の特に幅の条件が異なり、抵抗値の
較差が大きくなり、従って重みが最も大きく動作上抵抗
比精度が最も要求されるMSBの抵抗R(2n−1)1
 ,R(2n−1)2 のペアが抵抗島4の右端にある
と、上記した抵抗幅の較差の影響により、データが2n
−2 から2n−1 に切り換わる時の精度が極めて悪
くなる。
Furthermore, as shown in FIG. 6, the semiconductor diffusion layers 5 as each resistor are formed adjacently on the resistor island 4, so that the semiconductor diffusion layer 5 in the center of the resistor island 4 and the edge When comparing the semiconductor diffusion layer 5 located at the edge and the semiconductor diffusion layer 5 near the edge, the width conditions are different, and the difference in resistance value becomes large. Required MSB resistance R(2n-1)1
, R(2n-1)2 is located at the right end of resistive island 4, the data becomes 2n due to the influence of the resistance width difference mentioned above.
The accuracy when switching from -2 to 2n-1 becomes extremely poor.

【0010】一方、抵抗島4の左端近くに位置する抵抗
R11,R12のペアも抵抗幅の較差の影響はあるが、
これらの抵抗ペアは重みが1であるため、デジタル・ア
ナログ変換器の精度にはあまり影響がない。
On the other hand, the pair of resistors R11 and R12 located near the left end of the resistive island 4 is also affected by the difference in resistance width;
Since these resistor pairs have a weight of 1, they do not significantly affect the accuracy of the digital-to-analog converter.

【0011】[0011]

【発明が解決しようとする課題】従来のR−2Rラダー
抵抗回路2では、上記したように、動作上最も抵抗比精
度が必要なMSBの抵抗R(2n−1)1 ,R(2n
−1)2 のペアが抵抗島4の端に位置し、抵抗幅の較
差がデジタル・アナログ変換器の精度に大きく影響する
ため、抵抗幅を細くすることもできず、却って抵抗幅を
ある程度太くし、その幅に見合う長さにする方が良く、
ビット数の多いデジタル・アナログ変換器等に用いるR
−2Rラダー抵抗回路として、高精度のものを容易に得
ることが困難であるという問題点があった。
[Problems to be Solved by the Invention] As mentioned above, in the conventional R-2R ladder resistance circuit 2, the MSB resistors R(2n-1)1 and R(2n
-1) The pair of 2 is located at the end of the resistor island 4, and the difference in resistance width greatly affects the accuracy of the digital-to-analog converter, so it is impossible to make the resistance width narrower, and on the contrary, it is impossible to make the resistance width wider. It is better to make the length commensurate with the width,
R used for digital/analog converters with a large number of bits, etc.
There is a problem in that it is difficult to easily obtain a highly accurate -2R ladder resistance circuit.

【0012】この発明は、上記のような問題点を解消す
るためになされたもので、nビットのデジタル・アナロ
グ変換器等に用いるR−2Rラダー抵抗回路として、高
精度のものを容易に得られるようにすることを目的とす
る。
The present invention was made to solve the above-mentioned problems, and it is possible to easily obtain a high-precision R-2R ladder resistor circuit for use in an n-bit digital-to-analog converter, etc. The purpose is to make it possible to

【0013】[0013]

【課題を解決するための手段】この発明に係るR−2R
ラダー抵抗回路は、第1導電型の半導体領域上に、同一
方向に同一形状,同一の大きさで形成された第2導電型
の半導体拡散層からなる複数個の抵抗により構成される
R−2Rラダー抵抗回路において、前記各半導体拡散層
のうち中央部に位置する前記半導体拡散層を、動作上最
も抵抗比精度が必要な抵抗として用いることを特徴とし
ている。
[Means for solving the problem] R-2R according to the present invention
The ladder resistance circuit is composed of a plurality of resistors made of semiconductor diffusion layers of a second conductivity type formed in the same direction, in the same shape, and in the same size on a semiconductor region of the first conductivity type. In the ladder resistance circuit, the semiconductor diffusion layer located in the center of each of the semiconductor diffusion layers is used as a resistor that requires the highest resistance ratio accuracy for operation.

【0014】[0014]

【作用】この発明においては、半導体領域上に形成され
た各半導体拡散層のうち中央部の半導体拡散層を、動作
上最も抵抗比精度が必要な抵抗としたため、抵抗比精度
の必要な抵抗に抵抗幅の較差のない中央部の半導体拡散
層が用いられ、抵抗の幅や形状を特に変える必要もなく
、高精度のR−2Rラダー抵抗回路が容易に得られ、ビ
ット数の多いデジタル・アナログ変換器に適用した場合
にアナログ出力の精度低下が防止される。
[Operation] In this invention, among the semiconductor diffusion layers formed on the semiconductor region, the central semiconductor diffusion layer is made the resistor that requires the most resistance ratio accuracy for operation. A semiconductor diffusion layer in the center with no difference in resistance width is used, and there is no need to change the width or shape of the resistance, making it easy to obtain a high-precision R-2R ladder resistance circuit, which can be used for digital/analog circuits with a large number of bits. When applied to a converter, deterioration in accuracy of analog output is prevented.

【0015】[0015]

【実施例】図1はこの発明のR−2Rラダー抵抗回路の
一実施例の平面図、図2は結線図であり、nビットのデ
ジタル・アナログ変換器に適用した場合を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view of an embodiment of the R-2R ladder resistor circuit of the present invention, and FIG. 2 is a wiring diagram, showing the case where the circuit is applied to an n-bit digital-to-analog converter.

【0016】図1において、図6と相違するのは、抵抗
島4の中央を示す図1中の1点鎖線付近の半導体拡散層
5のMBS側の抵抗R(2n−1)1 ,R(2n−1
)2 ,R2n−2とし、抵抗島4の右端部の半導体拡
散層5をほぼ中間のビットの抵抗R2m−2,R(2m
−1)1 ,R(2m−1)2 (但し、1<m<n)
とし、図6におけるMBS側の抵抗R(2n−1)1 
,R(2n−1)2 ,R2n−2と中間のビットの抵
抗R2m−2,R(2m−1)1 ,R(2m−1)2
 を入れ換えたことである。
1 is different from FIG. 6 in that the resistances R(2n-1)1, R( 2n-1
)2, R2n-2, and the semiconductor diffusion layer 5 at the right end of the resistive island 4 is set to the almost middle bit resistance R2m-2, R(2m
-1)1 ,R(2m-1)2 (1<m<n)
and the resistance R(2n-1)1 on the MBS side in FIG.
, R(2n-1)2 , R2n-2 and the intermediate bit resistance R2m-2, R(2m-1)1 , R(2m-1)2
This means that the .

【0017】ところで、図2は図1のR−2Rラダー抵
抗回路2を用いたnビットのデジタル・アナログ変換器
の結線図であり、図5に示すものと同じ構成であり、図
5では図示省略されていた中間のビットの抵抗R(2m
−1)1 ,R(2m−1)2 ,R2m−2,R2m
−1及び抵抗R(2m−1)2 に接続された切換スイ
ッチSmを図示したものである。
By the way, FIG. 2 is a wiring diagram of an n-bit digital-to-analog converter using the R-2R ladder resistance circuit 2 of FIG. 1, and has the same configuration as that shown in FIG. Resistance R of the omitted middle bit (2m
-1)1 ,R(2m-1)2 ,R2m-2,R2m
-1 and the changeover switch Sm connected to the resistor R(2m-1)2.

【0018】このとき、上記したように、切換スイッチ
Smの重みが2m−1 であるため、抵抗R(2m−1
)1 ,R(2m−1)2 のペアも2m−1 の重み
を持つが、MSBの切換スイッチSn及び抵抗R(2n
−1)1 ,R(2n−1)2 の重み2n−1 (n
>m)に比べるとはるかに小さく、中間のビットの抵抗
R(2m−1)1 ,R(2m−1)2 のペアの重み
はMSBの抵抗R(2n−1)1 ,R(2m−1)2
 のペアの重みの1/2n−m となるため、中間のビ
ットの抵抗R(2m−1)1 ,R(2m−1)2 が
抵抗島4の右端にあっても、抵抗幅の較差によるデジタ
ル・アナログ変換器の精度への影響は無視できる程度で
ある。
At this time, as mentioned above, since the weight of the changeover switch Sm is 2m-1, the resistance R(2m-1
)1, R(2m-1)2 also has a weight of 2m-1, but the MSB changeover switch Sn and resistor R(2n
-1)1, R(2n-1)2 weight 2n-1 (n
> m), and the weight of the pair of middle bit resistances R(2m-1)1, R(2m-1)2 is much smaller than that of the MSB resistances R(2n-1)1, R(2m-1). 1)2
Since the weight of the pair is 1/2n-m, even if the intermediate bit resistances R(2m-1)1 and R(2m-1)2 are at the right end of the resistor island 4, the difference in resistance width The impact on the accuracy of the digital-to-analog converter is negligible.

【0019】また、LSBの抵抗R01,R02も抵抗
島4の左端に位置するため、上記したように抵抗幅の較
差は大きいが、重みは1であり、MSBの抵抗R(2n
−1)1 ,R(2n−2)2 の重みと比べると1/
2n−1 と極めて小さく、抵抗幅の較差によるデジタ
ル・アナログ変換器の精度への影響は中間ビットの抵抗
の場合よりもさらに少ない。
Furthermore, since the resistances R01 and R02 of the LSB are also located at the left end of the resistance island 4, the difference in resistance width is large as described above, but the weight is 1, and the resistance R (2n
-1)1 , 1/ compared to the weight of R(2n-2)2
2n-1, and the influence of the difference in resistance width on the accuracy of the digital-to-analog converter is even less than in the case of intermediate bit resistances.

【0020】従って、抵抗島4に並列に形成される各半
導体拡散層5のうち、抵抗幅の較差のない中央部の半導
体拡散層5を、抵抗比精度の最も要求されるMSBの抵
抗としたため、nビットのデジタル・アナログ変換器に
おいてデータが2n−2 から2n−1 に切り換わる
時のアナログ出力の精度の低下を防止でき、抵抗の幅や
形状を特に変える必要もなく、高精度のR−2Rラダー
抵抗回路2を容易に得るこができる。
Therefore, among the semiconductor diffusion layers 5 formed in parallel to the resistor island 4, the central semiconductor diffusion layer 5 with no difference in resistance width is made the MSB resistor where resistance ratio accuracy is most required. , it is possible to prevent a decrease in the accuracy of analog output when the data switches from 2n-2 to 2n-1 in an n-bit digital-to-analog converter, and there is no need to particularly change the width or shape of the resistor. -2R ladder resistance circuit 2 can be easily obtained.

【0021】つぎに、図3はこの発明の他の実施例の平
面図である。
Next, FIG. 3 is a plan view of another embodiment of the present invention.

【0022】図3において、図1と相違するのは、抵抗
島4の中央を示す図3中の1点鎖線下の半導体拡散層5
をMSBの一方の抵抗R(2n−1)1 とし、この抵
抗R(2n−1)である半導体拡散層5の左側の半導体
拡散層5を抵抗R(2n−1)2 とし、右側の半導体
拡散層5を抵抗R2n−2とし、以下同様にして下位の
ビットの抵抗として、順次に左側,右側の半導体拡散層
5を割り振っていき、最も左端の半導体拡散層5を抵抗
R02,最も右端の半導体拡散層5を抵抗R01とし、
抵抗島4の中央線に対して重みの重い順に抵抗を左,右
に振り分けて対称に配置し、抵抗に所定の接続を施した
ことであり、この場合も図1の場合と同等の効果を得る
ことができる。
3, the difference from FIG. 1 is that the semiconductor diffusion layer 5 below the dashed line in FIG.
is the resistance R(2n-1)1 of one side of the MSB, the semiconductor diffusion layer 5 on the left side of the semiconductor diffusion layer 5 having this resistance R(2n-1) is the resistance R(2n-1)2, and the semiconductor diffusion layer 5 on the right side is the resistance R(2n-1)2. The diffusion layer 5 is designated as a resistor R2n-2, and the semiconductor diffusion layers 5 on the left and right sides are assigned in the same manner as the resistance of the lower bits, and the leftmost semiconductor diffusion layer 5 is assigned as a resistor R02, and the rightmost semiconductor diffusion layer 5 is assigned as a resistor R02. The semiconductor diffusion layer 5 is a resistor R01,
The resistors are distributed symmetrically to the left and right in order of weight with respect to the center line of the resistor island 4, and the resistors are connected in the prescribed manner. In this case as well, the same effect as in the case of Fig. 1 can be obtained. Obtainable.

【0023】ところで、図4は図3のR−2Rラダー抵
抗回路2を用いたnビットのデジタル・アナログ変換器
の結線図であり、図5に示すものと同じ構成であり、図
5では図示省略されていた下位側から2ビット目の抵抗
R31,R32及び抵抗R32に接続された切換スイッ
チS2 を図示したものである。
By the way, FIG. 4 is a wiring diagram of an n-bit digital-to-analog converter using the R-2R ladder resistance circuit 2 of FIG. 3, and has the same configuration as that shown in FIG. This figure shows resistors R31 and R32 of the second bit from the lower order side, which have been omitted, and a changeover switch S2 connected to resistor R32.

【0024】なお、上記実施例では、R−2Rラダー抵
抗回路をnビットのデジタル・アナログ変換器に適用し
た場合について説明したが、特にデジタル・アナログ変
換器に限らず、抵抗比を使って電圧検出する場合などに
も適用できるのは勿論である。
In the above embodiment, the case where the R-2R ladder resistance circuit is applied to an n-bit digital-to-analog converter was explained, but it is not limited to digital-to-analog converters. Of course, this method can also be applied to detection.

【0025】[0025]

【発明の効果】以上のように、この発明のR−2Rラダ
ー抵抗回路によれば、半導体領域に形成された各半導体
拡散層のうち中央部の半導体拡散層を、動作上最も抵抗
比精度が必要な抵抗としたため、抵抗の幅や形状を特に
変える必要もなく、高精度のR−2Rラダー抵抗回路を
容易に得ることができ、ビット数の多いデジタル・アナ
ログ変換器等に適用した場合に高精度のデジタル・アナ
ログ変換器等を提供することが可能となる。
As described above, according to the R-2R ladder resistance circuit of the present invention, the central semiconductor diffusion layer among the semiconductor diffusion layers formed in the semiconductor region has the highest resistance ratio accuracy in operation. Since the required resistance is used, there is no need to particularly change the width or shape of the resistor, and a high-precision R-2R ladder resistance circuit can be easily obtained, making it suitable for applications such as digital-to-analog converters with a large number of bits. It becomes possible to provide highly accurate digital-to-analog converters and the like.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】この発明のR−2Rラダー抵抗回路の一実施例
の平面図である。
FIG. 1 is a plan view of an embodiment of the R-2R ladder resistance circuit of the present invention.

【図2】図1の結線図である。FIG. 2 is a wiring diagram of FIG. 1;

【図3】この発明の他の実施例の平面図である。FIG. 3 is a plan view of another embodiment of the invention.

【図4】図3の結線図である。FIG. 4 is a wiring diagram of FIG. 3;

【図5】一般のnビットデジタル・アナログ変換器の結
線図である。
FIG. 5 is a wiring diagram of a general n-bit digital-to-analog converter.

【図6】図5におけるR−2Rラダー抵抗回路の平面図
である。
6 is a plan view of the R-2R ladder resistance circuit in FIG. 5. FIG.

【符号の説明】[Explanation of symbols]

2  R−2Rラダー抵抗回路 4  半導体領域(抵抗島) 5  半導体拡散層 2 R-2R ladder resistance circuit 4 Semiconductor region (resistance island) 5 Semiconductor diffusion layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  第1導電型の半導体領域上に、同一方
向に同一形状,同一の大きさで形成された第2導電型の
半導体拡散層からなる複数個の抵抗により構成されるR
−2Rラダー抵抗回路において、前記各半導体拡散層の
うち中央部に位置する前記半導体拡散層を、動作上最も
抵抗比精度が必要な抵抗として用いることを特徴とする
R−2Rラダー抵抗回路。
Claim 1: R constituted by a plurality of resistors made of semiconductor diffusion layers of a second conductivity type formed in the same direction, in the same shape, and in the same size on a semiconductor region of the first conductivity type.
-2R ladder resistance circuit, wherein the semiconductor diffusion layer located in the center of each of the semiconductor diffusion layers is used as a resistor that requires the highest resistance ratio accuracy for operation.
JP12711791A 1991-05-30 1991-05-30 R-2r ladder-type resistor circuit Pending JPH04352466A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12711791A JPH04352466A (en) 1991-05-30 1991-05-30 R-2r ladder-type resistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12711791A JPH04352466A (en) 1991-05-30 1991-05-30 R-2r ladder-type resistor circuit

Publications (1)

Publication Number Publication Date
JPH04352466A true JPH04352466A (en) 1992-12-07

Family

ID=14952031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12711791A Pending JPH04352466A (en) 1991-05-30 1991-05-30 R-2r ladder-type resistor circuit

Country Status (1)

Country Link
JP (1) JPH04352466A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223775A (en) * 1996-02-19 1997-08-26 Nec Corp Resistor element and its composite resistor and resistor circuit
JP2009206122A (en) * 2008-02-26 2009-09-10 Ricoh Co Ltd Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994918A (en) * 1982-11-20 1984-05-31 Mitsubishi Electric Corp Ladder resistance type d-a converting circuit by monolithic integrated circuit
JPS6079766A (en) * 1983-10-05 1985-05-07 Nec Corp R-2r ladder type resistor circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994918A (en) * 1982-11-20 1984-05-31 Mitsubishi Electric Corp Ladder resistance type d-a converting circuit by monolithic integrated circuit
JPS6079766A (en) * 1983-10-05 1985-05-07 Nec Corp R-2r ladder type resistor circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223775A (en) * 1996-02-19 1997-08-26 Nec Corp Resistor element and its composite resistor and resistor circuit
JP2009206122A (en) * 2008-02-26 2009-09-10 Ricoh Co Ltd Semiconductor device

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