JP3245273B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for forming a plurality of capacitors on a chip.

In recent years, semiconductor devices have been increasingly integrated,
A number of active and passive devices are arranged on a chip.
Further, in such a semiconductor device, higher precision of its operation is increasingly required. Therefore, it is necessary to improve the precision of a large number of passive elements formed on a chip.

[0003]

2. Description of the Related Art An example of a 4-bit charge redistribution A / D converter will be described with reference to FIG. Capacity 8C, 4C, 2C,
1C has its capacitance value set by a value obtained by weighting 2;
The ratio of the capacitance values is set to 8: 4: 2: 1.

That is, the capacitor 8C is composed of eight unit capacitances, the capacitance 4C is composed of four unit capacitances,
C is composed of two unit capacitances, and capacitance 1C is composed of one unit capacitance.

One terminal of each of the capacitors 8C, 4C, 2C, 1C is connected to the chopper type comparator 1. The chopper type comparator 1 includes an inverter circuit 2 and an N-channel MOS transistor Trc connected in parallel to the inverter circuit 2. The on / off operation of the transistor Trc is controlled based on the operation of the successive approximation control unit (not shown).

The other terminals of the capacitors 8C to 1C are connected to switching circuits 3a to 3c controlled by the successive approximation control unit.
3d, and are switched so that any one of the reference power supply voltage AVR, the analog input signal Ain which fluctuates between the reference power supply voltage AVR and the level of the ground G, and the ground G is input. .

The operation of the A / D converter configured as described above will be described. First, based on the control of the successive approximation control unit, the switching circuits 3a to 3d switch the analog input signal Ain
And the sampling operation is performed.
1C stores an electric charge corresponding to the capacitance value.

At this time, the transistor Trc is turned on, and the terminals of the capacitors 8C to 1C on the chopper type comparator 1 side are maintained at the threshold value Vth of the chopper type comparator 1. Each of the capacitors 8C to 1C has the threshold value Vth,
Charged based on the difference voltage from the analog input signal Ain,
Negative charges are accumulated in the electrodes of the capacitors 8C to 1C on the chopper type comparator 1 side.

Next, while the transistor Trc is turned off, the switching circuits 3a to 3d are sequentially switched under the control of the successive approximation control section, and the change in the level of the input terminal of the inverter circuit 2 at that time causes the inverter circuit to change. The output signal OUT output from 2 becomes a 4-bit digital signal.

In the A / D converter as described above, each of the capacitors C8 to C1 is required to perform 4-bit A / D conversion, and each of the capacitors 8C to 1C is laid out as shown in FIG.

That is, 16 unit capacitors are arranged on the chip 4 in a grid pattern, and occupy half the area thereof.
A capacity 8C is constituted by the unit capacity. In addition, capacity 8C
A capacitor 4C is constituted by four unit capacitors arranged in the vertical direction adjacent to.

Also, a capacitor 2C composed of two unit capacitors and a capacitor 1C composed of one unit capacitor are arranged adjacent to the capacitor 4C. It should be noted that one capacitor adjacent to the capacitor 1C
The unit capacitance is a dummy capacitance D.

Each of the capacitors has a well formed on a substrate and a poly S formed on the well via an oxide film.
and i layer.

[0014]

As one means for improving the conversion accuracy of the A / D converter as described above, the capacitance values of each of the capacitors 8C to 1C formed on the chip 4 should be exactly 8: 4: 2: 1.

The respective capacitances 8C to 1C formed on the chip 4 can be easily set to the above-mentioned capacitance ratio if each unit capacitance has the same value. However, due to variations in the wafer process, the capacitance value of each unit capacitance is
May increase or decrease from one side to the other. For example, when a variation occurs on the chip 4 such that the capacitance value of each unit capacitance increases from right to left, the capacitance value of the capacitance 8C becomes smaller than the set value, and the capacitance value of the capacitances 1C and 2C. Becomes larger than the set value.

Then, it is difficult to accurately set the capacitance values of the capacitors 8C to 1C to the capacitance ratio. As a result,
There is a problem that the conversion accuracy of the A / D converter is reduced.

An object of the present invention is to provide a semiconductor device which forms a capacitance based on a large number of unit capacitances formed on a chip and which can suppress a change in the capacitance value of the capacitance due to a variation in a wafer process. Is to do.

[0018]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, a plurality of unit capacitance elements Cu are formed in the capacitance formation region A, and a plurality of the unit capacitances Cu are connected to form a capacitance element C having a predetermined capacitance value. With wiring
The connected unit capacitance elements Cu are evenly distributed with respect to the center CE of the capacitance formation region A.

Further, as shown in FIG.
Are formed in a point-symmetric unit capacitor element 8C1 to 8C8 with respect to the center CE of the capacitor forming area A1.
It is formed by connecting the children Cu by wiring . Further, a plurality of the unit capacitance elements are connected in parallel by wiring to form a capacitance element having a predetermined capacitance value. The unit capacitance elements are arranged in a grid pattern.

[0020]

A plurality of unit capacitance elements Cu constituting the capacitance element C are provided.
Are arranged so as to be evenly distributed with respect to the center CE of the capacitance forming region A, so that variations in the capacitance values of the unit capacitance elements Cu due to variations in the wafer process are canceled out.

[0021]

FIG. 2 shows a first embodiment of the present invention. Sixteen unit capacitors are formed in a grid pattern in the capacitor forming area A1 located at the center of the chip 4, and the unit capacitors constitute capacitors 8C, 4C, 2C, and 1C. Said 1
The six unit capacitors are arranged in a substantially uniform range around the center CE of the chip 4.

The capacitor 8C has eight unit capacitors 8C1 to 8C.
C8, and the capacitor 4C has four unit capacitors 4C1.
4C4, and the capacitor C2 is composed of two unit capacitors 2
C1 and 2C2, and the capacitance C1 is composed of one unit capacitance.

The unit capacitors 8C1 to 8C8 are arranged such that, for example, two units of the unit capacitors 8C1 and 8C8 are located point-symmetrically with respect to the center CE.
The unit capacitors 8C1 to 8C8 are connected in parallel by wiring (not shown) to form the capacitor 8C.

The unit capacitors 4C1 to 4C4 are arranged such that, for example, two units of the unit capacitors 4C1 and 4C4 are located point-symmetrically with respect to the center CE.
The unit capacitors 4C1 to 4C4 are connected in parallel by wiring (not shown) to form the capacitor 4C.

The unit capacitances 2C1 and 2C2 are equal to the center C
The unit capacitors 2C1 and 2C2 are arranged in a point symmetrical manner with respect to E, and the unit capacitors 2C1 and 2C2 are connected in parallel by wiring (not shown) to form the capacitor 2C.

The capacitor 1C is arranged adjacent to the center CE, and a dummy capacitor D is arranged at a point symmetrical position with respect to the center CE of the capacitor 1C. Therefore, each capacity 8C
1C are arranged so that the unit capacitors constituting them are dispersed point-symmetrically with respect to the center CE.

With such a configuration, even if a variation occurs in which the capacitance value of the unit capacitance changes from one side of the chip 4 to the other side due to the variation of the wafer process, each unit capacitance in each of the capacitors 8C to 2C is not changed. Since the capacitors 4 are arranged so as to be evenly distributed with respect to the center CE of the chip 4, the change in the capacitance value of each unit capacitor is, for example, such that the unit capacitors 8C1 and 8C8 complement the change in the capacitance value. Offset.

Further, since the capacitance 1C is disposed adjacent to the center CE, a change in the capacitance value due to a variation in the wafer process is small. Therefore, even if there is a variation in the wafer process, it is easy to accurately set the capacitance values of the capacitors 8C to 1C. If each of the capacitors 8C to 1C is used for the A / D converter, A
/ D conversion accuracy can be improved.

Next, a second embodiment of the present invention will be described with reference to FIG. Capacitance forming regions A2 and A3 are arranged on both sides of the center CE of the chip 4, and in each of the capacitance forming regions A2 and A3, eight unit capacitors are arranged in two columns in the vertical direction. 4C, 2C, 1
C is configured.

The capacitor 8C has eight unit capacitors 8C1 to 8C8.
C8, and the capacitor 4C is composed of unit capacitors 4C1 to 4C.
4 and the capacity C2 is unit capacity 2C1, 2C2.
, And the capacitance C1 is composed of one unit capacitance.

The unit capacitors 8C1 to 8C8 are arranged so as to be point-symmetrically distributed from the center CE in the capacitor forming regions A2 and A3, for example, the same as the unit capacitors 8C1 and 8C8. 8C8 are connected in parallel by wiring (not shown) to form the capacitor 8C.

The unit capacitors 4C1 to 4C4 are arranged so as to be point-symmetrically distributed from the center CE in the capacitor forming regions A2 and A3, for example, as the same as the unit capacitors 4C1 and 4C4. 4C4 are connected in parallel by wiring (not shown) to form the capacitor 4C.

The unit capacitances 2C1 and 2C2 are arranged in the capacitance forming areas A2 and A3 so as to be symmetrically dispersed from the center CE in a point-symmetric manner.
Are connected in parallel by wiring (not shown),
C is configured.

The capacitor 1C is connected to the capacitor forming region A
2, a dummy capacitor D is arranged near the center CE, and a dummy capacitor D is arranged at a point symmetrical position with respect to the center CE of the capacitor 1C in the capacitor forming region A3.

Therefore, each of the capacitors 8C to 1C is arranged such that each of the unit capacitors constituting the capacitors 8C to 1C is dispersed point-symmetrically with respect to the center CE. With such a configuration, even if a variation occurs in which the capacitance value of the unit capacitance changes from one side of the chip 4 to the other side due to the variation of the wafer process, each unit capacitance in each of the capacitors 8C to 2C is:
Since they are arranged so as to be point-symmetrically distributed with respect to the center CE of the chip 4, for example, the unit capacitance 8C1 and the same 8C8
Compensate for the variation in capacitance value, the variation in capacitance value of each unit capacitance is offset.

Further, since the capacitance 1C is arranged near the center CE, a change in the capacitance value due to a variation in the wafer process is small. Therefore, even if there is a variation in the wafer process, it is easy to accurately set the capacitance values of the capacitors 8C to 1C.

Next, a third embodiment of the present invention will be described with reference to FIG. 64 unit capacitors are formed in a grid pattern in a capacitor forming region A4 formed at the center of the chip 4, and the capacitors 32C, 16C, and 8 are formed from each unit capacitor.
C, 4C, 2C, and 1C are configured. The 64 unit capacitors are arranged in a substantially uniform range around the center CE of the chip 4.

The capacitor 32C has 32 unit capacitors 32C.
The capacitance 16C is composed of 16 unit capacitances 16C1 to 16C16, the capacitance 8C is composed of eight unit capacitances 8C1 to 8C8, and the capacitance 4C is composed of four unit capacitances 4C1 to 4C4. And the capacitance C
Reference numeral 2 denotes two unit capacitors 2C1 and 2C2, and the capacitor C1 includes one unit capacitor.

The unit capacitors 32C1 to 32C32 are arranged so as to be symmetrically dispersed with respect to the center CE, for example, the same as the unit capacitor 32C1 and 32C32, and the unit capacitors 32C1 to 32C32 are wired (not shown). ) Are connected in parallel to form the capacitor 32C.

The unit capacitors 16C1 to 16C16 are arranged so as to be symmetrically dispersed with respect to the center CE, for example, the same as the unit capacitors 16C1 and 16C16, and the unit capacitors 16C1 to 16C16 are wired (not shown). ) Are connected in parallel to form the capacitor 16C.

The unit capacitors 8C1 to 8C8 are arranged so as to be symmetrically dispersed with respect to the center CE, for example, the same as the unit capacitors 8C1 and 8C8.
C1 to 8C8 are connected in parallel by wiring (not shown) to form the capacitor 8C.

The unit capacitors 4C1 to 4C4 are similarly arranged so as to be distributed point-symmetrically from the center CE, and the unit capacitors 4C1 to 4C4 are connected in parallel by wiring (not shown). Is configured.

The unit capacitances 2C1 and 2C2 are equal to the center C
The capacitors 2C1 and 2C2 are arranged in a point-symmetric manner with respect to E, and the unit capacitors 2C1 and 2C2 are connected in parallel by wiring (not shown) to form the capacitor 2C.

The capacitor 1C is arranged adjacent to the center CE, and the dummy capacitor D is arranged at a point symmetrical position with respect to the center CE of the capacitor 1C. Therefore, each capacity 32
C to 1C are arranged such that the unit capacitors constituting them are distributed almost evenly with respect to the center CE.

With such a configuration, even if a variation occurs in which the capacitance value of the unit capacitance changes from one side of the chip 4 to the other side due to the variation of the wafer process, each unit capacitance in each of the capacitors 32C to 2C is not changed. Chip 4
Are arranged so as to be evenly distributed with respect to the center CE, so that the fluctuation of the capacitance value of each unit capacitance is cancelled.

Further, since the capacitance 1C is arranged adjacent to the center CE, the fluctuation of the capacitance value due to the fluctuation of the wafer process is very small. Therefore, even if a variation occurs in the wafer process, it is easy to accurately set the capacitance values of the capacitors 32C to 1C. If these capacitors 32C to 1C are used for an A / D converter having a 6-bit configuration, the A / D conversion accuracy can be improved.

In the above embodiment, the center CE of the chip 4 is
On the other hand, the unit capacitors are arranged so as to be dispersed in a point-symmetric manner, but the center CE is not necessarily required to be the center of the chip 4, but may be the center of the capacitor forming region.

[0048]

As described above in detail, the present invention relates to a semiconductor device in which a plurality of capacitance elements are formed on the basis of a large number of unit capacitance elements formed on a chip. An excellent effect of being able to provide a semiconductor device capable of suppressing a change in capacitance is exhibited.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a layout diagram of a unit capacitor showing the first embodiment.

FIG. 3 is a layout diagram of a unit capacitor showing a second embodiment.

FIG. 4 is a layout diagram of a unit capacitor showing a third embodiment.

FIG. 5 is a circuit diagram illustrating an example of a charge redistribution A / D converter.

FIG. 6 is a layout diagram of a conventional unit capacitor.

[Explanation of symbols]

 A capacitance forming region C capacitance element Cu unit capacitance element CE center

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (4)

(57) [Claims] 1. A plurality of unit capacitance elements (Cu) are formed in a capacitance formation region (A), and a plurality of the unit capacitance elements (Cu) are connected to form a capacitance element (C) having a predetermined capacitance value. In the semiconductor device to be formed, the unit capacitance elements (Cu) connected by wiring are uniformly distributed with respect to the center (CE) of the capacitance formation region (A).
A semiconductor device characterized by being arranged . 2. A plurality of unit capacitance elements (Cu) are formed in a capacitance formation area (A), and a plurality of the unit capacitance elements (Cu) are connected to form a capacitance element (C) having a predetermined capacitance value. A semiconductor device to be formed, wherein the capacitance element (C) is connected between unit capacitance elements (Cu) point-symmetric with respect to a center (CE) of the capacitance formation region (A).
A semiconductor device characterized by being formed by connecting with each other . 3. A plurality of said unit capacitance elements are connected in parallel by wiring.
Connecting to form a capacitive element having a predetermined capacitance value
The semiconductor device according to claim 1, wherein: 4. The unit capacitance element is arranged in a grid pattern.
The method according to claim 1, 2, or 3, wherein
Semiconductor device.