JPH05259390A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor which has a small parasitic capacitance between a semiconductor and well in a switched circuit and which is immune to the noise effects generated by outside noise or a group of switches in terms of a semiconductor device having groups of capacitors and transistors, such as switched capacitor circuits. CONSTITUTION:There are formed a first well 28 having the depth of the entire film thickness of a semiconductor layer 26 and second wells 30 and 32 having the depth of the semiconductor 26 on its way on the semiconductor layer 26 formed on an insulator layer 24. A group of capacitors 12 are formed on the first well 28 while a group of switches 10 and a group of operational amplifiers 13 are formed on the second wells 30 and 32 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor group and a transistor group such as a switched capacitor circuit.

[0002]

2. Description of the Related Art A specific example of a switched capacitor circuit will be described with reference to FIG. As shown in FIG. 1A, when a filter element including a capacitor 1, a resistor 2 and an operational amplifier 4 is formed on a semiconductor substrate, the resistance value of the resistor 2 varies about ± 30%. It is known that it is difficult to manufacture a filter element having stable characteristics.

Therefore, in order to realize a resistor having a small variation in resistance value, the resistor 2 in FIG. 1A is replaced by a switch composed of a capacitor 8 and a clock drive switch 6 as shown in FIG. 1B. It is known to replace with a de-capacitor circuit. An alternating pseudo resistance can be realized by turning on and off the clock drive switch 6 and repeating charging and discharging of the capacitor 8. Compared with the resistor 2, the variation in the capacitance value of the capacitor 8 formed on the semiconductor substrate can be suppressed to a very small value of about 1 to 2%, so that a highly accurate resistor is realized by the switched capacitor circuit. It is possible to manufacture a filter element having stable characteristics.

A conventional layout pattern of the filter element using the switched capacitor circuit is shown in FIG.
Will be explained. 2A is a plan view of a conventional filter element, and FIG. 2B is a sectional view taken along the line AA '.
As shown in FIG. 1B, the switched capacitor filter is composed of a switch 6, capacitors 1 and 8 and an operational amplifier 4, and a filter element composed of a plurality of switched capacitor filters has a plurality of elements. Switch 6
A switch group 10 having a plurality of capacitors, a capacitor group 12 having a plurality of capacitors 1 and 8, and an operational amplifier group 14 having a plurality of operational amplifiers.

In the conventional filter element, as shown in FIG. 2A, a switch group 10, a capacitor group 12, and an operational amplifier group 14 are sequentially arranged from the upper side, and FIG.
As shown in FIG. 5, the n-channel transistors of the switch group 10 are formed on the p-type well 11 formed on the surface of the n-type silicon substrate 9, and the capacitor group 12 is the p-type well 13.
The n-channel transistor of the operational amplifier group 14 formed above is formed on the p-type well 15. Each capacitor in the capacitor group 12 is, as schematically shown,
It is configured by forming a polysilicon layer 23B on the polysilicon layer 23A with an insulating layer 23C interposed therebetween.
Placing the p-type well 13 under the capacitor group 12 prevents switching noise from the switch group 10 or an external circuit from flowing into the capacitor group 12 or the operational amplifier group 14.

[0006]

As described above, by laying the p-type well 13 under the capacitor group 12 as described above, the sneak of switching noise is reduced, but as shown in FIG. 2 (b). , A large amount of parasitic capacitance is generated in the p-type well 13. For this reason, switching noise from the n-type silicon substrate 9 side via these parasitic capacitances,
There was a problem that it was transmitted to the capacitor group 12.

Further, the capacitor group 12 is the switch group 10
In the case where it is sandwiched between the operational amplifier group 14 and the operational amplifier group 14, the switching noise from the switch group 10 directly circulates through the underside of the p-type well 13 laid under the capacitor group 12. there were. An object of the present invention is to provide a semiconductor device in which a parasitic capacitance between a semiconductor substrate and a well is small in a switched capacitor circuit and which is not easily affected by external noise or noise generated in a switch group.

[0008]

The above object is to provide an insulating layer, a semiconductor layer formed on the insulating layer, a first well having a total thickness of the semiconductor layer, and the semiconductor layer. A second well having a halfway depth, a capacitor group formed on the first well and having a plurality of capacitors, and a transistor group formed on the second well and having a plurality of transistors. This is achieved by a semiconductor device characterized by the above.

[0009]

According to the present invention, the capacitor group is formed on the first well having the depth of the entire thickness of the semiconductor layer, and has the same polarity as the substrate on the second well having the depth up to the middle of the semiconductor layer. Since the transistor group of is formed, the area of the interface between the semiconductor layer and the well which causes the parasitic capacitance is reduced, and the parasitic capacitance can be reduced, and the power supply noise generated on the semiconductor layer side causes the noise between the substrate and the well. It is possible to reduce the transmission to the capacitor group via the parasitic capacitance. Further, by laying the well forming the capacitor group to the depth of the entire film thickness of the semiconductor layer, it is possible to prevent noise from the switch group and the outside from propagating in the semiconductor layer.

[0010]

EXAMPLE A semiconductor device according to an example of the present invention will be described with reference to FIG. FIG. 3A is a plan view of the filter element of this embodiment, and FIG. 3B is a sectional view taken along the line BB ′. The semiconductor device of this embodiment is also a filter element using the switched capacitor circuit shown in FIG. 1, as in FIG. The same components as those of the related art will be designated by the same reference numerals to omit or simplify the description.

The filter element of this embodiment has a switch group 10 as a first transistor group having a plurality of transistors and a capacitor group 12 having a plurality of capacitors.
And an operational amplifier group 14 as a second transistor group having a plurality of transistors. As shown in FIG. 3A, the switch group 10, the capacitor group 12, and the operational amplifier group 14 are arranged on both sides of the centrally arranged capacitor group 12 as shown in FIG. 3A. Has been done.

As shown in FIG. 3B, the filter element of this embodiment has a silicon oxide film 24 on a silicon substrate 22.
The n-type silicon layer 26 is formed as an element substrate on the support substrate on which is formed an SOI structure, and a filter element is formed on the surface of the n-type silicon layer 26. At the center of the n-type silicon layer 26, a p-type well 28 having a depth of the entire film thickness of the n-type silicon layer 26 and reaching the silicon oxide film 24 is formed, and on both sides of the p-type well 28,
P-type wells 30 and 32 having a depth up to the middle of the film thickness of the n-type silicon layer 26 are formed. The n-channel transistors of the capacitor group 12 are formed on the central p-type well 28, and the n-channel transistors of the switch group 10 and the operational amplifier group 14 are formed on the p-type wells 30 and 32 on both sides.

Since the p-type well 28 laid under the capacitor group 12 reaches the silicon oxide film 24, the interface between the p-type well 28 and the n-type silicon layer 26 is the p-type well 2.
There is no bottom part of 8 and only the side part. Since the bottom portion of the p-type well 28 is eliminated and the depth of the p-type well 28, that is, the thickness of the n-type silicon layer 26 is thin, the area of the interface between the p-type well 28 and the n-type silicon layer 26 is smaller than that of the conventional one. It has become very small. Therefore, in the filter element of the present embodiment, as shown in FIG.
The parasitic capacitance of the mold well 28 can be reduced, and switching noise and the like via the parasitic capacitance can be dramatically reduced.

Further, the switch group 10 and the operational amplifier group 14
Since the p-type well 28 is formed in the entire film thickness of the n-type silicon layer 26 so as to block the gap between them, the switching noise generated in the switch group 10 is blocked by the p-type well 28 and is directly transmitted to the operational amplifier group 14. Never. As described above, according to this embodiment, the area of the interface between the silicon layer and the well which causes the parasitic capacitance is reduced, the parasitic capacitance can be drastically reduced, and the power source noise generated on the silicon layer side is It is possible to reduce the transmission to the capacitor group via the parasitic capacitance. Further, by laying the well forming the capacitor group up to the depth of the entire film thickness of the silicon layer, it is possible to prevent noise from the switch group and noise from the outside from propagating in the silicon layer.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, the switch group and the operational amplifier group are arranged on both sides of the capacitor group in the above embodiment, but if a well having the depth of the entire thickness of the semiconductor layer is laid under the capacitor group, these switch group and capacitor group may be arranged. And the operational amplifier group may be arranged in any way. For example, the switch group, the operational amplifier group, and the capacitor group may be arranged in this order from above, or the switch group may be arranged above the capacitor group and the operational amplifier group may be arranged laterally.

[0016]

As described above, the capacitor group is formed on the first well having the depth of the entire thickness of the semiconductor layer, and the same polarity as the substrate is formed on the second well having the depth up to the middle of the semiconductor layer. Since the transistor group of is formed, the area of the interface between the semiconductor layer and the well which causes the parasitic capacitance is reduced, and the parasitic capacitance can be reduced, and the power supply noise generated on the semiconductor layer side causes the noise between the substrate and the well. It is possible to reduce the transmission to the capacitor group via the parasitic capacitance. Further, by laying the well forming the capacitor group to the depth of the entire film thickness of the semiconductor layer, it is possible to prevent noise from the switch group and the outside from propagating in the semiconductor layer.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a switched capacitor filter.

FIG. 2 is a diagram showing a layout of a conventional switched capacitor filter.

FIG. 3 is a diagram showing a layout of a switched capacitor filter according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Capacitor 2 ... Resistor 4 ... Operational amplifier 6 ... Switch 8 ... Capacitor 9 ... N-type silicon substrate 10 ... Switch group 11 ... P-type well 12 ... Capacitor group 13 ... P-type well 14 ... Operational-amp group 15 ... P-type well 22 ... Silicon substrate 23A ... Polysilicon layer 23B ... Polysilicon layer 23C ... Insulating layer 24 ... Silicon oxide film 26 ... N-type silicon layer 28 ... P-type well 30 ... P-type well 30 ... P-type well

Claims (2)

[Claims] 1. An insulating layer, a semiconductor layer formed on the insulating layer, a first well having a depth of the entire thickness of the semiconductor layer, and a first well having a depth halfway through the semiconductor layer. A semiconductor device comprising: two wells; a capacitor group formed on the first well and having a plurality of capacitors; and a transistor group formed on the second well and having a plurality of transistors. 2. The semiconductor device according to claim 1, wherein each of the transistor groups is formed on the second well, and has a first transistor group having a plurality of transistors and a second transistor group having a plurality of transistors. And a well in which the first transistor group is formed and a well in which the second transistor group is formed are arranged with the first well interposed therebetween. Semiconductor device.