JPH0677829A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce the number of chopper comparators used for the A/D converter acting like a 2-step flash type A/D converter. CONSTITUTION:A switch SWH receiving a comparison reference voltage VH in one-step for A/D conversion and switches SWL1-SWLn receiving comparison reference voltages VL1-VLn in 2-steps of A/D conversion are connected to an input of a chopper type comparator CP. Thus, the chopper type comparator CP is used for the comparison in one step of A/D conversion and for the comparison in two steps of A/D conversion and then the number of the comparators is reduced. Furthermore, the increase in the load by lot of switches with respect to the input is decreased at the input of an analog signal voltage VIN through the provision of the switch SWR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of comparison reference voltages having different voltages among a plurality of comparison reference voltages obtained by dividing a reference voltage by using a ladder resistor in which a plurality of resistance elements are connected in series. The chopper-type comparator used, which relates to an A / D (analog to digital) converter that simultaneously compares the generated analog signal voltage with a comparator group composed of a plurality of chopper-type comparators, and particularly operates as a two-step flash type. The present invention relates to an A / D converter that can reduce the number of

[0002]

2. Description of the Related Art A / D converters have long been used in industrial fields such as measuring devices such as digital voltmeters and programmable power supplies. In recent years, A / D
Converters are also used in consumer products such as compact disc players and in special fields such as codecs for connecting telephones to digital lines.

A home VTR (video tape recorder)
) For special playback and noise reduction on the device,
A capable of high-speed operation of 10 to 20 MHz with 6 to 8 bits
A / D converter is used. Relatively large capacity DR
With the recent development of digital technology such as the use of AM (dynamic random access memory) at relatively low cost, A / D converters are widely used in image processing devices and digital signal processors.
A / D converters used in such image processing devices and digital signal processors are required to operate at higher speed.

A flash type A / D converter is known as an A / D converter capable of high-speed operation. This flash type A / D converter is, for example, when this is an n-bit flash type A / D converter,
A total of (2 ⁿ -1) comparators are operated simultaneously and A
/ D conversion. These total (2 ⁿ −
1) To each of the comparators, reference reference voltages which are obtained by dividing the reference voltage using a ladder resistor in which a total of 2 ⁿ resistance elements having the same resistance value are connected in series are input respectively. . Therefore, the individual comparators are
The comparison reference voltage input to each and the analog signal voltage are compared. Also, an encoded n-bit digital signal is output based on the comparison result by such a total of (2 ⁿ -1) comparators. According to such a flash type A / D converter, a digital signal corresponding to the input analog signal voltage can be obtained at a much higher speed than the integration type A / D converter or the successive approximation type A / D converter. it can.

Regarding the A / D converter capable of high-speed operation, Japanese Patent Publication No. 2-39136 discloses a technique related to what is called a two-step flash type A / D converter in recent years. The 2-step flash type A / D converter disclosed in Japanese Patent Publication No. 2-39136 is
For example, if this is an (m + n) -bit A / D converter, first (2 ^m -1) comparators are used to perform A / D conversion corresponding to the upper m bits, and then the upper m bits are equivalent. Based on the result of the A / D conversion, a total of (2 ⁿ −1) different comparators are used to perform A / D conversion corresponding to the lower n bits. Therefore, the total number of comparators used in the 2-step flash A / D converter is (2 ^{(m + n)} −2).
This is a number, and can be greatly reduced compared to the general flash type A / D converter described above.

Also, such a two-step flash type A
In recent years, a chopper type comparator has been used as a comparator of a / D converter. This chopper type comparator is a CMOS (complementary metal oxide se
miconductor) First, input analog signal voltage to the capacitor connected in series to the input of the inverter.
By shorting its input and output of the CMOS inverter, a charge Q corresponding to the analog signal voltage is stored in the capacitor. After that, the capacitor to which the analog signal voltage is input is connected to the comparison reference voltage. At this time, the output of the CMOS inverter becomes an output according to the positive or negative value of the difference between the analog signal voltage and the comparison reference voltage.

[0007]

However, even in the above-mentioned two-step flash type A / D converter,
Although the number is smaller than that of a normal flash A / D converter, there is a problem that the number of comparators used is very large. For example, an 8-bit 2-step flash A / D converter requires a total of (2 ⁴ +2 ⁴ −2 = 30) comparators.

The present invention has been made to solve the above conventional problems, and provides an A / D converter that operates as a two-step flash type and can reduce the number of chopper type comparators used. With the goal.

[0009]

According to the present invention, among a plurality of comparison reference voltages obtained by dividing a reference voltage by using a ladder resistor in which a plurality of resistance elements are connected in series, a plurality of comparison reference voltages having different voltages are provided. In the A / D converter for simultaneously comparing the input analog signal voltage with a comparator group including a plurality of chopper type comparators, a plurality of resistor elements are connected in series to obtain a plurality of comparison reference voltages VL. Is further connected in series, and the ladder resistor is configured so as to obtain the comparison reference voltage VH from each of the series connection points of the resistance element groups, and the analog signal is input to the input of each of the chopper type comparators. It is provided for each of the chopper type comparators for selectively inputting a voltage or inputting the comparison reference voltage, and is provided to the input. For the connected switch SWI and switch SWR and each of the chopper type comparators, the comparison reference voltage VH is input as an input to the other contact of the switch SWR facing the contact of the switch SWR connected to its input. Either one of them is input, or one of the resistance element groups, or at least one of the comparison reference voltages VL from at most the same number n as the number of the resistance element groups is input, A switch SWH and switches SWL1 to SWL provided for each of the chopper type comparators for selectively switching these inputs.
n and an analog signal voltage by turning off the corresponding switch SWR, turning on the switch SWI, and resetting each of the chopper type comparators for each of the chopper type comparators that is first performed as an A / D conversion operation. For each of the chopper type comparators that are secondly performed as the input operation and the A / D conversion operation, the corresponding switch SWI is turned off, the switch SWR is turned on, the switch SWH is turned on, and the chopper is turned on. High-order bit conversion operation by detecting the output of each type comparator, and thirdly as the A / D conversion operation, for each of the chopper type comparators, the corresponding switch SWI is turned off,
By turning on the switch SWR, turning on any one of the switches SWL1 to SWLn according to the output result of each chopper type comparator immediately after the upper bit conversion operation, and detecting the output of each chopper type comparator. The above object is achieved by providing a conversion control circuit for controlling the analog signal voltage input operation, the upper bit conversion operation, and the lower bit conversion operation of the lower bit conversion operation.

[0010]

The present invention is based on the two-step flash type A / D.
Focusing on the converter, the plurality of comparators used for A / D conversion of upper bits and the plurality of comparators used for A / D conversion of lower bits do not operate at the same time. That is, the present invention has been made by finding a configuration in which a plurality of comparators that perform A / D conversion of such upper bits and a plurality of comparators that perform A / D conversion of such lower bits are shared. Is.

FIG. 1 is a circuit diagram showing a circuit around one of the comparators used, which is a feature of the present invention.

In FIG. 1, the chopper type comparator CP is one that can be used in the A / D converter of the present invention. The chopper type comparator CP
Is composed of CMOS inverters CPa and CPb, capacitors C1 and C2, and switches SWCa and SWCb.

In the chopper type comparator CP,
When comparing the magnitude relationship of two voltages, one of the voltages is first input to the input of the chopper type comparator CP, and both the switches SWCa and SWCb are turned on. As a result, electric charges corresponding to the voltage input at this time are stored in the capacitors C1 and C2. After this, the switch S
Both WCa and the switch SWCb are turned off, and the other voltage to be compared is input to the input of the chopper type comparator CP. At this time, the output of the chopper type comparator CP follows the sign of the difference between the two voltages to be compared.

In FIG. 1, the switch SWI and the switch SW are connected to the input of the chopper type comparator CP.
R and are connected. The switch SWI has A /
An analog signal voltage to be D-converted is input. On the other hand, a switch SWH and switches SWL1 to SWLn are connected to the switch SWR. To each of the switches SWH and the switches SWL1 to SWLn, comparison reference voltages having different voltages, which are obtained by dividing the reference voltage by using a ladder resistor in which a large number of resistance elements are connected in series, are input.

The ladder resistor used in the present invention, which is not shown in FIG. 1, has a plurality of resistance elements connected in series, and a plurality of resistance element groups for obtaining a plurality of comparison reference voltages VL are further connected in series. The comparative reference voltage VH is obtained from each series connection point of the groups. The plurality of comparison reference voltages VL having different voltages are, for example, V
L1 to VLn. Similarly, the plurality of comparison reference voltages VH having different voltages are, for example, VH1 to VHn. In the A / D converter of the present invention, a plurality of circuits shown in FIG. 1 are used for the ladder resistance having such a configuration.

In FIG. 1, the A / D conversion operation is such that the analog signal voltage input operation is first performed, the upper bit conversion operation is performed second, and the lower bit conversion operation is performed third. is there.

In the analog signal voltage input operation, the switch SWR is turned off and the switch SWI is turned on to input the analog signal voltage VIN to the chopper type comparator CP. At this time, in the analog signal voltage input operation, the chopper type comparator CP is reset. That is, in FIG. 1, by turning on both the switches SWCa and SWCb, charges corresponding to the analog signal voltage VIN are stored in the capacitors C1 and C2.

Next, in the high-order bit conversion operation, the switch SWI is turned off and the switch SWR is turned on. Further, by turning on the switch SWH, the comparison reference voltage VH obtained from one of the resistance element groups having serial connection points is input to the chopper type comparator CP.

Next, in the lower bit conversion operation, the switch SWI is turned off, the switch SWR is turned on, and the switch SWH is turned off. Also, based on the result of the upper bit conversion operation, the switch SWL1
One of SWLn is turned on. Therefore, according to the present invention, it is possible to reduce the number of comparators used to almost half as compared with the conventional two-step flash A / D converter.

In the A / D converter of the present invention, it is possible to omit the switch SWR shown in FIG. In this case, the number of switches used can be reduced, and, for example, the degree of integration can be improved.

However, if the switch SWR is omitted, the SWR mounting position is always on. Therefore, at the time of the analog signal voltage input operation,
When the switch SWI is turned on, the switch SW is used as a load of the input analog signal voltage VIN.
The amount of H and the amount of the switches SWL1 to SWLn are increased. Such an increase in load is caused by these switches S
This is due to the floating capacitance of the WH and the switches SWL1 to SWLn and the wiring related to these, and even if all of these switches SWH and the switches SWL1 to SWLn are off, the load increases.

Therefore, in order to avoid such an increase in load, it is effective to provide the switch SWR as in the present invention. The analog signal voltage VIN as described above
The increase of the load on the capacitor increases the time for accumulating charges in the capacitors C1 and C2 according to the analog signal voltage VIN, and as a result, the conversion time of the entire A / D conversion is extended.

[0023]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a 4-bit A / to which the present invention is applied.
It is a block diagram which shows the structure of a D converter.

As shown in FIG. 2, A of the present embodiment
The / D converter includes a reference voltage power source 10 and a ladder resistor 1
2, a switch network 14, a switch network 16, a comparator group 22, an upper bit register 24, and a lower bit register 26.
Further, the A / D converter of this embodiment includes a conversion control circuit (not shown in FIG. 2) for controlling the analog signal voltage input operation, the upper bit conversion operation, and the lower bit conversion operation. There is.

The reference voltage power supply 10 is a constant voltage power supply that generates a reference voltage. The reference voltage generated by the reference voltage power supply 10 is applied to the extreme ends of the resistance elements of the total (2 ⁴ = 16) of the ladder resistors 12 connected in series, and a total of 15 comparison reference voltages VH1 to VH1. VH3, VL11-V
L13, VL21 to VL23, VL31 to VL33, V
The voltage is divided into L41 to VL43.

The ladder resistor 12 is, as shown in FIG.
A total of 16 resistance elements R1 to R having the same resistance value
16 are connected in series. In the ladder resistor 12, the resistance elements R1 to R4 form a first resistance element group, the resistance elements R5 to R8 form a second resistance element group, and the resistance elements R9 to R12 form a first resistance element group. 3 is a resistance element group, and the resistance elements R13 to R16 are a fourth resistance element group. That is, the ladder resistor 1
2, a total of four resistance elements R1 to R16 are connected in series to form a total of four resistance element groups, and a total of four such resistance element groups are further connected in series. It is that.

In the ladder resistor 12, the first resistor
The comparison reference voltage VH1 is obtained from the connection point (series connection point) between the resistance element group and the second resistance element group. The comparison reference voltage VH2 is obtained from the connection point between the second resistance element group and the third resistance element group. The comparison reference voltage VH3 is obtained from the connection point between the third resistance element group and the fourth resistance element group.

In the first resistance element group, the comparison reference voltages VL11 to VL1 are respectively connected from respective connection points of the four resistance elements R1 to R4 connected in series.
3 has been obtained. In the second resistance element group, the comparison reference voltages VL21 to VL2 are respectively connected from a total of three connection points of the resistance elements R5 to R8 connected in series.
3 has been obtained. In the third resistance element group, the comparison reference voltages VL31 to VL are respectively connected from a total of three connection points of the resistance elements R9 to R12 connected in series.
33 have been obtained. In the fourth resistance element group,
From the total of three connection points of the resistance elements R13 to R16 connected in series, the comparison reference voltages VL41 to VL41 to
VL43 has been obtained.

In FIG. 2, the switch network 14 includes a total of four switches SWI1 to SWI4.
(Hereinafter, collectively referred to as switch SWIn) and a total of four switches SWR1 to SWR4 (hereinafter, switch SWRn).
(Collectively referred to as)).

The switch network 16 has a total of 3
Individual switches SWH1 to SWH3 (hereinafter switch SW
Hn)) and a total of three switches SWL11 ...
SWL13 (hereinafter collectively referred to as switch SWL1n)
And a total of three switches SWL21 to SWL23 (hereinafter collectively referred to as switch SWL2n) and a total of three switches SWL31 to SWL33 (hereinafter switch SWL).
3n), and a total of three switches SWL41-
The switch SWL43 (hereinafter collectively referred to as switch SWL4n).

The comparator group 22 has a total of four chopper type comparators CP1 to CP4 (hereinafter collectively referred to as CPn).

FIG. 4 is a circuit diagram around the chopper type comparator used in this embodiment.

In FIG. 4, the chopper type comparator C provided with a total of three in the comparator group 22.
Pn internal circuit and the chopper type comparator CPn
The connections on the input side of are shown.

As shown in FIG. 4, the chopper type comparator CPn is the same as the aforementioned chopper type comparator CP shown in FIG. The chopper type comparator CPn is a CMOS inverter C
It is composed of Pan and CPbn, capacitors C1n and C2n, and switches SWCan and SWCbn.
The chopper type comparator CPn is configured to switch the switches SWCan and S when the analog signal voltage VIN is input.
Both WCbn are turned on, and charges corresponding to the voltage value of the analog signal voltage VIN are transferred to the capacitors C1n and C2.
Store in n. Further, after the input of the analog signal voltage VIN, the comparison reference voltages VHn, VL1n, VL2n, V
When any one of L3n and VL4n is input, an output corresponding to the positive or negative value of the difference between any one of these comparison reference voltages and the analog signal voltage VIN is performed.

As shown in FIG. 4, for each of the three chopper type comparators CPn in total, one switch SWIn in the switch network 14 and one switch SWRn are provided at the inputs thereof.
Are connected. Neither switch SWIn nor switch SWRn is turned on, and only one of them is always turned on. When the switch SWIn is turned on, the analog signal voltage VIN is input to the input of the chopper type comparator CPn. When the switch SWRn is turned on, the comparison reference voltages VHn and VL1n are input to the input of the chopper type comparator CPn.
Any one of VL2n, VL3n or VL4n is input.

A total of three of the chopper type comparators C
For all Pn (CP1 to CP3), the switch SWIn (S
All of WI1 to SWI3) are turned on. On the other hand, a total of three of the chopper type comparators CPn (CP1 to CP1
For all P3), both of the switches SWRn (SWR1 to SWR3) are turned on during the high-order bit conversion operation and during the low-order bit conversion operation.

Each of the chopper type comparators C
Regarding Pn (CP1 to CP3), the switches SWHn, SWL1n, SWL2n and SWL3 are connected to the other contacts of the switch SWRn facing the contacts of the switches SWRn (SWR1 to SWR3) connected to their inputs.
n and SWL4n are connected. The switch SW
Hn turns on / off the comparison reference voltage VHn. The switch SWL1n turns on / off the comparison reference voltage VL1n, the switch SWL2n turns on / off the comparison reference voltage VL2n, the switch SWL3n turns on / off the comparison reference voltage VL3n, and the switch SWL4n turns on / off. The comparison reference voltage VL4n is turned on / off.

First, with respect to the first chopper type comparator CP1, the switch SWH1 is provided,
The comparison reference voltage VH1 obtained from the connection point between the first resistance element group and the second resistance element group is turned on / off by the switch SWH1. Also, the switch S
WL11 is provided, and the comparison reference voltage VL11 of the first resistance element group is turned on / off by the switch SW11. The SWL21 is provided, and the reference voltage VL21 obtained from the second resistance element group is turned on / off by the switch SWL21. The SWL31 is provided, and the comparison reference voltage VL31 obtained from the third resistance element group is turned on by the switch SWL31.
Turned off. The switch SWL41 is provided, and the comparison reference voltage VL4 obtained from the fourth resistance element group.
1 is turned on / off by the switch SWL41.

Next, with respect to the second chopper type comparator CP2, the switch SWH2 is provided, and the comparison reference voltage VH2 obtained from the connection point between the second resistance element group and the third resistance element group. Is the switch S
It is turned on / off by WH2. The switch SWL1
2 is provided, and the comparison reference voltage VL12 obtained from the first resistance element group is turned on / off by the switch SWL12. The switch SWL22 is provided,
The comparative reference voltage V obtained from the second resistance element group
L22 is turned on / off by the switch SWL22. The switch SWL32 is provided, and the comparison reference voltage VL32 obtained from the third resistance element group is turned on / off by the switch SWL32. The switch SWL42 is provided, and the reference voltage VL42 obtained from the fourth resistance element group is supplied to the switch SWL42.
Is turned on and off.

Next, with respect to the third chopper type comparator CP3, the switch SWH3 is provided, and the comparison reference voltage VH3 obtained from the connection point between the third resistance element group and the fourth resistance element group. Is the switch S
Turned on and off at WH3. The switch SWL13
Is provided and the comparison reference voltage VL13 obtained from the first resistance element group is turned on / off by the switch SWL13. The switch SWL23 is provided, and the comparison reference voltage VL obtained from the second resistance element group.
23 is turned on / off by the switch SWL23.
The switch SWL33 is provided, and the comparison reference voltage VL33 obtained from the third resistance element group is turned on / off by the switch SWL33. The switch S
WL43 is provided, and the comparison reference voltage VL43 obtained from the fourth resistance element group is supplied to the switch SWL43.
Is turned on and off.

The switches SWHn (SWH1 to SWH
3), SWL1n (SWL11 to SWL13), SWL
2n (SWL21 to SWL23), SWL3n (SWL
31-SWL33) and SWL4n (SWL41-SW
The configuration of L43) is as described above, and is configured in a network with respect to the ladder resistor 12. or,
The switch network 16 has such a configuration.

In the switch network 16 having such a configuration, first, all the switches SWHn are turned on during the high-order bit conversion operation. on the other hand,
The switches SWL1n, SWL2n, SWL3n and SWL4n are all turned off. The first chopper type comparator CP1 compares the analog signal voltage VIN with the comparison reference voltage VH1. The second chopper type comparator CP2 makes a comparison with the comparison reference voltage VH2. The third chopper type comparator CP3 compares with the comparison reference voltage VH3. A / D conversion of the upper bits of the analog signal voltage VIN is performed according to the comparison result of the chopper type comparator CPn. The A / D conversion result is output to the upper bit register 24.

Next, during the lower bit conversion operation, all the switches SWHn (SWH1 to SWH3) are turned off. The switches SWL1n, SWL2n, and SWL are based on the result of the upper bit conversion operation.
Any one of 3n and SWL4n is turned on. This relationship is as follows.

(1) When the analog signal voltage VIN is equal to or lower than the comparison reference voltage VH1 during the high-order bit conversion operation: the switches SWL11 and SW
L12 and SWL13 are turned on, and other switches are turned off.

(2) When the analog signal voltage VIN is higher than the comparison reference voltage VH1 and lower than the comparison reference voltage VH2: The switches SWL21, SWL22 and SWL23 are turned on,
The other switches are off.

(3) When the analog signal voltage VIN is higher than the comparison reference voltage VH2 and lower than or equal to the comparison reference voltage VH3: the switch S
WL31, SWL32, and SWL33 are turned on, and other switches are turned off.

(4) When the analog signal voltage VIN is higher than the comparison reference voltage VH3: The switches SWL41, SWL42 and SWL43 are turned on and the other switches are turned off.

When the respective switches are turned on and off and the comparator group 22 is connected to the predetermined resistance element group in the lower bit conversion operation, all the comparators CPn are supplied with the analog signal voltage VIN. Are compared, and the output result is the A / D conversion result. The A / D conversion result is output to the lower bit register 26.

FIG. 5 is a circuit diagram of a bit register circuit used in this embodiment.

In FIG. 5, the circuit of the upper bit register 24 or the lower bit register 2 is used.
A circuit diagram of circuit 6 is shown. The high-order bit register 24 includes an encoder 30, two flip-flops 32 and 34 in total, and a decoder 36. The lower bit register 26 is composed of the encoder 30 and two flip-flops 32 and 34 in total. The decoder 36 is not used in the lower bit register 26.

The encoder 30 includes the comparators CPn (CP1 to CP3) in the comparator group 22.
Outputs OUTn (OUT1 to OUT)
Enter 3). The encoder 30 outputs the output OUT
A value of "0" when all 1 to OUT3 are in the L state, a value of "1" when only the output OUT1 is in the H state, the output OU
"2" when only two values of T1 and OUT2 are in H state
Value, and a two-digit binary number corresponding to these values, which is a value of "3" when all the outputs OUT1 to OUT3 are in the H state, are output to the two flip-flops 32 and 34 in total.

The flip-flops 32 and 34 store the 2-digit binary number output from the encoder 30.
The outputs of the flip-flops 32 and 34 are the high-order bit output DH when it is of the high-order bit register 24, and the low-order bit output when it is of the low-order bit register 26. It becomes the output DL.

The decoder 36 is provided only in the upper bit register 24. The decoder 36 includes the switches SWL1n (SWL11 to SWL13), the switches SWL2n (SWL21 to SWL23), the switches SWL3n (SWL31 to SWL33), and
A total of four signal lines corresponding to the switches SWL4n (SWL41 to SWL43) are output. That is, when any one of the signal lines is in the H state, the corresponding switch is turned on.

FIG. 6 is a time chart showing the operation of this embodiment.

In FIG. 6, the analog signal voltage input operation performed first as the A / D conversion operation is
It is performed three times in total from t1 to t2, time t4 to t5, and time t7. The higher bit conversion operation performed second as the A / D conversion operation is time t2 to t3 and time t5.
~ T6, twice in total. The lower bit conversion operation thirdly performed as the A / D conversion operation is performed at times t3 to t4.
, T6 to t7, twice in total.

As shown in the time chart of FIG. 6, during the first analog signal voltage input operation, the switch SWIn and the switch SWC are operated.
An and the switch SWCbn are turned on, and the switch SWRn, the switch SWHn, and the switches SWL1n to SWL4n are turned off. Further, during the upper bit conversion operation performed second, the switch SWIn, the switch SWCan, and the switch S
WCbn and the switches SWL1n to SWL4n are turned off, and the switches SWRn and S
WHn turns on. During the third lower bit conversion operation, the switch SWRn is turned on, and the switch SWIn, the switch SWCan, the switch SWCbn, and the switch SWHn are turned off. or,
During this lower bit conversion operation, the switch SWL1
Any one of n to SWL4n is turned on.

As described above, according to the present embodiment, a 4-bit 2-step flash A / D converter can be constructed using a total of three chopper type comparators CP1 to CP3. Similarly, with respect to 4 bits, the above-mentioned flash A / D converter has a total of 1
Requires 5 comparators. In addition, the above-mentioned conventional 2
The step flash type A / D converter required a total of 6 comparators. According to the present embodiment, the number of comparators used can be reduced as compared with these conventional A / D converters, and the degree of integration can be improved.

[0059]

As described above, according to the present invention, 2
It is possible to reduce the number of chopper type comparators used that operate as a step flash type.
An excellent effect that a D converter can be provided can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a circuit around a comparator used in the present invention showing the gist of the present invention.

FIG. 2 is a block diagram showing a configuration of an A / D converter according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a ladder resistor used in the above embodiment.

FIG. 4 is a circuit diagram of a circuit of a chopper type comparator used in the above-mentioned embodiment and a circuit around this.

FIG. 5 is a circuit diagram of an upper bit register or a lower bit register used in the above embodiment.

FIG. 6 is a time chart showing the operation of the embodiment.

[Explanation of symbols]

 10 ... Reference voltage power supply 12 ... Ladder resistance 14, 16 ... Switch network 22 ... Comparator group 24 ... Upper bit register 26 ... Lower bit register 30 ... Encoder 32, 34 ... Flip-flop 36 ... Decoder CP, CPn ... Chopper type comparator CPa, CPb, Cpan, CPbn ... CMOS inverters C1, C2, C1n, C2n ... Capacitors R1 to R16 ... Resistor elements

Claims (1)

[Claims] 1. A plurality of comparison reference voltages having different voltages among a plurality of comparison reference voltages obtained by dividing a reference voltage by using a ladder resistor in which a plurality of resistance elements are connected in series, and an input analog signal voltage. In an A / D converter that simultaneously compares a plurality of resistance elements in series in a comparator group composed of a plurality of chopper type comparators, a plurality of comparison reference voltages V
A plurality of resistance element groups for obtaining L are further connected in series, and the comparison reference voltage VH is obtained from each series connection point of the resistance element groups.
The chopper type comparator, wherein the ladder resistor is configured so as to obtain, and for each of the chopper type comparators, the analog signal voltage is input to the input, or the comparison reference voltage is input to the chopper type comparator. A switch SWI and a switch SWR which are provided for each input and are connected to its input, and an input to the other contact of the switch SWR facing the contact of the switch SWR connected to its input for each of the chopper type comparators. Either one of the comparison reference voltages VH is input, or one of the resistance element groups is selected, and one of the comparison reference voltages VL is selected from the same number n at most as the number of the resistance element groups. One of the chopper type comparators, which inputs one of them or selectively switches between these inputs. Switch SWH and switches SWL1 to SWLn, and the corresponding switch S for each of the chopper type comparators that first performs the A / D conversion operation.
The analog signal voltage input operation by turning off WR, turning on the switch SWI, and resetting each of the chopper type comparators, and secondly performing the A / D conversion operation, each of the chopper type comparators, A high-order bit conversion operation by turning off the switch SWI, turning on the switch SWR, turning on the switch SWH, and detecting the output of each of the chopper type comparators, and thirdly as the A / D conversion operation. For each of the chopper type comparators, the switch SWI is turned off, the switch SWR is turned on, and the switch S according to the output result of each chopper type comparator immediately after the upper bit conversion operation.
Controls the analog signal voltage input operation, the upper bit conversion operation, and the lower bit conversion operation of the lower bit conversion operation by turning on any one of WL1 to SWLn and detecting the output of each of the chopper type comparators. An A / D converter comprising a conversion control circuit.