JPH0499356A - Integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the rise time and fall time of output signals by using a circuit structure in which input/output signal pads connected with input/output buffers have smaller areas than other pads so as to decrease parasitic capacitance around the input/output pads. CONSTITUTION:An ECL integrated circuit 1 includes a cell array 2, input/output buffer arrays 3, conventional square signal pads 4, 5 and 6, and smaller square signal pads 7 and 8. Each output buffer 31 has an input terminal 32 connected with a signal line from the cell array and an output terminal 33 connected with both a signal pad and a static protective element. The output terminal has capacitive elements connected: they are the parasitic capacitance C1 between the signal pad and the substrate, the parasitic capacitance C2 between the substrate and the conductor from the output buffer and the pad, and the equivalent capacitance C3 corresponding to the protective element. According to this configuration, it is possible to decrease rise and fall time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with reduced capacitance at input/output terminals.

[Conventional technology]

An example of a conventional master slice type semiconductor integrated circuit device is shown in FIG. As shown in the figure, a semiconductor integrated circuit device 1 includes an internal cell array 2, an input/output column buffer column 3, a signal pad 4, and electrostatic discharge protection elements 9, 10, 11, 12, 1.
3. It has a power band 14. By arbitrarily changing the pattern of the aluminum process, semiconductor integrated circuit devices having desired functions are realized.

In this type of semiconductor integrated circuit device, an aluminum pattern 15.21 of the input buffer is arranged at the position of the input buffer used, and the input buffer 3, signal pad 4, and electrostatic damage protection element 10.12 are arranged as follows. Signal wiring 17
．． It was connected by 23. The output buffer aluminum pattern 18 is located at the location of the output buffer used.
．． 24 was arranged, and the output buffer 3, signal pad 4, and electrostatic discharge protection elements 11 and 13 were connected by a signal wiring t20°26. The signal pad 4 has 1 side on each side to enable bonding by automatic wire bonding equipment.
They had the same shape of about 00 μm.

[Problem to be solved by the invention]

In this conventional master slice type semiconductor integrated circuit device, since the signal pads 4 have the same shape with a size of about 100 μm, input/output waveforms are affected by parasitic capacitance generated in the tube between the signal band and the substrate of the semiconductor integrated circuit device. There is a problem that the rise time and fall time increase.

An object of the present invention is to provide a semiconductor integrated circuit device in which the rise time and fall time due to such parasitic capacitance are shortened.

[Problem to be solved by the invention]

A semiconductor integrated circuit device of the present invention includes an internal cell array, an input/output buffer, and a signal and power supply pad. It is also formed in a small area.

(Function) According to the present invention, by forming the input/output signal pad connected to the input/output buffer to have a smaller area than other pads, the parasitic capacitance of the input/output pad is reduced, and the output waveform Shorten the rise time and fall time.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of a master slice type semiconductor integrated circuit device according to a first embodiment of the present invention. An internal cell array 2 is included in a semiconductor integrated circuit 1 whose circuit format is ECL.
, input/output buffer row 3, square signal pad 4°5.6 with side 1100p, same as conventional one, - square signal pad 7.8 which is much smaller than conventional one with side 30 μm, electrostatic damage protection element 9410.11, 12 , 13, and a power supply pad 14 are arranged.

A high frequency signal, here a clock signal with a frequency IGH2, is configured to be input to a small signal pad 7, and this signal pad 7 is connected to the input terminal 16 of the input buffer aluminum pattern 15 and the electrostatic damage protection element. 1
0 by a signal wiring 17. Similarly, the clock signal with the frequency IGH2 is configured to be output to a small signal pad 8, and this signal pad 8 is connected to the output terminal 19 of the aluminum pattern 18 of the output sofa and the electrostatic damage protection element 11 through the signal wiring. 20.

On the other hand, a low frequency signal, here the frequency is 500MH2
The following data signals are input into a large signal band 5, and this signal pad 5 is connected to the input terminal 22 of the aluminum pattern 21 of the input buffer and the electrostatic damage protection element 12 by a signal wiring 23. ing. Similarly, the following data signals with a frequency of 500 MH2 are configured to be output to the large signal pad 6, and this signal pad 7
The signal wiring 26 is connected to the output terminal 25 of the aluminum pattern 24 of the output buffer and the electrostatic discharge protection element 13.
connected by.

Note that the power supply pad and the square signal pads 4 to 6 with a side of 100 μm are wire-bonded using an automatic wire bonding machine, and the square signal pads 7 and 8 with a side of 30 μm are wire-bonded manually because the pad size is small. Wire bonded.

FIG. 2 is a block diagram showing an example of an output buffer.

The input terminal 32 of the output buffer 31 receives the signal from the internal cell array shown in FIG. 1, the output terminal 33 is connected to the signal band and the electrostatic damage protection element, and the output terminal is connected to the signal pad. Parasitic capacitance CI that occurs between the boards, parasitic capacitance C2 that occurs between the wiring from the output sofa to the band and the board, and equivalent capacitance C3 that corresponds to the electrostatic breakdown protection element.
is connected. Parasitic capacitance C1 that occurs between the signal band and the board when the signal pad is a square with 1100tI on each side
l is 0.2 pF, and when the signal pad is a square with a side of 30 μm, the parasitic capacitance CI2 generated between the signal band and the substrate is o
, ot8p F, C2 is O, ]pF, C3 is 1.0p
Assuming F, the simulation results of the output waveforms of each output buffer shown in FIG. 2 are: rise time t11-119 ps when C11=0.2 pF, rise time tr=90 ps, CI2=0.018 p F The rise time for tr 2 = 102 ps.

The rise time t t 2 =77 ps, and the rise time and fall time can be improved by 14%.

FIG. 3 is a layout diagram of a master slice type semiconductor integrated circuit device according to a second embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals and detailed explanations are omitted.

In this embodiment, no electrostatic damage protection element is connected between the small signal pad 7.8 of 30 μm and the input/output buffer. Therefore, the equivalent capacitance of 1 pF of the electrostatic discharge protection element is not connected to the signal terminal. The single output capacity is
0, which corresponds to the parasitic capacitance of a 30 μm square signal pad.
, 018pF, and the parasitic capacitance of the wiring from the output sofa to the pad, 0.1pF, totaling 0.118pF,
The rise time and fall time of the output waveform can be made smaller.

[Effects of the Invention] As explained above, in the present invention, at least the input/output signal pad connected to the traffic buffer is formed to have a smaller area than other pads, so that parasitic It is possible to reduce the capacitance and shorten the rise time and fall time of the output waveform. Further, since only the input/output band is made smaller, the other pads can be automatically wire bonded, and the number of wire bonding steps does not increase.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a master slice type semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a block diagram of an example of an output buffer, and FIG. 3 is a semiconductor integrated circuit according to a second embodiment of the present invention. Device Layout Diagram FIG. 4 is a layout diagram of a conventional semiconductor integrated circuit device. DESCRIPTION OF SYMBOLS 1... Semiconductor integrated circuit device, 2... Internal cell array, 3... Input/output buffer row, 4-6... 100 μm
Signal pad, 7, 8...30μm Signal pad, 9-1
3... Electrostatic damage protection element, 14... Power supply pad, 1
5... Aluminum pattern, 16... Input terminal,
17... Signal wiring, 18... Aluminum pattern, 19... Output terminal, 20... Signal wiring, 21...
・Aluminum bar, turn, 22...input terminal, 23
...Signal wiring, 24...Aluminum pattern, 2
5... Output terminal, 26... Signal wiring, 31... Output buffer, 32... Input terminal, FIG. 2 CI. Figure 3

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device that includes an internal cell array, an input/output buffer, and signal and power supply pads, and connects these with a desired wiring pattern, at least an input/output signal pad connected to the input/output buffer is provided. A semiconductor integrated circuit device characterized in that the pad is formed in a smaller area than other pads.