JP2929784B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to connection of an electrostatic discharge protection element of a master slice type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art FIG. 3 is a plan view of the left half showing the layout of a conventional master slice type semiconductor integrated circuit device, and FIG. 4 is a plan view of the right half of FIG. FIG. 3 and FIG. 4 are an overall plan view.

Referring to FIGS. 3 and 4, a conventional semiconductor integrated circuit device 21 includes an internal cell array 22, an I / O buffer column 23, signal pads 27, 28, 29, a power supply pad 213, an electrostatic discharge protection. Element 210, 211, 212
, Wirings 215 and 217, an I-buffer aluminum pattern 214, and an O-buffer aluminum pattern 216. Each I / O buffer column 23 has five I / O buffers.

As shown in FIGS. 3 and 4, such a conventional master slice type semiconductor integrated circuit device includes an internal cell array 22, an I / O
It had the same number of signal pads 27, 28, 29 as the buffer row 23, the I / O buffers 24, 25, 26, the same number of electrostatic breakdown protection elements 210, 211, 212 as the I / O buffers, and the power supply pads 213. .

Each semiconductor integrated circuit device 21 has been realized by changing the pattern of the aluminum process according to the circuit. The location of the I buffer used is
A buffer aluminum pattern 214 is placed,
The buffer, the signal pad 27 and the electrostatic breakdown protection element 210 were connected by the wiring 215. The position of the O-buffer used is the aluminum pattern 216 of the O-buffer.
Are arranged, and the O buffer, the signal pad 28 and the electrostatic discharge protection element 211 are connected by the wiring 217.

[0006]

In the conventional master slice type semiconductor integrated circuit device 21, since the signal pad 28 is connected to the electrostatic discharge protection element 211, a large capacitance is connected to the signal wiring. However, there is a problem that input and output waveforms are deteriorated.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide a semiconductor integrated circuit device in which a large capacity is not connected to a signal wiring.

[0008]

According to the present invention, there is provided an internal cell array, an I / O buffer array in which a plurality of I / O buffers are arranged, and the I / O buffer outside the I / O buffer array. The semiconductor integrated circuit device having the same number of electrostatic discharge protection elements and one more pad than the number of the I / O buffers on the outside of the I / O buffer row. Pad and the first
A first node between the second pad adjacent to the first pad and the first pad is connected by a first wiring, and the first node and the second pad are connected by a second wiring. The first node and the signal terminal of the first electrostatic discharge protection element among the electrostatic discharge protection elements are connected by a third wiring, and the first pad and the I / O buffer column are connected. Among them, the first I / O buffer is connected to a fourth wiring.

In the above-mentioned conventional master-slice type semiconductor integrated circuit device, the signal terminals of the respective electrostatic discharge protection elements are connected to one pad, respectively. An integrated circuit device includes one or more electrostatic discharge protection elements having signal terminals connected to one pad, and one or more electrostatic discharge protection elements having signal terminals connected to two pads.

[0010]

FIG. 1 is a plan view showing a left half of an arrangement of a master slice type semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a plan view showing a right half of FIG. 1 and 2, the overall arrangement is obtained.

1 and 2, an internal cell array 1 is provided in a semiconductor integrated circuit device 11 having a circuit type of ECL.
2, I / O buffer row 13, signal pads 14, 15, 1
6, 17, 18, 19, 110, 111, 112, 11
3, 114, 115, 116, power supply pad 117, electrostatic discharge protection elements 118, 119, 120, 121, 12
2,123,124,125,126,127,128
Is arranged.

A signal pad 15 to which a clock signal having a frequency of 1 GHz is input is connected to the aluminum pattern 12 of the I buffer.
9, the signal pad 15 and the node 132 are connected by a line 133, the signal pad 14 and the node 132 are connected by a line 134, and the node 132 and the electrostatic discharge protection are connected. The signal terminal 135 of the element 118 is connected by a wiring 136.

The signal pad 16 is connected to the input terminal 138 of the I-buffer aluminum pattern 137 by a wiring 139, and the signal pad 16 is connected to the signal terminal 140 of the electrostatic discharge protection element 119 by a wiring 141. .
The signal pads 17, 18, and 19 are connected in the same manner as the signal pad 16.

A signal pad 111 to which a clock signal of a frequency of 1 GHz is output is an aluminum pattern 1 of an O buffer.
42, connected to the output terminal 143 by a wiring 144,
The signal pad 111 and the node 145 are connected by a wiring 146, and the signal pad 112 and the node 145 are connected by a wiring 1
47, the node 145 and the electrostatic discharge protection element 1
The 24 signal terminals 148 are connected by wiring 149.

The signal pad 110 is connected to the output terminal 151 of the aluminum pattern 150 of the O-buffer by a wiring 152, and the signal pad 110 and the electrostatic discharge protection element 123 are connected.
Are connected to the signal terminal 153 by a wiring 154. The signal pads 113, 114, and 115 are connected similarly to the signal pad 110. As shown in an enlarged view of the wirings 133 and 146, the center of the aluminum wiring is narrowed to 1 μm in width and 25 μm in length as shown in FIG.

FIG. 8 is a block diagram showing the O buffer. 8, a signal from the internal cell array 12 shown in FIGS. 1 and 2 is input to an input terminal 42 of an O buffer 41, and an output terminal 43 is connected to a signal pad and an electrostatic discharge protection element. The output terminal corresponds to a parasitic capacitance C1 generated between the signal pad and the substrate, a parasitic capacitance C2 generated between the wiring from the output buffer to the signal pad and the electrostatic discharge protection element, and the electrostatic discharge protection element. The equivalent capacitance C3 is connected. Here, C1 = 0.2 pF, C
2 = 0.05 pF and C3 = 1 pF.

In the semiconductor integrated circuit device of the master slice type of this embodiment, after assembling into a wafer state and a package, a functional test is performed by an LSI tester, and a non-defective product is shipped. After mounting the semiconductor integrated circuit device on the device, the device maker connects between the terminals on the device to which the signal pads 14 and 15 shown in FIG.
When about 1 V is applied between the terminals of the device to which the terminals 12 and 111 are connected, a current of about several amperes flows between the terminals, the wires 133 and 146 melt, and the electrostatic breakdown protection element is signaled. It can be separated from the line, and the value of C3 in FIG. 4 can be set to 0.

The simulation results of the output waveform of the circuit of FIG. 8 when C3 = 1.0 pF and when C3 = 0 pF show rise times tr = 64 ps and 65 pF, respectively.
s, fall time tf = 60 = 4, 52 ps,
A 15% improvement in tf is possible. Before mounting on a device, an electrostatic discharge protection element is connected to the signal pad, and the semiconductor integrated circuit device is protected from electrostatic discharge.

FIG. 5 is a plan view showing the left half of the layout of the master slice type semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 6 is a plan view showing the right half of FIG. 5 and FIG. 6 together form a plan view of the whole.

5 and 6, a master slice type semiconductor integrated circuit device according to a second embodiment of the present invention includes an internal cell array 52, an I / O circuit, and a semiconductor integrated circuit device 51 having a circuit type of ECL. The buffer row 53, signal pads 54, 55, 56, 57, power supply pad 58, and electrostatic discharge protection elements 59, 510, 511 are arranged.

A signal pad 54 to which a clock signal having a frequency of 1 GHz is output is an aluminum pattern 51 of an O buffer.
2 is connected to the output terminal 513 by a wiring 514, the signal pad 54 and the node 515 are connected by a wiring 516, the signal pad 55 and the node 515 are connected by a wiring 517, and the node 515 and the electrostatic damage protection are connected. The signal terminal 518 of the element 59 is connected to the wiring 519.

The signal pad 56 for outputting a signal having a phase opposite to that of the signal pad 54 for outputting the clock includes an output terminal 521 of the aluminum pattern 520 of the O buffer and a wiring 522.
The signal pad 56 and the node 523 are connected by a wire 524, the signal terminal 526 of the electrostatic discharge protection element 510 and the node 523 are connected by a wire 527, and the signal pad 55 and the node 523 are connected by a wire 524. They are connected by a wiring 528.

The wirings 518 and 524 have a width of 1 .mu.m and a length of 25 .mu.m, as shown in FIG.
And thin.

In the present embodiment, the electrostatic discharge protection elements at the input / output terminals of the adjacent I / O buffer can be cut off after the device is mounted, and in particular, the waveform of high-speed complementary input / output can be improved.

[0025]

As described above, the present invention is particularly applicable to a master slice type semiconductor integrated circuit device.
A pad that is one more than the number of I / O buffers outside the I / O buffer row, and a first node between the first pad and a second pad next to the first pad is a first node; The first node is connected to the second pad and the second line, and the first node is connected to the signal terminal of the first electrostatic discharge protection element by the third line. When the first pad and the first I / O buffer are connected by the fourth wiring, the second wiring is blown after the assembly inspection of the semiconductor integrated circuit device and the mounting of the device. In addition, the electrostatic discharge protection element connected to the signal line can be removed, and the input / output waveform can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a left half of a layout of a master slice type semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a right half of FIG. 1;

FIG. 3 is a plan view showing the left half of the layout of a conventional master slice type semiconductor integrated circuit device.

FIG. 4 is a plan view showing a right half of FIG. 3;

FIG. 5 is a plan view showing the left half of the layout of a master slice type semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing a right half of FIG. 5;

FIG. 7 is an enlarged plan view showing wiring of the semiconductor integrated circuit device.

FIG. 8 is a block diagram showing an O buffer.

[Explanation of symbols]

11, 21, 51 Semiconductor integrated circuit device 12, 22, 52 Internal cell array 13, 23, 53 I / O buffer row 14, 15, 16, 17, 18, 19, 110, 11
1,112,113,114,115,116,21
3,58 power pad 118,119,120,121,122,123,1
24, 125, 126, 127, 128, 210, 21
1, 212, 59, 510, 511 Electrostatic discharge protection element 129, 137, 214 I-buffer aluminum pattern 130 Input terminal 131, 133, 134, 136, 139, 140, 1
46, 149, 152, 154, 215, 217, 51
4,516,517,522,527,528,52
4,519 Wiring 138,42 Input terminal 143,151,521,513,43 Output terminal 150,216,512,520 Aluminum pattern of O buffer 24,25,26 I / O buffer 41 O buffer 27,28,29, 54, 55, 56, 57 Signal pad 518, 526 Signal terminal of electrostatic discharge protection element C1 Parasitic capacitance generated between signal pad and substrate C2 Parasitic capacitance generated between wiring and substrate C3 Equivalent capacitance of electrostatic discharge protection element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/118 H01L 21/82 H01L 21/822 H01L 27/04

Claims (1)

(57) [Claims] 1. An internal cell array, an I / O buffer row in which a plurality of I / O buffers are arranged, and the same number of electrostatic discharge protection elements as the I / O buffers outside the I / O buffer row; A semiconductor integrated circuit device having a master slice arrangement and having one more pad than the number of the I / O buffers on the outside of the I / O buffer row, and a first pad among the pads and a pad adjacent to the first pad A first node between the second pad and the first pad is connected with a first wiring, the first node and the second pad are connected with a second wiring, A first node and a signal terminal of the first electrostatic discharge protection element of the electrostatic discharge protection element are connected by a third wiring, and the first pad and the first of the I / O buffer row are connected to each other. The I / O buffer is connected by a fourth wiring. Semiconductor integrated circuit device.