JPH0498841A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0498841A JPH0498841A JP2216635A JP21663590A JPH0498841A JP H0498841 A JPH0498841 A JP H0498841A JP 2216635 A JP2216635 A JP 2216635A JP 21663590 A JP21663590 A JP 21663590A JP H0498841 A JPH0498841 A JP H0498841A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- buried
- layer
- electrode pad
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 239000003989 dielectric material Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Wire Bonding (AREA)
Abstract
Description
この発明は、電極パッドを有する半導体装置に関する。 The present invention relates to a semiconductor device having an electrode pad.
第３図は、従来の集積回路用半導体装置の一例を示す。
この例の半導体装置の半導体基板３０は、第１の半導体
層３１、低抵抗の埋め込み層３２及び第２の半導体層３
３を下から上にこの順に有する。第２半導体層３３の上
には絶縁膜３４を介して電極パッド３５が設けられる。
電極パッド３５は、ワイヤボンディング等によって外部
接続するためのポンディングパッドであって、絶縁膜３
４の配線導体（図示せず）に比べて幅広（大面積）に形
成されている。FIG. 3 shows an example of a conventional semiconductor device for integrated circuits. The semiconductor substrate 30 of the semiconductor device of this example includes a first semiconductor layer 31, a low-resistance buried layer 32, and a second semiconductor layer 3.
3 in this order from bottom to top. An electrode pad 35 is provided on the second semiconductor layer 33 with an insulating film 34 interposed therebetween. The electrode pad 35 is a bonding pad for external connection by wire bonding or the like, and is
It is formed wider (larger area) than the wiring conductor No. 4 (not shown).
ところで、第３図の半導体装置の電極パッド３５と半導
体基板３０の裏面との間には、必然的に容量Ｃが存在す
る。この容量Ｃは、半導体装置の高周波性能に悪影響を
与える。例えば、第３図に示されるように、半導体基板
３０の裏面は、通常、アースに接続されるため、人力信
号が供給される電極パッド３５と半導体基板３０の裏面
とが、絶縁膜３４の容量Ｃ１と、第２半導体層３３の抵
抗Ｒ２と、埋め込み層３２の抵抗ＲＢ（抵抗値は低い）
と、埋め込み層３２と第１半導体層３１との間のｐｎ接
合容量Ｃ２と、第１半導体層３１の抵抗Ｒ１とを直列接
続した回路で電気的に接続されるので、入力信号の高周
波成分がアースへ漏れ、このため、入力信号が劣化して
しまう。
上述のように、電極パッド３５と半導体基板３０との間
の容量Ｃは、絶縁膜３４の容量Ｃ１と、埋め込み層３２
と第１半導体層３１との間のｐｎ接合容量Ｃ２とからな
る。これらの容量のうち、絶縁膜３４の容量Ｃ１は、絶
縁膜３４か電極パッド３５の直下に位置するため、容量
として機能する部分の面積は、電極パッド３５の面積に
等しいと考えられるが、埋め込み層３２と第１半導体層
３１との間のｐｎ接合容量Ｃ２は、このｐｎ接合が電極
パッド３５から数ミクロン深い位置にあるために、横方
向への広がり成分かかなり大きくなると考えられる。
この発明は、第１の半導体層、埋め込み層、及び第２の
半導体層を縦方向に二の順に有する半導体基板と、この
半導体基板の第２半導体層上に設けられた電極パッドと
を備えた半導体装置において、埋め込み層と第１半導体
層との間のｐｎ接合容量の横方向への拡がり成分を抑え
て、電極パッドと半導体基板裏面との間の容量を小さく
することを目的とする。Incidentally, a capacitance C necessarily exists between the electrode pad 35 of the semiconductor device shown in FIG. 3 and the back surface of the semiconductor substrate 30. This capacitance C adversely affects the high frequency performance of the semiconductor device. For example, as shown in FIG. 3, the back surface of the semiconductor substrate 30 is normally connected to ground, so that the electrode pad 35 to which the human input signal is supplied and the back surface of the semiconductor substrate 30 are connected to each other by the capacitance of the insulating film 34. C1, resistance R2 of the second semiconductor layer 33, and resistance RB of the buried layer 32 (resistance value is low)
The high-frequency components of the input signal are leaks to ground, thereby degrading the input signal. As described above, the capacitance C between the electrode pad 35 and the semiconductor substrate 30 is determined by the capacitance C1 of the insulating film 34 and the buried layer 32.
and a pn junction capacitance C2 between the first semiconductor layer 31 and the first semiconductor layer 31. Among these capacitances, the capacitance C1 of the insulating film 34 is located directly under the insulating film 34 or the electrode pad 35, so the area of the portion that functions as a capacitor is considered to be equal to the area of the electrode pad 35. It is considered that the pn junction capacitance C2 between the layer 32 and the first semiconductor layer 31 has a considerably large lateral spread component because this pn junction is located several microns deep from the electrode pad 35. The present invention includes a semiconductor substrate having a first semiconductor layer, a buried layer, and a second semiconductor layer in the order of two in the vertical direction, and an electrode pad provided on the second semiconductor layer of the semiconductor substrate. An object of the present invention is to reduce the capacitance between an electrode pad and the back surface of a semiconductor substrate by suppressing a lateral expansion component of a pn junction capacitance between a buried layer and a first semiconductor layer in a semiconductor device.
上記目的を達成するために、この発明による半導体装置
は、電極パッドの配設領域付近の埋め込み層及び第１半
導体層と、その周囲の埋め込み層及び第１半導体層とを
分離するように、少なくとも埋め込み層から第１半導体
層へ縦方向に延びる誘電体を具備する。
上記誘電体の横方向の断面形状を、電極パッドの外縁と
実質的に同一とするのが好ましい。In order to achieve the above object, a semiconductor device according to the present invention includes at least a structure in which a buried layer and a first semiconductor layer near an electrode pad arrangement region are separated from a buried layer and a first semiconductor layer around the region. A dielectric extends vertically from the buried layer to the first semiconductor layer. Preferably, the lateral cross-sectional shape of the dielectric is substantially the same as the outer edge of the electrode pad.
上述のように構成されたこの発明による半導体装置にお
いては、埋め込み層と第１半導体層との間のｐｎ接合容
量が誘電体によって囲まれた部分の容量に限定されるの
で、ｐｎ接合容量を小さくできる。したがって、入力信
号の高周波成分か電極パッドと半導体基板裏面との間の
容量を介して他に与える影響が小さくなる。
また、誘電体の横方向の断面形状を電極バットの外縁と
実質的に同一にすると、埋め込み層と第１半導体層との
間のｐｎ接合容量を最小にすることができる。In the semiconductor device according to the present invention configured as described above, the pn junction capacitance between the buried layer and the first semiconductor layer is limited to the capacitance of the portion surrounded by the dielectric, so that the pn junction capacitance can be reduced. can. Therefore, the influence of high frequency components of the input signal on others via the capacitance between the electrode pad and the back surface of the semiconductor substrate is reduced. Furthermore, when the lateral cross-sectional shape of the dielectric is made substantially the same as the outer edge of the electrode butt, the pn junction capacitance between the buried layer and the first semiconductor layer can be minimized.
第１図は、この発明の半導体装置の一実施例を製造する
方法の一例を示す。
この例では、半導体基板１０として、第１半導体層を成
すｐ型シリコン半導体層１１、例えばアンチモン拡散層
からなる低抵抗の埋め込み層１２、及び第２半導体層を
成すｎ型シリコンエビタキンヤル層１３を縦方向にこの
順に有する半導体基板を用いる。
そして、先ず、第１図Ａに示すように、この半導体基板
１０のｎ型シリコンエピタキシャル層１３の全表面を薄
く酸化して絶縁膜を成すシリコン酸化膜１４を形成し、
しかる後、シリコン酸化膜１４上にＮＳＣ（ノンドープ
ドシリケートガラス）膜１５をデポジットする。
次に、第１図Ｂに示すように、レジスト１６をマスクと
して、電極パッド形成予定部分の外縁を２．５ｐ幅でＮ
ＳＧ膜１５をエツチングで除去して開口１７を形成し、
しかる後、第１図Ｃに示すように、レジスト１６及び開
口１７の部分のシリコン酸化膜１４を除去する。
次に、第１図りに示すように、ＮＳＧ膜１５をマスクと
して、ｎ型シリコンエピタキシャル層１３及び埋め込み
層１２を貫通してｐ型シリコン半導体層１１に達するエ
ツチングを行い、トレンチ１８を形成する。
次に、第１図Ｅに示すように、前にマスクとして使用し
たＮＳＣ膜１５をエツチングで除去した後、トレンチ１
８の底部にボロンをイオン注入してストッパ領域１９を
形成し、しかる後、トレンチ１８の側壁を薄く酸化して
、シリコン酸化膜１４を形成する。
次に、第１図Ｆに示すように、トレンチ１８が完全に埋
め込まれるように、誘電体であるポリシリコン２０をデ
ポジットし、しかる後、最初に形成したシリコン酸化膜
１４の位置までポリシリコン２０をエツチングして平坦
にする。これにより、トレンチ１８て囲まれて、ｐ型シ
リコン半導体層（第１半導体層）１１、埋め込み層１２
、及びｎ型シリコンエピタキシャル層（第２半導体層）
１３は、トレンチ１８の周囲のすなわち外側のｐ型シリ
コン半導体層１１、埋め込み層１２、及びｎ型シリコン
エピタキシャル層１３と誘電体分離される。
次に、第１図Ｇに示すように、フィールド酸化を行なっ
てシリコン酸化膜１４を厚くした回路素子（図示せず）
を作り、しかる後、シリコン酸化膜１４上にワイヤボン
ディング用の電極パッド２１を形成する。この電極パッ
ド２１は、回路素子用の配線導体（図示せず）よりも幅
広（大面積）に形成される。
第２図Ａは、第３図に示された従来の半導体装置を示し
、また、第２図Ｂは第１図に示された方法によって製造
されたこの発明の半導体装置の実施例を示す（第１図Ｇ
に対応）。また、第２図Ｃは電極パッド２１の内側１０
０ｊ１に分離用誘電体（ポリシリコン２０）を形成した
この発明の半導体装置の実施例を示し、第２図りは電極
パッド２１の外側１００周に分離用誘電体（ポリシリコ
ン２０）を形成したこの発明の半導体装置の実施例を示
す。これらの図に示された電極パッドは、いずれも１辺
が５００８の正方形である。
次に示す第１表は、第２図Ａ及至りに示された半導体装
置の電極パッドと半導体基板裏面との間の容量の測定値
と、第２図Ａの従来例に対する第２図Ｂ、Ｃ及びＤのこ
の発明の各実施例の容量の減少率とを示す。
〔第１表〕
この第１表に示されているように、第２図Ｂ１Ｃ及びＤ
の、この発明の各実施例は、電極バ―ソドと半導体基板
裏面との間の容量を、第２図Ａの従来例に対して、それ
ぞれ３０％、１１％及び１８％減少させることができる
。したがって、これらの実施例によれば、電極パッド２
１と半導体基板１０の裏面との相互干渉を小さくでき、
高周波特性を向上させることができる。
最も好ましいのは、分離用誘電体を構成するポリシリコ
ン２０を電極パッド２１の外縁に沿うように形成した、
換言すればポリシリコン２ｏの横方向の断面形状を電極
パッド２１の外縁と実質的に同一にした第２図Ｂの実施
例であり、この実施例が容量を最も減少させることがで
きる。
なお、上記実施例においては、第１及び第２半導体層１
１及び１３をそれぞれｐ型シリコン半導体層及びｎ型シ
リコンエピタキシャル層としたが、シリコン以外の例え
ばゲルマニウム等の半導体であってもよい。
また、上述の実施例では、絶縁膜１４としてシリコン酸
化物を使用したが、他の絶縁物も使用でき、絶縁物を多
層構造にしてもよい。
また、上述の実施例では、分離用誘電体２ｏとしてポリ
シリコンを使用したが、他の誘電体も使用できる。
さらに、上述の実施例では、分離用誘電体２゜が内側と
外側の第１半導体層１１及び埋め込み層１２だけではな
く第２半導体層１３をも分離しているが、内側と外側の
第１半導体層１１及び埋め込み層１２を分離すれば十分
である。
ただし、第１図及び第２図の実施例のように、第２半導
体層１３も分離するようにすれば、トレンチの形成か容
易であり、半導体装置の製造か簡単になる。FIG. 1 shows an example of a method for manufacturing an embodiment of the semiconductor device of the present invention. In this example, the semiconductor substrate 10 includes a p-type silicon semiconductor layer 11 forming a first semiconductor layer, a low-resistance buried layer 12 formed of, for example, an antimony diffused layer, and an n-type silicon epitaxial layer 13 forming a second semiconductor layer. A semiconductor substrate is used which has the following structures in this order in the vertical direction. First, as shown in FIG. 1A, the entire surface of the n-type silicon epitaxial layer 13 of this semiconductor substrate 10 is thinly oxidized to form a silicon oxide film 14 forming an insulating film.
Thereafter, an NSC (non-doped silicate glass) film 15 is deposited on the silicon oxide film 14. Next, as shown in FIG. 1B, using the resist 16 as a mask, the outer edge of the area where the electrode pad is to be formed is formed with a width of 2.5p.
The SG film 15 is removed by etching to form an opening 17,
Thereafter, as shown in FIG. 1C, the resist 16 and the silicon oxide film 14 in the opening 17 are removed. Next, as shown in the first diagram, using the NSG film 15 as a mask, etching is performed to penetrate the n-type silicon epitaxial layer 13 and the buried layer 12 to reach the p-type silicon semiconductor layer 11, thereby forming a trench 18. Next, as shown in FIG. 1E, after removing the NSC film 15 previously used as a mask by etching, the trench 1 is etched.
A stopper region 19 is formed by ion-implanting boron into the bottom of the trench 8 , and then the side wall of the trench 18 is thinly oxidized to form a silicon oxide film 14 . Next, as shown in FIG. 1F, polysilicon 20, which is a dielectric material, is deposited so that the trench 18 is completely buried, and then the polysilicon 20 is deposited to the position of the silicon oxide film 14 formed first. Etch and make it flat. As a result, the trench 18 is surrounded by the p-type silicon semiconductor layer (first semiconductor layer) 11 and the buried layer 12.
, and n-type silicon epitaxial layer (second semiconductor layer)
13 is dielectrically isolated from the p-type silicon semiconductor layer 11, the buried layer 12, and the n-type silicon epitaxial layer 13 around the trench 18, that is, on the outside. Next, as shown in FIG. 1G, a circuit element (not shown) in which the silicon oxide film 14 is thickened by field oxidation is applied.
After that, an electrode pad 21 for wire bonding is formed on the silicon oxide film 14. This electrode pad 21 is formed to have a wider width (larger area) than a wiring conductor (not shown) for a circuit element. FIG. 2A shows the conventional semiconductor device shown in FIG. 3, and FIG. 2B shows an embodiment of the semiconductor device of the present invention manufactured by the method shown in FIG. Figure 1G
). In addition, FIG. 2C shows the inner side 10 of the electrode pad 21.
An embodiment of the semiconductor device of the present invention is shown in which a dielectric material for isolation (polysilicon 20) is formed at 0j1. 1 shows an embodiment of a semiconductor device of the invention. The electrode pads shown in these figures are all squares with 5008 sides. Table 1 below shows the measured values of the capacitance between the electrode pad and the back surface of the semiconductor substrate of the semiconductor device shown in FIG. 2A and FIG. 3 shows the reduction rate of capacity of each embodiment of the present invention in C and D. [Table 1] As shown in this Table 1, Fig. 2 B1C and D
Each of the embodiments of the present invention can reduce the capacitance between the electrode and the back surface of the semiconductor substrate by 30%, 11%, and 18%, respectively, compared to the conventional example shown in FIG. 2A. . Therefore, according to these embodiments, the electrode pad 2
1 and the back surface of the semiconductor substrate 10 can be reduced,
High frequency characteristics can be improved. Most preferably, the polysilicon 20 constituting the isolation dielectric is formed along the outer edge of the electrode pad 21.
In other words, this is the embodiment shown in FIG. 2B in which the lateral cross-sectional shape of the polysilicon 2o is made substantially the same as the outer edge of the electrode pad 21, and this embodiment can reduce the capacitance the most. Note that in the above embodiment, the first and second semiconductor layers 1
Although 1 and 13 are a p-type silicon semiconductor layer and an n-type silicon epitaxial layer, respectively, they may be made of a semiconductor other than silicon, such as germanium. Further, in the above embodiment, silicon oxide was used as the insulating film 14, but other insulating materials may be used, and the insulating material may have a multilayer structure. Further, in the above embodiment, polysilicon was used as the isolation dielectric 2o, but other dielectrics can also be used. Furthermore, in the above-described embodiment, the separating dielectric 2° separates not only the inner and outer first semiconductor layers 11 and the buried layer 12 but also the second semiconductor layer 13; It is sufficient to separate the semiconductor layer 11 and the buried layer 12. However, if the second semiconductor layer 13 is also separated as in the embodiments shown in FIGS. 1 and 2, the trench can be easily formed and the semiconductor device can be easily manufactured.
以上の説明から明らかなように、この発明によれば、埋
め込み層と第１半導体層との間のｐｎ接合容量の横方向
の広かりを限定てきるのて、電極パッドと半導体基板裏
面との間の容量を小さくてき、入力信号の高周波成分が
前記容量を介して他に与える影響を小さくてき、また、
入力信号の劣化を抑制できる。As is clear from the above description, according to the present invention, the width of the pn junction capacitance between the buried layer and the first semiconductor layer can be limited in the lateral direction. By reducing the capacitance between the capacitance and the capacitance, the influence of high frequency components of the input signal on others via the capacitance is reduced, and
Deterioration of input signals can be suppressed.
第１図は、この発明による半導体装置の一実施例を製造
する方法の各工程を示す断面図、第２図は、従来の半導
体装置の一例及びこの発明の各実施例の半導体装置の断
面図を示す図、第３図は、従来の半導体装置の一例を示
す断面図である。
１０：半導体基板
１１・第１半導体層（ｐ型シリコン半導体層）１２、埋
め込み層
１３：第２半導体層（ｎ型シリコンエピタキシャル層）
１４：絶縁膜
１８ニドレンチ
２０：誘電体（ポリシリコン）
２１：電極パッドFIG. 1 is a cross-sectional view showing each step of a method for manufacturing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view of an example of a conventional semiconductor device and a semiconductor device of each embodiment of the present invention. FIG. 3 is a sectional view showing an example of a conventional semiconductor device. 10: Semiconductor substrate 11, first semiconductor layer (p-type silicon semiconductor layer) 12, buried layer 13: second semiconductor layer (n-type silicon epitaxial layer) 14: insulating film 18 trench 20: dielectric (polysilicon) 21: electrode pad
Claims (2)
層を縦方向にこの順に有する半導体基板と、この半導体
基板の前記第２半導体層上に設けられた電極パッドとを
備えた半導体装置において、 前記電極パッドの配設領域付近の前記埋め込み層及び前
記第１半導体層と、その周囲の前記埋め込み層及び前記
第１半導体層とを分離するように、少なくとも前記埋め
込み層から前記第１半導体層へ縦方向に延びる誘電体を
具備することを特徴とする半導体装置。(1) A semiconductor comprising a semiconductor substrate having a first semiconductor layer, a buried layer, and a second semiconductor layer in this order in the vertical direction, and an electrode pad provided on the second semiconductor layer of this semiconductor substrate. In the device, at least the buried layer and the first semiconductor layer are separated from the buried layer and the first semiconductor layer in the vicinity of the region where the electrode pad is provided, and the buried layer and the first semiconductor layer around the buried layer and the first semiconductor layer. A semiconductor device comprising a dielectric extending vertically into a semiconductor layer.
ドの外縁と実質的に同一であることを特徴とする請求項
（１）記載の半導体装置。(2) The semiconductor device according to claim (1), wherein a cross-sectional shape of the dielectric in the lateral direction is substantially the same as an outer edge of the electrode pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216635A JPH0498841A (en) | 1990-08-17 | 1990-08-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216635A JPH0498841A (en) | 1990-08-17 | 1990-08-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0498841A true JPH0498841A (en) | 1992-03-31 |
Family
ID=16691528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2216635A Pending JPH0498841A (en) | 1990-08-17 | 1990-08-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0498841A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6778572B1 (en) | 1999-03-18 | 2004-08-17 | Fujitsu Quantum Devices Limited | Electrode structure, process for fabricating electrode structure and semiconductor light-emitting device |
-
1990
- 1990-08-17 JP JP2216635A patent/JPH0498841A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6778572B1 (en) | 1999-03-18 | 2004-08-17 | Fujitsu Quantum Devices Limited | Electrode structure, process for fabricating electrode structure and semiconductor light-emitting device |
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