JP2002009245A - Dielectrically isolated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease variation in the resistance of a resistance diffusion layer in a dielectrically isolated semiconductor device. SOLUTION: The entire side panel of opposite conductivity type resistance diffusion layer 107a provided on the surface of one conductivity type single crystal silicon layer 104 of an SOI substrate 101 are making direct contact with a dielectrically isolating region wherein an embedding insulating film 115 is filled up in a trench 113a reaching an embedding insulating layer 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dielectric isolation type semiconductor device provided on an SOI substrate, and more particularly to a dielectric isolation type semiconductor device including a resistance element formed of a resistance diffusion layer.

[0002]

2. Description of the Related Art In recent years, a power semiconductor device including a high breakdown voltage semiconductor element is formed using an SOI substrate. In the semiconductor device, horizontal isolation between elements is performed by trench isolation in which a trench is filled with an insulating film. This groove reaches a buried insulating layer constituting the SOI substrate. In other words, each element of the semiconductor device is separated from the dielectric in the vertical direction and the horizontal direction, and electrical interference between the elements is suppressed.

[0003] Regarding the structure of the resistive element in such a dielectric isolation type semiconductor device, FIG. 6 (a) which is a schematic plan view of the dielectric isolation type semiconductor device, and a schematic cross-sectional view taken along line AA in FIG. 6 (a). This will be described with reference to FIG.

An SOI substrate 401 is a silicon substrate 402
And a buried insulating layer 403 made of silicon oxide and a single conductivity type single crystal silicon layer 404 are stacked. On the surface of the single crystal silicon layer 404, a resistance diffusion layer 407 of the opposite conductivity type is provided. Including the resistance diffusion layer 407,
The surface of the single crystal silicon layer 404 is covered with an interlayer insulating film 411. The resistance diffusion layer 407 is surrounded by a dielectric isolation region in which the trench 413 is filled with the buried insulating film 415. The resistance diffusion layer 407 is separated from the dielectric isolation region. The formation of the groove 413 is performed after the formation of the resistance diffusion layer 413 and the like and the formation of the interlayer insulating film 411. The groove 413 is formed in the interlayer insulating film 411.
And penetrates the single crystal silicon layer 404 to reach the buried insulating layer 403. Contact holes 416 and 417 reaching the resistance diffusion layer 407 are provided in the interlayer insulating film 411, and the contact holes 41 are provided on the surface of the interlayer insulating film 411.
Metal wirings 418, 419 connected to the resistance diffusion layer 407 via 6, 417 are provided.

[0005]

However, when a resistance element having the above structure is employed in a dielectric isolation type semiconductor device, the resistance value of the resistance element tends to vary. This corresponds to variations in the lateral spread of the resistance diffusion layer due to heat treatment during and after the formation of the resistance element.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a resistance element having a structure with less variation in resistance value.

[0007]

According to a first aspect of the present invention, there is provided a dielectric isolation type semiconductor device in which a buried insulating layer and a single conductivity type single crystal silicon layer are laminated on a surface of a silicon substrate.
On the surface of this single-crystal silicon layer of the substrate, a resistance diffusion layer of the opposite conductivity type is provided, and the entire side surface of the resistance diffusion layer is
A buried insulating film is filled in a groove reaching the buried insulating layer from the surface of the single crystal silicon layer, and is directly in contact with a dielectric isolation region.

According to a second aspect of the present invention, there is provided a dielectric isolation type semiconductor device.
A resistance diffusion layer of a required conductivity type is provided on the surface of the single crystal silicon layer of the SOI substrate in which a buried insulating layer and a single conductivity type single crystal silicon layer are laminated on the surface of the silicon substrate. The entire side surface of the layer is in direct contact with a dielectric isolation region formed by filling a trench reaching the buried insulating layer from the surface of the single crystal silicon layer with a buried insulating film, and furthermore, a bottom surface of the resistance diffusion layer. Is directly in contact with the buried insulating film.

[0009] In a preferred first aspect of the second invention,
The resistance element region on the surface of the single crystal silicon layer of the SOI substrate in which the buried insulating layer and the one conductivity type single crystal silicon layer are laminated on the surface of the silicon substrate has an inverted trapezoidal or bathtub-shaped cross section. The surface of the single crystal silicon layer including the depression is covered with an interlayer insulating film. The depression is filled with a first buried insulating film via the interlayer insulating film, and the resistance is reduced. The element region is surrounded by a first trench that reaches the buried insulating layer through the first buried insulating film, the interlayer insulating film, and the single crystal silicon layer, and is provided on a surface of the single crystal silicon layer. The high-breakdown-voltage semiconductor element region thus surrounded is surrounded by the interlayer insulating film and the second trench penetrating the single-crystal silicon layer and reaching the buried insulating layer, and is surrounded by the first and second trenches. The second buried insulating film is filled to form first and second dielectric isolation regions. The entire surface of the side surface of the resistance diffusion layer provided in the resistance element region is covered with the first dielectric isolation region. The resistance diffusion layer is in direct contact with the region, and the entire bottom surface of the resistance diffusion layer is in direct contact with the buried insulating layer.

[0010] In a preferred second aspect of the second invention,
The resistance element region on the surface of the single crystal silicon layer of the SOI substrate in which the buried insulating layer and the one conductivity type single crystal silicon layer are laminated on the surface of the silicon substrate has an inverted trapezoidal or bathtub-shaped cross section. The surface of the single crystal silicon layer including the depression is covered with an interlayer insulating film, and the resistance element region penetrates the interlayer insulating film and the single crystal silicon layer to form the buried insulating layer. A high breakdown voltage semiconductor element region provided on the surface of the single crystal silicon layer and surrounded by the first groove reaching the first trench reaches the buried insulating layer through the interlayer insulating film and the single crystal silicon layer. The first trench and the first and second trenches are filled with a buried insulating film, and the first dielectric is formed by the first trench and the buried insulating film. An isolation region, a second dielectric isolation region composed of the second trench and the buried insulating film is formed, and the entire side surface of the resistance diffusion layer provided in the resistance element region is covered with the first dielectric. The present invention is characterized in that it directly contacts the isolation region, and that the entire bottom surface of the resistance diffusion layer directly contacts the buried insulating layer.

A third preferred aspect of the second invention is as follows.
In the single crystal silicon layer of the SOI substrate in which the first buried insulating layer and the one conductivity type single crystal silicon layer are laminated on the surface of the silicon substrate, directly below the resistance element region on the surface of the single crystal silicon layer Is provided with a second buried insulating layer, the surface of the single crystal silicon layer is covered with an interlayer insulating film, and the resistance element region penetrates the interlayer insulating film and the single crystal silicon layer to form the second The high-breakdown-voltage semiconductor element region provided on the surface of the single-crystal silicon layer and surrounded by the first groove reaching the buried insulating layer of the first through-hole extends through the interlayer insulating film and the single-crystal silicon layer. Surrounded by a second groove reaching the buried insulating layer of
The first and second trenches are respectively filled with a buried insulating film to form first and second dielectric isolation regions, and the entire side surface of the resistance diffusion layer provided in the resistance element region is formed as The first dielectric isolation region is directly contacted, and the entire bottom surface of the resistance diffusion layer is directly contacted with the second buried insulating layer.

[0012]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1A, which is a schematic plan view of a dielectric isolation type semiconductor device, and FIG. 1B, which is a schematic cross-sectional view taken along the line AA in FIG. The structure of the resistance element according to the first example of the first embodiment is as follows.

The SOI substrate 101 is a silicon substrate 102
Then, a buried insulating layer 103 made of, for example, silicon oxide having a thickness of about 1 μm, and a single-conductive single-crystal silicon layer 104 having a thickness of, for example, about 5 μm are sequentially laminated.
Since the SOI substrate 101 is formed by bonding, the entire main surface of the silicon substrate 102 is covered with the buried insulating layer 103. The surface of the single crystal silicon layer 104 has a junction depth Xj of about 2 μm, for example.
(And a lateral spread of, for example, about 1.4 μm (= 0.7 Xj)) of the reverse conductivity type.
And a high breakdown voltage semiconductor element (not shown). The high withstand voltage semiconductor element has a withstand voltage of 50V to 250V. The surface of the single-crystal silicon layer 104 including the resistance diffusion layer 107a and the like is covered with an interlayer insulating film 111 of, for example, about 1.5 μm.

The interlayer insulating film 111 and the single crystal silicon layer 10
4 to reach the buried insulating layer 103
a is filled with a buried insulating film 115 to form a dielectric isolation region. Unlike the conventional resistance diffusion layer (407), the entire side surface of the resistance diffusion layer 107a is in direct contact with the dielectric isolation region. The opening width at the upper end of the groove 113a is, for example, about 2 μm (similar to Xj of the resistance diffusion layer 107a).

The interlayer insulating film 111 includes a resistance diffusion layer 107
contact holes 116 reaching one end and the other end of
a, 117a. On the surface of the interlayer insulating film 111, metal wirings 118a and 119a connected to one end and the other end of the resistance diffusion layer 107a are provided via contact holes 116a and 117a, respectively.

An example of the main steps of the method of manufacturing the dielectric isolation type semiconductor device according to the first embodiment is as follows.

First, the silicon substrate 102 is thermally oxidized.
Buried insulating layer 103 is formed on the main surface of. A single conductivity type single crystal silicon substrate is attached to the surface of the buried insulating layer 103, and the single crystal silicon substrate is ground to form a single conductivity type single crystal silicon layer 104. On the surface of the single crystal silicon layer 104, a resistance diffusion layer 107a of a reverse conductivity type and a high-breakdown-voltage semiconductor element (not shown) are formed. On the surface of the single-crystal silicon layer 104, an interlayer insulating film 111 made of, for example, a silicon oxide-based insulating film is formed.

Thereafter, a groove 113a is formed. The groove 113a is formed by anisotropic etching of the interlayer insulating film 111 using the photoresist film as a mask and anisotropic etching of the single crystal silicon layer 104 (and the resistance diffusion layer 107a) using the interlayer insulating film 111 as a mask. It is formed by the following two-stage anisotropic etching. In this etching, if the opening width at the upper end of the groove 113a is set to about Xj of the resistance diffusion layer 107a, the groove 113a completely etches off the laterally expanded portion of the resistance diffusion layer 107a, The bottom surface of the diffusion layer 107a can directly cross the side surface of the groove 113a. The anisotropic etching of the single crystal silicon layer 104 (or the like) is performed by using an etching gas (for example, HBr + Cl
₂ ) are used. For example, a silicon oxide insulating film is formed on the entire surface by LPCVD. Etchback or CMP is performed on the silicon oxide-based insulating film to leave a buried insulating film 115 filling the groove 113a, thereby forming a dielectric isolation region.

The silicon oxide-based insulating film constituting the buried insulating film 115 may be a combination of a first silicon oxide-based insulating film formed by LPCVD and a second silicon oxide-based insulating film made of an SOG film. In this case, it is preferable to perform a heat treatment in an oxidizing atmosphere at about 500 ° C. to 700 ° C. before the etch back or the CMP. The SOG film used here is an SOG film containing hydrogenated silsesquioxane ((HSiO _3/2 ) _n ) as a main component.
G films are preferred. In the case of this SOG film, shrinkage due to heat treatment is extremely small.

If a manufacturing method of forming a dielectric isolation region including a groove before forming a resistance diffusion layer, a high breakdown voltage semiconductor element, or the like is employed, a silicon oxide film is formed on the side surface of the groove by thermal oxidation. Then, a silicon oxide-based insulating film can be formed, and a buried insulating film can be formed.

Subsequently, contact holes 116a and 117a reaching one end and the other end of the resistance diffusion layer 107a, respectively, are formed.
It is formed on the interlayer insulating film 111. Contact hole 116
a, 117a are connected to one end and the other end of the resistance diffusion layer 107a, respectively.
It is formed on the surface of the interlayer insulating film 111.

The resistance diffusion layer 107a according to the first embodiment.
Since the entire side surface is directly covered with the dielectric isolation region including the groove 113a, the resistance spreading layer 107a is removed (as a result, the lateral spread portion is removed). Variations in values are suppressed. Further, according to the first embodiment, it is easier to reduce the occupied area of the resistance diffusion layer than the resistance diffusion layer having the conventional structure.

Referring to FIG. 2A, which is a schematic plan view of the dielectric isolation type semiconductor device, and FIG. 2B, which is a schematic cross-sectional view taken along the line AA in FIG. The structure of the resistance element according to the second example of the first embodiment is as follows.

As in the first embodiment, the SOI substrate 1
01 denotes a buried insulating layer 103 made of silicon oxide and a single conductivity type single crystal silicon layer 10 on a silicon substrate 102.
4 are sequentially laminated.

Unlike the first embodiment, the surface of the single-crystal silicon layer 104 has a junction depth Xj of about 2 μm (for example, and a lateral direction of about 1.4 μm (= 0.7Xj)). Resistance diffusion layer 10 of the opposite conductivity type having
7b and a high breakdown voltage semiconductor element (not shown) and the like are provided. The resistance diffusion layer 107b has a meandering planar shape. The surface of the single crystal silicon layer 104 including the resistance diffusion layer 107b and the like is covered with an interlayer insulating film 111.

The interlayer insulating film 111 and the single crystal silicon layer 10
4 to reach the buried insulating layer 103
b is filled with a buried insulating film 115 to form a dielectric isolation region. The entire side surface of the resistance diffusion layer 107b is also in direct contact with the dielectric isolation region, as in the first embodiment. The opening width at the upper end of the groove 113b is
For example, 2 μm (similar to Xj of the resistance diffusion layer 107b)
It is about.

The interlayer insulating film 111 has a resistance diffusion layer 107
contact holes 116 that reach one end and the other end of b, respectively.
b, 117b are provided. On the surface of the interlayer insulating film 111, metal wirings 118b and 119b connected to one end and the other end of the resistance diffusion layer 107b are provided via contact holes 116b and 117b, respectively.

The second embodiment has the same advantages as the first embodiment. Furthermore, in the case of forming a resistance diffusion layer having a meandering planar shape in the conventional structure, it is difficult to reduce the gap between the air gaps in order to reduce the influence of the depletion layer extending from both sides in the parallel portion. In the second embodiment, the gap can be easily reduced.

A PN junction is formed between the reverse conductivity type resistance diffusion layer and the one conductivity type single crystal silicon layer according to the first embodiment of the present invention. The dielectric isolation type semiconductor device of the present invention is not limited to the first embodiment.

In the resistance diffusion layers according to the second and third embodiments of the present invention, the entire bottom surface is in direct contact with the buried insulating layer. Therefore, unlike the first embodiment, the conductivity type of the resistance diffusion layer is not limited to the opposite conductivity type, and the degree of freedom in design is improved. The second embodiment of the present invention is preferably applied to a dielectric isolation type semiconductor device including a relatively low withstand voltage semiconductor element of, for example, about 50 V to 75 V. In the second embodiment of the present invention, the 50 V
The present invention can be applied to a dielectric isolation type semiconductor device including a high-voltage semiconductor element in a wide range of about 250 V.

Referring to FIG. 3, which is a schematic sectional view of a dielectric isolation type semiconductor device, the first embodiment of the present invention will be described.
The outline of the dielectric isolation type semiconductor device according to the embodiment is as follows.

The SOI substrate 201 is a silicon substrate 202
Then, a buried insulating layer 203 made of, for example, silicon oxide having a thickness of, for example, about 1 μm, and a single-conductive single-crystal silicon layer 204 having a thickness of, for example, about 2 μm are sequentially laminated.
Since the SOI substrate 201 is also formed by bonding, the entire main surface of the silicon substrate 202 is covered with the buried insulating layer 203. A recess 205 having a depth of, for example, about 1 μm is provided in the resistance element region on the surface of the single crystal silicon layer 204. This depression 205
Is formed by, for example, anisotropic wet etching of the single crystal silicon layer 204 and has an inverted trapezoidal cross section (or a depression having a bathtub-shaped cross section formed by isotropic etching). ).

The surface of the single-crystal silicon layer 204 (the depression 2
In the resistive element region (consisting of the bottom of FIG. 05), a reverse conductivity type having, for example, a junction depth Xj of at least about 1 μm (and a lateral extension of at least about 0.7 μm (= 0.7Xj), for example) is provided. Is provided. A high breakdown voltage semiconductor element (not shown) is provided in the high breakdown voltage semiconductor element region on the surface of the single crystal silicon layer 204. The high breakdown voltage semiconductor element has a breakdown voltage of about 50V to 75V.

The surface of the single crystal silicon layer 204, including the resistance diffusion layer 207 and the depression 205, is covered with an interlayer insulating film 211 of, for example, about 1 μm. Hollow 205
A first buried insulating film 212 made of a silicon oxide-based insulating film is provided on the surface of the interlayer insulating film 211 in this portion. The upper surface of the buried insulating film 212 and the upper surface of the interlayer insulating film 211 except for the recess 205 substantially coincide with each other. The buried insulating film 212 is preferably made of an SOG film containing hydrogenated silsesquioxane as a main component.

In the resistive element region, the first buried insulating film 212, the interlayer insulating film 211, and the first crystal silicon layer 204 forming the bottom of the depression 205 penetrate and reach the buried insulating layer 203. Groove 213a is provided. The opening width at the upper end of the groove 213a is at least about 1 μm, for example. In the high breakdown voltage semiconductor element region, the interlayer insulating film 211 and the single crystal silicon layer 204 are penetrated,
A second groove 214a reaching the buried insulating layer 203 is provided. The opening width at the upper end of the groove 214a is the same as the opening width at the upper end of the groove 213a, for example.

The grooves 213a and 214a are respectively filled with a second buried insulating film 215a. Groove 21
3a and the buried insulating film 215a form a first dielectric isolation region, and the trench 214a and the buried insulating film 2
15a constitutes a second dielectric isolation region. As in the first embodiment, the entire side surface of the resistance diffusion layer 207 is in direct contact with the first dielectric isolation region.

As the silicon oxide-based insulating film constituting the buried insulating film 215a, as in the first example of the first embodiment, only the silicon oxide-based insulating film by LPCVD or oxidation by LPCVD is used. It is formed of a laminated film of a silicon-based insulating film made of a silicon-based insulating film and an SOG film. When this laminated film is formed, S
As the OG film, an SOG film containing hydrogenated silsesquioxane as a main component is preferable.

A buried insulating film 212 is formed in the resistance element region.
And the resistance diffusion layer 207 through the interlayer insulating film 211.
Contact holes 216a reaching one end and the other end of
217a is provided. Contact holes 216a and 217 are formed on the surface of the buried insulating film 212 in the resistance element region.
Metal wirings 218a and 219a connected to one end and the other end of the resistance diffusion layer 207 via a are provided.

The resistance diffusion layer 207 according to the first example of the second embodiment has the same effects as those of the first and second examples of the first embodiment. . further,
Resistance diffusion layer 20 of the first embodiment of the second embodiment
7, the parasitic capacitance is reduced (because a PN junction is not formed) as compared with the resistance diffusion layers of the first and second examples of the first embodiment.

The conductivity type of the resistance diffusion layer in the first example of the second embodiment is not limited to the opposite conductivity type. Further, like the second example of the first embodiment, the first example of the second embodiment is applicable to a resistance diffusion layer having a meandering planar shape. Can be.

Referring to FIG. 4, which is a schematic sectional view of a dielectric isolation type semiconductor device, a second embodiment of the present invention will be described.
The outline of the dielectric isolation type semiconductor device according to the embodiment is as follows.

As in the first embodiment of the second embodiment, the SOI substrate 201 is
For example, a buried insulating layer 203 made of silicon oxide having a thickness of about 1 μm and a single conductivity type single crystal silicon layer 204 having a thickness of about 2 μm are sequentially laminated. Since the SOI substrate 201 is also formed by bonding, the entire main surface of the silicon substrate 202 is covered with the buried insulating layer 203. Single crystal silicon layer 20
A recess 205 having a depth of, for example, about 1 μm is provided in the resistance element region on the surface of No. 4. The depression 205 has an inverted trapezoidal shape or a bathtub-shaped cross section.

As in the first embodiment of the second embodiment, the surface of the single crystal silicon
In the resistive element region (consisting of the bottom portion), for example, a junction depth Xj of at least about 1 μm (and a lateral extension of at least about 0.7 μm (= 0.7Xj), for example)
Is provided with a resistance diffusion layer 208 of one conductivity type. A high breakdown voltage semiconductor element (not shown) is provided in the high breakdown voltage semiconductor element region on the surface of the single crystal silicon layer 204. The high breakdown voltage semiconductor element has a breakdown voltage of about 50V to 75V. The surface of the single-crystal silicon layer 204, including the resistance diffusion layer 208, the depression 205, and the like, is covered with, for example, an interlayer insulating film 211 of about 1 μm.

Unlike the first embodiment of the second embodiment, the resistance element region penetrates the interlayer insulating film 211 and the single-crystal silicon layer 204 forming the bottom of the recess 205. , First groove 213b reaching buried insulating layer 203
Is provided. The opening width at the upper end of the groove 213b is at least about 1 μm, for example. As in the first example of the second embodiment, in the high-breakdown-voltage semiconductor element region, the second through the interlayer insulating film 211 and the single-crystal silicon layer 204 to reach the buried insulating layer 203. 2 grooves 21
4b is provided. The opening width at the upper end of the groove 214b is, for example, the same as the opening width at the upper end of the groove 213b.
The photolithography for forming the groove 213b and the groove 214b is preferably separate.

Unlike the first embodiment of the second embodiment, the trench 213b, the trench 214b, and the depression 205 are filled with a buried insulating film 215b. The trench 213b and the buried insulating film 215b constitute a first dielectric isolation region, and the trench 214b and the buried insulating film 215b constitute a second dielectric isolation region. The entire surface of the side surface of the resistance diffusion layer 208 is
As in the first embodiment, the first dielectric isolation region is in direct contact with the first dielectric isolation region.

An example of a method for forming the buried insulating film 215b is as follows. First, a silicon oxide-based insulating film is formed by LPCVD, and then, for example, an SOG film mainly containing silsesquioxane hydride is formed. After heat treatment in an oxidizing atmosphere at about 500 ° C. to 700 ° C., etch back or CMP is performed,
The buried insulating film 215b is left.

A buried insulating film 215 is formed in the resistance element region.
b and the interlayer insulating film 211,
Contact holes 216 reaching one end and the other end of
b, 217b. A contact hole 216b, a contact hole 216b,
217b, one end of the resistance diffusion layer 208,
Metal wirings 218b and 219b connected to the other end are provided.

The resistance diffusion layer 208 according to the second embodiment of the second embodiment is different from the first embodiment of the second embodiment.
This has the effect of the embodiment of FIG.

The conductivity type of the resistance diffusion layer of the second embodiment of the second embodiment is not limited to one conductivity type. Further, like the second example of the first embodiment, the second example of the second embodiment is also applied to a resistance diffusion layer having a meandering planar shape. Can be.

Referring to FIG. 5, which is a schematic sectional view of a dielectric isolation type semiconductor device, an outline of a dielectric isolation type semiconductor device according to an example of the third embodiment of the present invention is as follows. ing.

The SOI substrate 301 is a silicon substrate 302
Then, a first buried insulating layer 303 made of, for example, silicon oxide having a thickness of, for example, about 1 μm, and a single-conductive single-crystal silicon layer 504 having a thickness, for example, of about 5 μm, are sequentially laminated. Since this SOI substrate 301 is also formed by bonding, the entire main surface of the silicon substrate 302 is covered with the buried insulating layer 303. In the single crystal silicon layer 304 immediately below the resistance element region, for example, 1 μm
A second buried insulating layer 306 having a thickness of about 30 nm is provided. The second buried insulating layer 306 is formed by ion implantation of high dose oxygen and activation heat treatment. Single-crystal silicon layer 30 on buried insulating layer 306
The thickness of 4 is, for example, about 2 μm.

The resistance element region on the surface of the single crystal silicon layer 304 has a junction depth X of at least about 2 μm, for example.
j (and, for example, at least 1.4 μm (= 0.7Xj)
And a resistance diffusion layer 307 of the opposite conductivity type having a degree of lateral spread. In the high-breakdown-voltage semiconductor element region on the surface of the single-crystal silicon layer 304, a high-breakdown-voltage semiconductor element (not shown) is provided. The high breakdown voltage semiconductor element is 50
It has a withstand voltage of about V to 250V. The surface of the single crystal silicon layer 304 is covered with an interlayer insulating film 311 made of, for example, a silicon oxide insulating film having a thickness of about 1.5 μm.

In the resistance element region, an interlayer insulating film 311
A first groove 313 penetrating through the single crystal silicon layer 204 and reaching the second buried insulating layer 306 is provided. The opening width at the upper end of the groove 313 is at least, for example, 2
It is about μm. In the high breakdown voltage semiconductor element region, a second groove 314 that penetrates through the interlayer insulating film 311 and the single crystal silicon layer 304 and reaches the first buried insulating layer 303 is provided. The opening width at the upper end of the groove 314 is the same as the opening width at the upper end of the groove 313, for example.

The grooves 313 and 314 are filled with a buried insulating film 315, respectively. The groove 313 and the buried insulating film 315 form a first dielectric isolation region, and the groove 314 and the buried insulating film 315 form a second dielectric isolation region. The entire side surface of the resistance diffusion layer 307 is in direct contact with the first dielectric isolation region as in the first and second embodiments. As the silicon oxide-based insulating film constituting the buried insulating film 315,
As in the first example of the first embodiment, L
Only silicon oxide insulating film by PCVD, or
It is composed of a laminated film of a silicon oxide-based insulating film formed by LPCVD and a silicon oxide-based insulating film made of an SOG film. When this laminated film is formed, the SOG film is preferably an SOG film containing hydrogenated silsesquioxane as a main component.

In the resistance element region, there are provided contact holes 316 and 317 penetrating through the interlayer insulating film 311 and reaching one end and the other end of the resistance diffusion layer 307, respectively. On the surface of the interlayer insulating film 311 in the resistance element region, metal wirings 318 and 319 connected to one end and the other end of the resistance diffusion layer 307 are provided via contact holes 316 and 317, respectively.

The resistance diffusion layer 307 according to the present example of the third embodiment has the same effects as those of the first and second embodiments. Further, the resistance diffusion layer 307 of the present example of the third embodiment is also different from the resistance diffusion layers of the first and second examples of the first embodiment by (P
Parasitic capacitance is reduced (because no N-junction is formed).

Note that the conductivity type of the resistance diffusion layer of the present example of the third embodiment is not limited to the reverse conductivity type. Further, similarly to the second example of the first embodiment, the first example of the third embodiment can be applied to a resistance diffusion layer having a meandering planar shape. .

[0059]

As described above, at least the entire side surface of the resistance diffusion layer of the dielectric isolation type semiconductor device of the present invention is in direct contact with the dielectric isolation region in which the trench is filled with the insulating film. ing. Therefore, by employing the present invention, it is easy to reduce the variation in the resistance value of the resistance diffusion layer.

[Brief description of the drawings]

FIG. 1 is a schematic plan view and a schematic sectional view of a first example of the first embodiment of the present invention.

FIG. 2 is a schematic plan view and a schematic sectional view of a second example of the first embodiment.

FIG. 3 is a schematic cross-sectional view of a first example of the second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a second example of the second embodiment.

FIG. 5 is a schematic cross-sectional view of one example of the third embodiment of the present invention.

FIG. 6 is a schematic plan view and a schematic cross-sectional view of a conventional dielectric isolation type semiconductor device.

[Explanation of symbols]

101, 201, 301, 401 SOI substrate 102, 202, 302, 402 Silicon substrate 103, 203, 303, 306, 403 Buried insulating layer 104, 204, 304, 404 Single crystal silicon layer 107a, 107b, 207, 208, 307 , 407
Resistance diffusion layers 111, 211, 311, 411 Interlayer insulating films 113a, 113b, 213a, 213b, 214a,
214b, 313, 314, 413 Grooves 115, 212, 215a, 215b, 315, 415
Embedded insulating films 116a, 116b, 117a, 117b, 216a,
216b, 217a, 217b, 316, 317, 41
6,417 contact holes 118a, 118b, 119a, 119b, 218a,
218b, 219a, 219b, 318, 319, 41
8,419 metal wiring 205 hollow

Claims (10)

[Claims] 1. An SOI substrate in which a buried insulating layer and a one-conductivity-type single-crystal silicon layer are laminated on the surface of a silicon substrate, a reverse-conductivity-type resistance diffusion layer is provided on the surface of the single-crystal silicon layer. The entire surface of the side surface of the resistance diffusion layer is in direct contact with a dielectric isolation region formed by filling a trench reaching the buried insulating layer from the surface of the single crystal silicon layer with a buried insulating film. A dielectric isolation type semiconductor device characterized by the above-mentioned. 2. The dielectric isolation type semiconductor device according to claim 1, wherein said resistance diffusion layer has a meandering planar shape. 3. An SOI substrate in which a buried insulating layer and one conductivity type single crystal silicon layer are laminated on the surface of a silicon substrate, a required conductivity type resistance diffusion layer is provided on the surface of the single crystal silicon layer. Wherein the entire surface of the side surface of the resistance diffusion layer is directly in contact with a dielectric isolation region formed by filling a trench reaching the buried insulating layer from the surface of the single crystal silicon layer with a buried insulating film; A dielectric isolation type semiconductor device, wherein the entire bottom surface of the resistance diffusion layer is in direct contact with the buried insulating film. 4. The dielectric isolation type semiconductor device according to claim 3, wherein said resistance diffusion layer has a meandering planar shape. 5. An SOI substrate in which a buried insulating layer and a single conductivity type single crystal silicon layer are laminated on a surface of a silicon substrate, an inverted trapezoidal shape or a bathtub is formed in a resistance element region on the surface of the single crystal silicon layer. A recess having a cross section of a shape is provided. The surface of the single crystal silicon layer including the recess is covered with an interlayer insulating film, and the recess is formed by a first buried insulating film via the interlayer insulating film. The resistive element region is surrounded by a first groove that reaches the buried insulating layer through the first buried insulating film, the interlayer insulating film, and the single-crystal silicon layer; The high-breakdown-voltage semiconductor element region provided on the surface of the layer is surrounded by a second groove that penetrates the interlayer insulating film and the single-crystal silicon layer and reaches the buried insulating layer, and groove Are respectively filled with a second buried insulating film to form first and second dielectric isolation regions. The entire surface of the side surface of the resistance diffusion layer provided in the resistance element region is the first dielectric material. A dielectric isolation type semiconductor device, wherein said isolation region is in direct contact with the entire surface of the bottom surface of said resistance diffusion layer and is directly in contact with said buried insulating layer. 6. The dielectric isolation type semiconductor device according to claim 5, wherein said resistance diffusion layer has a meandering planar shape. 7. An inverted trapezoidal shape or a bathtub is formed in a resistance element region on a surface of a single crystal silicon layer of an SOI substrate in which a buried insulating layer and a single conductivity type single crystal silicon layer are stacked on the surface of the silicon substrate. A depression having a cross section of a shape is provided, a surface of the single crystal silicon layer including the depression is covered with an interlayer insulating film, and the resistance element region penetrates the interlayer insulating film and the single crystal silicon layer. First reaching the buried insulating layer
The high-breakdown-voltage semiconductor element region provided on the surface of the single-crystal silicon layer and surrounded by the groove is formed as a second groove reaching the buried insulating layer through the interlayer insulating film and the single-crystal silicon layer. The recess and the first and second trenches are filled with a buried insulating film, respectively, to form a first dielectric isolation region including the first trench and the buried insulating film; A second dielectric isolation region including the second groove and the buried insulating film is formed, and the entire side surface of the resistance diffusion layer provided in the resistance element region is directly in contact with the first dielectric isolation region. A dielectric isolation type semiconductor device, wherein the entire surface of the bottom surface of the resistance diffusion layer is in direct contact with the buried insulating layer. 8. The dielectric isolation type semiconductor device according to claim 7, wherein said resistance diffusion layer has a meandering planar shape. 9. An S layer comprising a first buried insulating layer and a single conductivity type single crystal silicon layer laminated on a surface of a silicon substrate.
A second buried insulating layer is provided in the single crystal silicon layer immediately below the resistance element region on the surface of the single crystal silicon layer of the OI substrate, and the surface of the single crystal silicon layer is covered with an interlayer insulating film. The resistance element region is surrounded by a first groove that penetrates through the interlayer insulating film and the single crystal silicon layer and reaches the second buried insulating layer, and is provided on a surface of the single crystal silicon layer. The high-breakdown-voltage semiconductor element region is surrounded by a second groove penetrating the interlayer insulating film and the single-crystal silicon layer and reaching the first buried insulating layer, and is buried in the first and second grooves, respectively. An insulating film is filled to form first and second dielectric isolation regions, and the entire side surface of the resistance diffusion layer provided in the resistance element region is in direct contact with the first dielectric isolation region. And the resistance expansion The entire bottom surface of the layer, the dielectric isolation semiconductor device characterized by direct contact with the second buried insulating layer. 10. The dielectric isolation type semiconductor device according to claim 9, wherein said resistance diffusion layer has a meandering planar shape.