JPH0497531A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0497531A JPH0497531A JP21555290A JP21555290A JPH0497531A JP H0497531 A JPH0497531 A JP H0497531A JP 21555290 A JP21555290 A JP 21555290A JP 21555290 A JP21555290 A JP 21555290A JP H0497531 A JPH0497531 A JP H0497531A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- aluminum
- thickness
- conductor film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004020 conductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000002844 melting Methods 0.000 claims abstract description 9
- 230000008018 melting Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 29
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 abstract description 10
- 239000010937 tungsten Substances 0.000 abstract description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 6
- 238000000576 coating method Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 239000012535 impurity Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 210000003128 head Anatomy 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に配線の形成
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming wiring.
従来の半導体装置における配線は、アルミニウム膜をス
パッタリング法を用いて形成した後選択的にエツチング
することにより得ていた。さらに、アルミニウム配線の
耐湿性を強化するためにパッシベーション膜として窒化
シリコン膜等の水分の透過率の小さい材料で被覆する構
造にしていた。Wiring in conventional semiconductor devices has been obtained by forming an aluminum film using a sputtering method and then selectively etching it. Furthermore, in order to strengthen the moisture resistance of the aluminum wiring, the aluminum wiring is coated with a material with low moisture permeability, such as a silicon nitride film, as a passivation film.
上述した従来の配線の形成方法では、高集積化を図るた
めに隣接した２本のアルミニウム配線の間隔を小さくし
ていくと、パッシベーション膜の窒化シリコン膜が局部
的に薄くなる現象が起こる。これは、隣接したアルミニ
ウム配線間に形成される凹部の縦／横比、すなわち（ア
ルミニウム配線の厚さ）／（アルミニウム配線の間隔）
比が大きくなると、段部被覆率、すなわち（段部におけ
る最小の被覆膜厚）／（平坦部における被覆膜厚）が小
さくなるという性質をプラズマ分解ＣＶＤ法で形成する
窒化シリコン膜がもっているためである。この結果、平
坦部で一様の膜厚の窒化シリコン膜を形成しても耐湿性
が低下してしまうという欠点がある。In the conventional wiring formation method described above, when the distance between two adjacent aluminum wirings is reduced in order to achieve high integration, a phenomenon occurs in which the silicon nitride film of the passivation film becomes locally thin. This is the aspect/width ratio of the recess formed between adjacent aluminum wires, that is, (thickness of aluminum wires)/(distance between aluminum wires)
The silicon nitride film formed by plasma decomposition CVD has the property that as the ratio increases, the step coverage ratio (minimum coating thickness at the step)/(coating thickness at the flat area) decreases. This is because there is. As a result, even if a silicon nitride film with a uniform thickness is formed on a flat portion, the moisture resistance is reduced.
この様子を第２図（ａ）及び（ｂ）に示す。This situation is shown in FIGS. 2(a) and 2(b).
眉間絶縁膜２１５上に厚さ１．０μｍ、幅１．０μｍの
アルミニウム間隔２１６−１ａ。An aluminum interval 216-1a having a thickness of 1.0 μm and a width of 1.0 μm is formed on the glabellar insulating film 215.
２１６−２ａ、２１６−１ｂ、２１６−２ｂを形成した
後、厚さ０．５μｍの窒化シリコン膜２１４ａ及び２１
４ｂをそれぞれ形成したものである。After forming 216-2a, 216-1b, and 216-2b, silicon nitride films 214a and 21 with a thickness of 0.5 μm are formed.
4b, respectively.
第２図（ａ）ではアルミニウム配線２１６−１ａ、２１
６−２ａの間隔は１．０μｍ、第２図（ｂ）ではアルミ
ニウム配線２１６−１ｂ。In FIG. 2(a), aluminum wiring 216-1a, 21
The interval between 6-2a is 1.0 μm, and in FIG. 2(b), aluminum wiring 216-1b.
２１６−２ｂの間隔は０．８μｍとなっている。The spacing between 216-2b is 0.8 μm.
平坦部では同一の厚さの窒化シリコン膜を形成したにも
かかわらず、第２図（ａ）では段部における最小の被覆
膜厚は０．２μｍあるのに対し、第２図（ｂ）では０．
１μｍしかなくなってしまう。Although the silicon nitride film was formed with the same thickness on the flat part, the minimum coating thickness on the step part in Fig. 2(a) was 0.2 μm, whereas in Fig. 2(b) Then 0.
It becomes only 1 μm.
このように、プラズマ分解ＣＶＤ法で形成する窒化シリ
コン膜は凹部の縦／横比が大きくなると段部被覆率が急
激に低下してしまうという性質がある。As described above, the silicon nitride film formed by the plasma decomposition CVD method has a property that when the aspect ratio of the recessed portion increases, the coverage of the step portion decreases rapidly.
この対策として段部における最小の被覆膜厚が一定値以
上になるような条件で成膜すると、アルミニウム配線上
の平坦部には厚い窒化シリコン膜が形成されることにな
り、この場合はアルミニウム配線が窒化シリコン膜から
受ける応力によりストレスマイグレーションが起こりや
すくなる。これは、応力によりアルミニウム原子が移動
して空隙（ボイド）が発生する現象である。As a countermeasure for this, if the film is formed under conditions such that the minimum coating film thickness at the step part is a certain value or more, a thick silicon nitride film will be formed on the flat part on the aluminum wiring. Stress migration is likely to occur due to the stress that the wiring receives from the silicon nitride film. This is a phenomenon in which aluminum atoms move due to stress and voids are generated.
また、第二の対策としてアルミニウム間隔の縦横比を小
さくするためにアルミニウム膜厚を小さくすると、配線
の電気抵抗が増大し高速で回路を動作させることが困難
になる。Furthermore, as a second measure, if the aluminum film thickness is reduced in order to reduce the aspect ratio of the aluminum interval, the electrical resistance of the wiring increases, making it difficult to operate the circuit at high speed.
このように、従来の配線形成方法では、耐湿性、ストレ
スマイグレーション、配線抵抗等の要因を同時に満足さ
せつつ高集積化を実現することが困難であった。As described above, with conventional wiring forming methods, it has been difficult to achieve high integration while simultaneously satisfying factors such as moisture resistance, stress migration, and wiring resistance.
本発明の半導体装置の製造方法は、基板上に第１の導体
膜、第２の導体膜及び前記第２の導体膜より融点の高い
第３の導体膜を順次積層して多層膜を形成したのち選択
的に除去して前記第３の導体膜の幅が第２の導体膜の幅
より小さな多層膜配線を形成し、熱処理により前記第２
の導体膜の少なくとも一部を溶融する工程を有するとい
うものである。In the method for manufacturing a semiconductor device of the present invention, a first conductor film, a second conductor film, and a third conductor film having a higher melting point than the second conductor film are sequentially laminated on a substrate to form a multilayer film. Thereafter, the width of the third conductor film is smaller than that of the second conductor film by selectively removing the film, and the second conductor film is removed by heat treatment.
The method includes a step of melting at least a portion of the conductive film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の第１の実施例の説明に
使用する半導体チップの縦断面図である。FIGS. 1(a) to 1(d) are longitudinal sectional views of a semiconductor chip used to explain a first embodiment of the present invention.
抵抗率１０Ωｃｍのｐ型シリコン基板１０１の主表面に
選択的に厚さ０．６μｍのフィールド酸化膜１０２を形
成して活性領域を区画する。次に、活性領域上に厚さ２
０ｎｍのゲート酸化膜１０３を形成する。次に、ｎ型不
純物であるリンをドーピングした厚さ０．３μｍの多結
晶シリコン膜を形成した後選択的に除去してゲート長１
、Ｏｔｔｍのゲート電１ｉ１０４−１，１０４−２を形
成する。A field oxide film 102 having a thickness of 0.6 μm is selectively formed on the main surface of a p-type silicon substrate 101 having a resistivity of 10 Ωcm to define an active region. Next, place a thickness of 2 on the active area.
A gate oxide film 103 with a thickness of 0 nm is formed. Next, a polycrystalline silicon film doped with phosphorus, an n-type impurity, with a thickness of 0.3 μm is formed and then selectively removed to form a gate with a gate length of 1 μm.
, Ottm gate electrodes 1i104-1, 104-2 are formed.
次に、ｎ型不純物であるヒ素の１価イオンを打ち込んだ
後活性化処理を施して、深さ０．２μｍのｎ型不純物頭
域１０５−１，１０５−２を選択的に形成しＭＯＳ）ラ
ンジスタのソース／ドレイン領域を形成する。次に、厚
さ０．５μｍのＢＰＳＧＩｌ！を形成した後熱処理を施
してリフローさせ第１の眉間絶縁膜１０６を形成する。Next, monovalent ions of arsenic, which are n-type impurities, are implanted and then activated, to selectively form n-type impurity head regions 105-1 and 105-2 with a depth of 0.2 μm (MOS). Form source/drain regions of transistors. Next, BPSGIl! with a thickness of 0.5 μm! After forming, heat treatment is performed and reflow is performed to form the first glabella insulating film 106.
次に、厚さ０．３μｍのタングステンシリサイド膜を形
成した後選択的に除去して第の配線１０７を形成する。Next, a tungsten silicide film having a thickness of 0.3 μm is formed and then selectively removed to form a first wiring 107.
次に、厚さ０．５μｍのＢＰＳＧ膜を形成した後熱処理
を施してリフローさせ第２の眉間絶縁ＭＩＯ８を形成す
る。Next, a BPSG film with a thickness of 0.5 μm is formed, and then heat treated and reflowed to form a second glabellar insulation MIO8.
次にコンタクト開口部１０９−１ １０９−２．１０９
−３を形成する。Next, contact opening 109-1 109-2.109
-3 is formed.
次に、以上の工程を経たものを基板としてその上に厚さ
０．１μｍの窒化チタン膜（第１の導体！＞１１０、厚
さ１．Ｏｔｔｍのアルミニウム膜（第２の導体膜＞１１
１、厚さ０．１μｍのタングステン膜（第３の導体り１
１２を順次形成した後選択的に除去して第２の配線（多
層膜配線）１１３等を形成する。Next, a 0.1 μm thick titanium nitride film (first conductor!>110) and a 1.Ottm thick aluminum film (second conductor film>11
1. Tungsten film with a thickness of 0.1 μm (third conductor layer 1
12 is sequentially formed and then selectively removed to form a second wiring (multilayer film wiring) 113 and the like.
このとき第１図（ｂ）に示すようにタングステン配線の
幅は下層のアルミニウム配線及び窒化チタン配線の幅よ
りも０．４μｍ小さく形成する。At this time, as shown in FIG. 1(b), the width of the tungsten wiring is formed to be 0.4 μm smaller than the width of the lower layer aluminum wiring and titanium nitride wiring.
次に、第１図（ｃ）に示すように９素雰囲気中でハロゲ
ンランプによる６００℃、１０秒の熱処理を施しアルミ
ニウム配線を選択的に溶融し、角が丸くなったアルミニ
ウム配線１１１ａを形成する。Next, as shown in FIG. 1(c), heat treatment is performed at 600° C. for 10 seconds using a halogen lamp in a 9-element atmosphere to selectively melt the aluminum wiring, forming an aluminum wiring 111a with rounded corners. .
このとき、窒化チタン膜はコンタクト開口部におけるア
ルミニウム膜とシリコン基板とが反応して合金化するの
を防ぐバリア膜として働く。また、タングステン膜は、
アルミニウム膜より融点が高く、溶融したアルミニウム
ｌ康４配線が表面張力により過度に変形するのを防いで
いる。At this time, the titanium nitride film acts as a barrier film that prevents the aluminum film and silicon substrate in the contact opening from reacting and forming an alloy. In addition, the tungsten film is
It has a higher melting point than aluminum film, and prevents molten aluminum wiring from being excessively deformed due to surface tension.
次に、第１図（ａ）、（ｂ）に示すように、厚さ０．５
μｍの窒化シリコン膜１１４を形成する。Next, as shown in FIGS. 1(a) and (b), a thickness of 0.5
A silicon nitride film 114 with a thickness of μm is formed.
このとき、アルミニウム配線間の距離が０．８μｍであ
っても段部における最小の窒化シリコン膜厚は０．２μ
ｍ以上とすることが可能であり、従来の配線構造で得ら
れる量の約２倍にすることができる。これにより、アル
ミニウム配線間の距離を小さくした場合にも耐湿性を劣
化させないような窒化シリコン膜によるパッシベーショ
ンが可能である。また、過度に厚い窒化シリコン膜を用
いる必要もないため、ストレスマイグレーションも発生
しにくいという利点を有する。At this time, even if the distance between aluminum wires is 0.8 μm, the minimum silicon nitride film thickness at the stepped portion is 0.2 μm.
m or more, and can be approximately twice the amount obtained with conventional wiring structures. This makes it possible to perform passivation using a silicon nitride film that does not deteriorate moisture resistance even when the distance between aluminum wirings is reduced. Furthermore, since there is no need to use an excessively thick silicon nitride film, there is an advantage that stress migration is less likely to occur.
第３図（ａ）〜（ｃ）は本発明の第２の実施例の工程順
の縦断面図である。FIGS. 3(a) to 3(c) are longitudinal cross-sectional views of the second embodiment of the present invention in the order of steps.
第３図（ａ）に示すように、Ｐ型シリコン基板の表面に
選択的に形成されたｎ型不純物領域３１６上に形成した
厚さ−１，０μｍの眉間絶縁膜３１５にコンタクト開口
３１７を形成した基板を準備する。As shown in FIG. 3(a), a contact opening 317 is formed in a glabella insulating film 315 with a thickness of -1.0 μm formed on an n-type impurity region 316 selectively formed on the surface of a P-type silicon substrate. Prepare the substrate.
次に、厚さ０１１μｍの窒化チタン膜３１０４、厚さ１
．０μｍのアルミニウム膜３１１、厚さ０．１μｍタン
グステン膜３１２を順次積層して形成するが、タングス
テン膜は段部における被覆率の小さい条件で形成するこ
とにより、コンタクト開口の内側には入りこまないよう
にする。例えば、ｐ型シリコン基板の主表面に対して、
入射角が少なくとも４５°となる条件でスパッタリング
法によりタングステン膜を形成するとコンタクト開口の
内側に入りこまず表面にのみ成膜することが可能である
。Next, a titanium nitride film 3104 with a thickness of 011 μm and a thickness of 1
．． An aluminum film 311 with a thickness of 0 μm and a tungsten film 312 with a thickness of 0.1 μm are sequentially laminated, but the tungsten film is formed with a low coverage at the step so that it does not enter the inside of the contact opening. Make it. For example, for the main surface of a p-type silicon substrate,
If a tungsten film is formed by sputtering under the condition that the incident angle is at least 45°, it is possible to form the film only on the surface without entering the inside of the contact opening.
次に、第３図（ｂ）に示すように、窒化雰囲気中でハロ
ゲンランプによる６００℃、１０秒の熱処理を施しアル
ミニウム膜を選択的に溶融する。Next, as shown in FIG. 3(b), heat treatment is performed using a halogen lamp at 600° C. for 10 seconds in a nitriding atmosphere to selectively melt the aluminum film.
このとき、タングステン膜の付着していないコンタクト
開口部のアルミニウム膜だけが選択的にリフローしてコ
ンタクト開口部の内部にボイド３１８を残すとともにコ
ンタクト開口部をふさぐ。At this time, only the aluminum film in the contact opening to which the tungsten film is not attached is selectively reflowed, leaving a void 318 inside the contact opening and blocking the contact opening.
この後に第１の実施例で述べたのと同様にパターニング
を行ない、再びハロゲンランプによる熱処理を行ない、
第３図（ｃ）に示すように、アルミニウム膜の角が丸く
なった配線構造を得る。After this, patterning is performed in the same manner as described in the first example, and heat treatment is performed again using a halogen lamp.
As shown in FIG. 3(c), a wiring structure in which the corners of the aluminum film are rounded is obtained.
次に厚さ０．５μｍの窒化シリコンＭ３１を形成するが
、急しゅんな段差が存在しないので、良好な被覆性を有
する構造が得られる。Next, silicon nitride M31 with a thickness of 0.5 μm is formed, but since there are no sharp steps, a structure with good coverage can be obtained.
この実施例は、深さ７幅の比較的大きなコンタクト開口
部に配線の形成するのに有効な手段を与える。This embodiment provides an effective means for forming interconnects in relatively large contact openings that are 7 deep and wide.
以上説明したように、本発明は導体膜の配線を別の種類
の導体膜で上下からはさんで形成し、中央部の導体を熱
処理により溶融することによってその後形成するパッシ
ベーション膜の被覆率を向上させ耐湿性を向上、させる
効果がある。このとき、下部の導体膜（第１の導体膜）
は中央部の導体膜（第２の配線）と下地との合金反応を
抑制し、上部の導体膜（第３の導体膜）は中央部の導体
膜の溶融時に表面張力による過度の変形が生じない目的
で用いている。As explained above, the present invention improves the coverage of the passivation film that is subsequently formed by forming the wiring of a conductor film by sandwiching it between two different types of conductor films from above and below, and melting the conductor in the center through heat treatment. It has the effect of improving moisture resistance. At this time, the lower conductor film (first conductor film)
suppresses the alloy reaction between the central conductor film (second wiring) and the base, and the upper conductor film (third conductor film) is excessively deformed due to surface tension when the central conductor film is melted. It is used for no purpose.
実施例では、第１（下部）の導体膜に窒化チタン、第２
（中央部）の導体膜にアルミニウム、第３（上部）の導
体膜にタングステンを用いて説明したが、第１の導体膜
は下地と第２の導体膜との合金反応を抑制する材料であ
ればよく、また、第３の導体膜は、第２の導体膜よりも
融点が高い材料であればよい。In the example, the first (lower) conductor film is made of titanium nitride, the second
In the explanation, aluminum is used for the (center) conductor film and tungsten is used for the third (upper) conductor film, but the first conductor film may be made of a material that suppresses the alloy reaction between the base and the second conductor film. The third conductor film may be made of a material having a higher melting point than the second conductor film.
第１図（ａ）〜（ｄ）は本発明の第１の実施例の説明と
使用する縦断面図、第２図（ａ）（ｂ）は従来例とその
問題点を説明するための縦断面図、第３図（ａ）〜（ｃ
）は本発明の第２の実施例の工程順縦断面図である。
１０１・・・ｐ型シリコン基板、１０２・・・フィール
ド酸化膜、１０３・・・ゲート酸化膜、１０４−１゜１
０４−２・・・ゲート電極、１０５−１，１０５−２・
・・ｎ型不純物領域、１０６・・・第１の層間絶縁膜、
１０７・・・第１の配線、１０８・・・第２の眉間絶縁
膜、１０９−１，１０９−２．１０９−３・・・コンタ
クト開口部、１１０，３１０・・・窒化チタン膜、１１
１，１ｌｌａ、３１１・・・アルミニウム膜、１１２，
３１２・・・タングステン膜、１１３゜１１３−１，１
１３−２−・・第２の配線、１１４゜２１４ａ、２１４
ｂ、３１４−窒化シリコン膜、２１５．３１５・・・層
間絶縁膜、２１６−１ａ。
２１６−１ｂ、２１６−２ａ、２１６−２ｂ−−−アル
ミニウム配線、３１７・・・コンタクト開口部、３１８
・・・ボイド。Figures 1 (a) to (d) are longitudinal cross-sectional views used to explain the first embodiment of the present invention, and Figures 2 (a) and (b) are longitudinal cross-sectional views for explaining the conventional example and its problems. Top view, Figures 3(a) to (c)
) is a vertical cross-sectional view in the order of steps of a second embodiment of the present invention. 101...p-type silicon substrate, 102...field oxide film, 103...gate oxide film, 104-1゜1
04-2...Gate electrode, 105-1, 105-2.
. . . n-type impurity region, 106 . . . first interlayer insulating film,
107... First wiring, 108... Second eyebrow insulating film, 109-1, 109-2.109-3... Contact opening, 110, 310... Titanium nitride film, 11
1,1lla, 311...aluminum film, 112,
312...Tungsten film, 113°113-1,1
13-2--Second wiring, 114°214a, 214
b, 314-silicon nitride film, 215.315... interlayer insulating film, 216-1a. 216-1b, 216-2a, 216-2b---Aluminum wiring, 317... Contact opening, 318
···void.
Claims (1)
導体膜より融点の高い第３の導体膜を順次積層して多層
膜を形成したのち選択的に除去して前記第３の導体膜の
幅が第２の導体膜の幅より小さな多層膜配線を形成し、
熱処理により前記第２の導体膜の少なくとも一部を溶融
する工程を有することを特徴とする半導体装置の製造方
法。A first conductor film, a second conductor film, and a third conductor film having a higher melting point than the second conductor film are sequentially laminated on the substrate to form a multilayer film, and then selectively removed to form the third conductor film. forming a multilayer wiring in which the width of the conductor film is smaller than the width of the second conductor film;
A method for manufacturing a semiconductor device, comprising the step of melting at least a portion of the second conductor film by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21555290A JPH0497531A (en) | 1990-08-15 | 1990-08-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21555290A JPH0497531A (en) | 1990-08-15 | 1990-08-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0497531A true JPH0497531A (en) | 1992-03-30 |
Family
ID=16674321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21555290A Pending JPH0497531A (en) | 1990-08-15 | 1990-08-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0497531A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333518B1 (en) | 1997-08-26 | 2001-12-25 | Lg Electronics Inc. | Thin-film transistor and method of making same |
| US6340610B1 (en) | 1997-03-04 | 2002-01-22 | Lg. Philips Lcd Co., Ltd | Thin-film transistor and method of making same |
| JP2013171940A (en) * | 2012-02-20 | 2013-09-02 | Ulvac Japan Ltd | Semiconductor device manufacturing method |
-
1990
- 1990-08-15 JP JP21555290A patent/JPH0497531A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6340610B1 (en) | 1997-03-04 | 2002-01-22 | Lg. Philips Lcd Co., Ltd | Thin-film transistor and method of making same |
| US6548829B2 (en) | 1997-03-04 | 2003-04-15 | Lg Lcd Inc. | Thin-film transistor |
| US6815321B2 (en) | 1997-03-04 | 2004-11-09 | Lg. Philips Lcd Co., Ltd. | Thin-film transistor and method of making same |
| US7176489B2 (en) | 1997-03-04 | 2007-02-13 | Lg. Philips Lcd. Co., Ltd. | Thin-film transistor and method of making same |
| USRE45579E1 (en) | 1997-03-04 | 2015-06-23 | Lg Display Co., Ltd. | Thin-film transistor and method of making same |
| US6333518B1 (en) | 1997-08-26 | 2001-12-25 | Lg Electronics Inc. | Thin-film transistor and method of making same |
| US6573127B2 (en) | 1997-08-26 | 2003-06-03 | Lg Electronics Inc. | Thin-film transistor and method of making same |
| JP2013171940A (en) * | 2012-02-20 | 2013-09-02 | Ulvac Japan Ltd | Semiconductor device manufacturing method |
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