JPH0497519A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0497519A
JPH0497519A JP21554490A JP21554490A JPH0497519A JP H0497519 A JPH0497519 A JP H0497519A JP 21554490 A JP21554490 A JP 21554490A JP 21554490 A JP21554490 A JP 21554490A JP H0497519 A JPH0497519 A JP H0497519A
Authority
JP
Japan
Prior art keywords
growth
polysilicon
film
silicon substrate
polysilicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21554490A
Other languages
Japanese (ja)
Inventor
Toru Aoyama
亨 青山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21554490A priority Critical patent/JPH0497519A/en
Publication of JPH0497519A publication Critical patent/JPH0497519A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To curtail growth period and improve throughput by forming a base layer of thin plysilicon thin film on a silicon substrate in the initial growth stage under the condition of low temperature selective polysilicon growth and then allow the growth of polysilicon film under the condition of a high temperature selective epitaxial growth. CONSTITUTION:After forming a silicon oxide film 9 on a single crystalline silicon substrate 7, a contact hole 8 is formed thereon. Next, a thin polysilicon film 10 is selectively grown on a substrate 7, growth is once stopped, and temperature is raised. Thereafter, polysilicon is selectively grown only on the film 10 and a thick polysilicon film 10 is grown. Namely, a base layer of thin polysilicon film is formed on the silicon substrate under the condition of low temperature selective polysilicon growth and then a polysilicon film is grown under the condition of high temperature selective epitaxial growth. Thereby, a growth time can be curtailed and throughput can also be improved remarkably.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に間し、特に選択ポリシ
リコン成長法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a selective polysilicon growth method.

〔従来の技術〕[Conventional technology]

酸化膜で覆われたシリコン基板の開口部に選択的にシリ
コンを成長する穴埋め技術として、選択エピタキシャル
成長がある(特開昭57−37829)。
Selective epitaxial growth is a hole-filling technique for selectively growing silicon in the openings of a silicon substrate covered with an oxide film (Japanese Patent Laid-Open No. 57-37829).

これは第4図(a)に示すように、コンタクト孔8を有
する絶縁膜12で覆われた単結晶シリコン基板7に、第
4図(b)に示すようにシリコンエピタキシャル層13
を成長させる。
As shown in FIG. 4(a), a single crystal silicon substrate 7 covered with an insulating film 12 having a contact hole 8 is covered with a silicon epitaxial layer 13 as shown in FIG. 4(b).
grow.

このとき周りの絶縁膜12上にはシリコンを堆積させる
ことなく、穴を埋めるように単結晶シリコン7上にのみ
、下地の単結晶シリコン7と同じ結晶方位の単結晶シリ
コンからなるエピタキシャル層13を、絶縁膜12とほ
ぼ等しい厚さに成長させる。
At this time, without depositing silicon on the surrounding insulating film 12, an epitaxial layer 13 made of single crystal silicon having the same crystal orientation as the underlying single crystal silicon 7 is formed only on the single crystal silicon 7 so as to fill the hole. , is grown to a thickness approximately equal to that of the insulating film 12.

第4図(a)の状態で配線層を形成しようとすると、第
5図(a)に示すように、電極配線層14に薄い部分が
生じて高抵抗化や断線の危険性の問題があるが、選択エ
ピタキシャル成長のあと第4図(b)の状態で配線層を
形成すると、第5図(b)に示すように、平坦な配線層
14を形成することができる。
If an attempt is made to form a wiring layer in the state shown in FIG. 4(a), thin portions will occur in the electrode wiring layer 14 as shown in FIG. However, if a wiring layer is formed in the state shown in FIG. 4(b) after selective epitaxial growth, a flat wiring layer 14 can be formed as shown in FIG. 5(b).

選択エピタキシャル成長はジクロロシラン(S1H2C
ρ2)などのシラン系ガスを水素(H2)で熱分解ある
いは還元して、単結晶シリコン基板7にシリコンエピタ
キシャル層13を堆積させると同時に、絶縁膜12の上
に堆積するポリシリコンを塩化水素(HCJ)でエツチ
ングすることにより実現される。
Selective epitaxial growth is performed using dichlorosilane (S1H2C
At the same time, the silicon epitaxial layer 13 is deposited on the single-crystal silicon substrate 7 by thermally decomposing or reducing a silane-based gas such as ρ2) with hydrogen (H2), and at the same time, the polysilicon deposited on the insulating film 12 is heated with hydrogen chloride (H2). This is achieved by etching with HCJ).

塩化水素の流量を選ぶことにより絶縁膜12の上にはポ
リシリコンが堆積することなく、コンタクト孔8のみに
シリコンエピタキシャル層13が成長する選択エピタキ
シャル成長になる。
By selecting the flow rate of hydrogen chloride, selective epitaxial growth is achieved in which the silicon epitaxial layer 13 grows only in the contact hole 8 without depositing polysilicon on the insulating film 12.

成長条件の1例をあげると、成長温度850℃でジクロ
ロシラン:塩化水素=2=1になるように、ジクロロシ
ラン(SiHzCfflz>などのシラン系ガス、水素
(H2)および塩化水素(HCj)のガスを流す。
To give an example of growth conditions, a silane-based gas such as dichlorosilane (SiHzCfflz), hydrogen (H2) and hydrogen chloride (HCj) are used so that dichlorosilane:hydrogen chloride=2=1 at a growth temperature of 850°C. Let the gas flow.

もう1つの選択ポリシリコン成長は、第4図(C)に示
すようにコンタクト孔8にポリシリコン膜10を成長さ
せるものであル。
Another selective polysilicon growth is to grow a polysilicon film 10 in the contact hole 8 as shown in FIG. 4(C).

バイポーラトランジスタのエミッタ形成の際に、特に穴
埋めによる平坦化技術が重要になっている。
When forming the emitter of a bipolar transistor, planarization technology using hole filling is particularly important.

単結晶シリコン基板に直接Asをイオン注入すると浅い
エミッタ接合を形成することができないので、高いt流
増幅率や高周波特性を得るためことができない。
If As is ion-implanted directly into a single-crystal silicon substrate, a shallow emitter junction cannot be formed, so it is impossible to obtain a high t-current amplification factor or high-frequency characteristics.

そのためNPN)−ランジスタの場合、第6図(a)に
示すようにベース層15を形成し、コンタクト孔8を有
する酸化シリコン膜9を形成したのち、第6図(b)に
示すように、コンタクト孔8に厚さ200nmのポリシ
リコン膜10を堆積する。
Therefore, in the case of an NPN transistor, after forming a base layer 15 as shown in FIG. 6(a) and forming a silicon oxide film 9 having a contact hole 8, as shown in FIG. 6(b), A polysilicon film 10 with a thickness of 200 nm is deposited in the contact hole 8 .

そのあと第6図(C)、(d)に示すように、Asなど
のN型の不純物をイオン注入し、アニル熱処理により拡
散して浅いN型エミツタ層16を形成する。ポリシリコ
ン膜10は通常エミッタ配線の引出しを兼ねている。
Thereafter, as shown in FIGS. 6C and 6D, N-type impurities such as As are ion-implanted and diffused by annealing to form a shallow N-type emitter layer 16. The polysilicon film 10 usually also serves as a lead-out for emitter wiring.

従来は単結晶シリコン基板7の上に通常のポリシリコン
膜10を成長させるだけであったが、集積回路のパター
ン微細化に伴い、コンタクト孔のサイズがサブミクロン
のオーダーに達してアスペクト比が大きく、平坦化の技
術が重要となり選択ポリシリコン成長が重要になってき
た。
Conventionally, a regular polysilicon film 10 was simply grown on a single-crystal silicon substrate 7, but with the miniaturization of integrated circuit patterns, the size of contact holes has reached the submicron order and the aspect ratio has increased. , planarization technology has become important, and selective polysilicon growth has become important.

さらに選択的に金属シリサイド層を埋設したコンタクト
孔に選択的にシリコンを成長させる方法がある(特開昭
58−34916>。
Furthermore, there is a method in which silicon is selectively grown in a contact hole in which a metal silicide layer is selectively buried (Japanese Patent Laid-Open No. 58-34916).

この場合は選択性を与えるために金属シリサイド層を必
要とて工数が増えるうえに、エミッタ形成に利用するこ
とができない。
In this case, a metal silicide layer is required to provide selectivity, which increases the number of steps, and it cannot be used for emitter formation.

第4図(C)のように直接単結晶シリコン基板7上のコ
ンタクト孔8を埋める選択ポリシリコン膜10の成長は
実用化されていない。
The growth of selective polysilicon film 10 directly filling contact hole 8 on single crystal silicon substrate 7 as shown in FIG. 4(C) has not been put to practical use.

選択エピタキシャル成長の成長温度を750℃に下げ、
ガスの条件をジクロロシラン:塩化水素=8:1に変え
ることによって、第4図(c)に示すようにエピタキシ
ャル膜13に代わってポリシリコン膜10がコンタクト
孔8の中に堆積する選択ポリシリコン成長が実現される
Lowering the growth temperature of selective epitaxial growth to 750°C,
By changing the gas conditions to dichlorosilane:hydrogen chloride=8:1, a selective polysilicon film 10 is deposited in the contact hole 8 instead of the epitaxial film 13, as shown in FIG. 4(c). Growth is achieved.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のポリシリコン成長法においては、シリコン上にの
み成長させるなめ塩化水素でエツチングしながら成長し
ている。また成長温度を上げるとエピタキシャル成長と
なってしまい多結晶化しないために成長温度を上げられ
ない。
In the conventional polysilicon growth method, polysilicon is grown only on silicon by etching with hydrogen chloride. Furthermore, if the growth temperature is raised, epitaxial growth occurs and polycrystalization does not occur, so the growth temperature cannot be raised.

そのため成長速度が選択エピタキシャル成長に対して約
1桁遅いという欠点がある。
Therefore, there is a drawback that the growth rate is about one order of magnitude slower than that of selective epitaxial growth.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、成長初期の段階では
、低温の選択ポリシリコン成長の条件でシリコン基板上
にポリシリコン薄膜の下地をつくり、つぎに高温の選択
エピタキシャル成長の条件で、引き続きポリシリコン膜
を成長させるものである。
In the manufacturing method of a semiconductor device of the present invention, in the early stage of growth, a polysilicon thin film is formed on a silicon substrate under low-temperature selective polysilicon growth conditions, and then a polysilicon thin film is formed on a silicon substrate under high-temperature selective epitaxial growth conditions. It grows a film.

〔実施例〕〔Example〕

はじめに本発明で用いるポリシリコン膜の気相成長装置
について、第1図を参照して説明する。
First, a vapor phase growth apparatus for polysilicon films used in the present invention will be explained with reference to FIG.

石英ガラスでできたチャンバー3の中で、回転している
基板支持台5の上に被成長基板4が固定されている。
A growth substrate 4 is fixed on a rotating substrate support 5 in a chamber 3 made of quartz glass.

被成長基板4は、チャンバー3の周りの赤外線ランプ2
によって所定の温度に加熱されている。
The growth substrate 4 is provided with infrared lamps 2 around the chamber 3.
is heated to a predetermined temperature.

チャンバー3の上部には、反応ガス導入口lが設けられ
ており、シリコン薄膜を成長させるためのジクロロシラ
ンなどのシラン系ガス、水素および塩化水素が被成長基
板4に吹き付けられている。
A reactive gas inlet 1 is provided at the top of the chamber 3, and a silane gas such as dichlorosilane, hydrogen, and hydrogen chloride for growing a silicon thin film are blown onto the growth substrate 4.

成長に関与しなかったガスは、ガス排出口6を通って真
空ポンプで排気される。
Gas not involved in the growth is exhausted through the gas outlet 6 by a vacuum pump.

つぎに本発明の第1の実施例について、第2図(a)〜
(c)を参照して説明する。
Next, regarding the first embodiment of the present invention, FIGS.
This will be explained with reference to (c).

はじめに第2図(a)に示すように単結晶シリコン基板
7に厚さ500nmの酸化シリコン膜9を形成し、さら
にサブミクロンないし数ミクロンの大きさの平面寸法の
コンタクト孔8を形成する。
First, as shown in FIG. 2(a), a silicon oxide film 9 with a thickness of 500 nm is formed on a single-crystal silicon substrate 7, and a contact hole 8 with a planar size of submicron to several microns is further formed.

つぎに第2図(b)に示すように、チャンバー内圧力は
30To o r、温度750℃でジクロロシランを4
0QSCCm、塩化水素を50secm、ジクロロシラ
ンと塩化水素の比が8=1になるように20分間流して
、単結晶シリコン基板7上に選択的に厚さ30nmの薄
いポリシリコン膜10を成長させた。
Next, as shown in Fig. 2(b), dichlorosilane was poured into the chamber at a pressure of 30 Torr and a temperature of 750°C.
A thin polysilicon film 10 with a thickness of 30 nm was selectively grown on the single crystal silicon substrate 7 by flowing 0QSCCm and hydrogen chloride for 50 seconds so that the ratio of dichlorosilane and hydrogen chloride was 8=1. .

つぎに第2図(c)に示すようにいったん成長を止めて
温度を850℃に上げたのち、ジクロロシランと塩化水
素の比を2=1となるようにジクロロシラン300se
cm、塩化水素150secm流して10分間成長させ
た。するとポリシリコンが、ポリシリコン膜10の上に
のみに選択的に成長し、厚さ200nmの厚いポリシリ
コン膜10が成長した。
Next, as shown in Figure 2(c), after stopping the growth and raising the temperature to 850°C, 300 se of dichlorosilane was added so that the ratio of dichlorosilane and hydrogen chloride was 2=1.
cm, and hydrogen chloride was flowed at 150 sec for 10 minutes. Then, polysilicon selectively grew only on the polysilicon film 10, and a thick polysilicon film 10 with a thickness of 200 nm was grown.

厚さ200nmの選択多結晶シリコンは、バイポーラト
ランジスタのエミッタ形成を想定したものである。
The selected polycrystalline silicon with a thickness of 200 nm is intended for forming the emitter of a bipolar transistor.

850℃の成長条件のときの成長速度は17nm/mi
nと750℃の成長速度(1,5nm、/mi n)に
比べると約10倍となる。
The growth rate under the growth condition of 850°C is 17 nm/mi.
This is approximately 10 times the growth rate (1.5 nm,/min) at 750°C.

850℃の条件でシリコン薄膜をいきなり単結晶シリコ
ン基板7に成長させると選択エピタキシャル成長になっ
てしまい、ポリシリコンを上記のような速い速度で成長
させることはできなかった。
If a silicon thin film were suddenly grown on the single-crystal silicon substrate 7 under conditions of 850° C., selective epitaxial growth would occur, making it impossible to grow polysilicon at such a fast rate.

本発明では、最初に下地となるさまざまな結晶方位をも
つポリシリコンを成長させてから、そのあとで高温にし
てもエピタキシャル化することなくポリシリコンの選択
成長を続けることができた。
In the present invention, after first growing polysilicon with various crystal orientations as a base, it was possible to continue selective growth of polysilicon without epitaxialization even at high temperatures.

本実施例において、温度を850℃に上げる時間も考慮
して、厚さ200nmの選択ポリシリコンを成長させる
のに合計50分を要し、実質のガスを流している成長時
間は30分であった。
In this example, considering the time to raise the temperature to 850°C, it took a total of 50 minutes to grow selective polysilicon with a thickness of 200 nm, and the actual growth time with gas flowing was 30 minutes. Ta.

従来の方法では1回成長させるのに100分かかってい
たので、本発明によれば、成長速度は実効的に2倍に増
加したことになる。
In the conventional method, it took 100 minutes for one growth, so according to the present invention, the growth rate is effectively doubled.

つぎに本発明の第2の実施例として、コンタクト孔の穴
埋めについて第3図(a)〜(c)を参照して説明する
。ここで用いた装置は、実施例1と同じものである。
Next, as a second embodiment of the present invention, filling of contact holes will be described with reference to FIGS. 3(a) to 3(c). The device used here is the same as in Example 1.

はじめに第3図(a)に示すように、シリコン基板7上
に、コンタクト孔8を有し、絶縁膜となる厚さ500n
mのP S G (phospho−silicate
 glass)膜11を形成する。
First, as shown in FIG. 3(a), a contact hole 8 is formed on a silicon substrate 7, and a thickness of 500 nm is formed to serve as an insulating film.
m of P S G (phospho-silicate
A glass) film 11 is formed.

つぎに第3図(b)、(c)に示すように、コンタクト
孔8の中にPSGIIllと同じ厚さのポリシリコン膜
10を選択成長させる。
Next, as shown in FIGS. 3(b) and 3(c), a polysilicon film 10 having the same thickness as PSG IIll is selectively grown in the contact hole 8.

成長条件は第1の実施例と同様に、まず第3図(b)に
示すように、750℃で下地となる厚さ30nmのポリ
シリコン膜10を20分間成長させる。
The growth conditions are the same as in the first embodiment, and first, as shown in FIG. 3(b), a polysilicon film 10 with a thickness of 30 nm as a base is grown at 750° C. for 20 minutes.

つぎに第3図(c)に示すように、いったん成長を止め
、850℃に昇温してからポリシリコン膜10をジクロ
ロシラン300secmに対して塩化水素150sec
mの条件で30分間成長し、PSG膜11に開けたコン
タクト孔8をポリシリコン膜lOで埋めた。
Next, as shown in FIG. 3(c), once the growth is stopped and the temperature is raised to 850° C., the polysilicon film 10 is coated with dichlorosilane for 300 seconds and hydrogen chloride for 150 seconds.
The contact hole 8 made in the PSG film 11 was filled with a polysilicon film IO.

その結果、コンタクト孔8の中に厚さ500nmのポリ
シリコン膜lOを成長させるのに費やした時間は、温度
を750℃から800℃に上げる時間もいれて70分で
あった。従来の750℃のみの成長方法だと、成長速度
が1.5nm/minと遅いため、500nm成長させ
るのに300分かかってしまうのに対して大幅に成長時
間の短縮がはかれたことになる。
As a result, the time it took to grow a 500 nm thick polysilicon film IO in the contact hole 8 was 70 minutes, including the time to raise the temperature from 750°C to 800°C. With the conventional growth method of only 750°C, the growth rate is slow at 1.5 nm/min, so it takes 300 minutes to grow 500 nm, but this means that the growth time has been significantly shortened. .

このようなコンタクト孔の穴埋めの場合は、エミッタ形
成の場合よりも大きい成長膜厚を要するので、効果がさ
らに大きくなる。
In the case of filling such a contact hole, a larger growth film thickness is required than in the case of emitter formation, so that the effect is even greater.

〔発明の効果〕〔Effect of the invention〕

成長初期の段階では、低温の選択ポリシリコン成長の条
件でシリコン基板上にポリシリコンff膜の下地をつく
り、つぎに高温の選択エピタキシャル成長の条件で、引
き続きポリシリコン膜を成長させることにより、成長時
間の短縮が実現でき、スルーブツトの大幅な向上ができ
る効果がある。
At the early stage of growth, a polysilicon FF film is formed on the silicon substrate under low-temperature selective polysilicon growth conditions, and then the polysilicon film is subsequently grown under high-temperature selective epitaxial growth conditions to shorten the growth time. This has the effect of significantly increasing throughput.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明で用いた選択ポリシリコン用の気相成長
装置の断面図、第2図(a)〜(c)は本発明の第1の
実施例を工程順に示す断面図、第3図(a)〜(c)は
本発明の第2の実施例を工程順に示す断面図、第4図(
a)〜(c)は従来技術による選択成長を示す断面図、
第5図(a)(b)は電極配線を示す断面図、第6図(
a)〜(d)はNPN)−ランジスタのエミッタ形成を
工程順に示す断面図である。 1・・・反応ガス導入口、2・・・赤外線ランプ、3・
・・チャンバー、4・・・被成長基板、5・・・基板支
持台、6・・・ガス排出口、7・・・単結晶シリコン基
板、8・・・コンタクト孔、9・・・酸化シリコン膜、
1o・・・ポリシリコン膜、11・・・PSGWi、1
2・・・絶縁膜、13・・・シリコンエピタキシャル層
、14・・・電極配線層、15・・・ベース層、16・
・・エミツタ層。
FIG. 1 is a cross-sectional view of a vapor phase growth apparatus for selective polysilicon used in the present invention, FIGS. 2(a) to (c) are cross-sectional views showing the first embodiment of the present invention in order of process, Figures (a) to (c) are cross-sectional views showing the second embodiment of the present invention in order of process, and Figure 4 (
a) to (c) are cross-sectional views showing selective growth by conventional technology;
5(a) and 5(b) are cross-sectional views showing electrode wiring, and FIG.
3A to 4D are cross-sectional views illustrating the formation of an emitter of an NPN transistor in the order of steps; 1... Reaction gas inlet, 2... Infrared lamp, 3...
...Chamber, 4...Growth substrate, 5...Substrate support, 6...Gas exhaust port, 7...Single crystal silicon substrate, 8...Contact hole, 9...Silicon oxide film,
1o...Polysilicon film, 11...PSGWi, 1
2... Insulating film, 13... Silicon epitaxial layer, 14... Electrode wiring layer, 15... Base layer, 16...
...Emitsuta layer.

Claims (1)

【特許請求の範囲】[Claims]  開口部を有する酸化シリコン膜で被覆された単結晶シ
リコン基板に、第1の成長温度でポリシリコンを前記開
口部に薄く選択成長させたのち、前記第1の成長温度よ
りも高い第2の成長温度でポリシリコンを前記開口部に
厚く選択成長させることを特徴とする半導体装置の製造
方法。
A single crystal silicon substrate covered with a silicon oxide film having an opening is selectively grown thinly in the opening at a first growth temperature, and then a second growth is performed at a temperature higher than the first growth temperature. A method of manufacturing a semiconductor device, comprising selectively growing polysilicon thickly in the opening at a temperature.
JP21554490A 1990-08-15 1990-08-15 Manufacture of semiconductor device Pending JPH0497519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21554490A JPH0497519A (en) 1990-08-15 1990-08-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21554490A JPH0497519A (en) 1990-08-15 1990-08-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0497519A true JPH0497519A (en) 1992-03-30

Family

ID=16674188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21554490A Pending JPH0497519A (en) 1990-08-15 1990-08-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0497519A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065514A (en) * 1992-06-23 1994-01-14 Nippon Telegr & Teleph Corp <Ntt> Selective growth method for compound semiconductor thin film
US5342792A (en) * 1986-03-07 1994-08-30 Canon Kabushiki Kaisha Method of manufacturing semiconductor memory element
US5387538A (en) * 1992-09-08 1995-02-07 Texas Instruments, Incorporated Method of fabrication of integrated circuit isolation structure
JPH08139017A (en) * 1994-11-11 1996-05-31 Nec Corp Manufacture of semiconductor device
KR100334961B1 (en) * 1998-12-30 2002-06-20 박종섭 Method of forming multi-layered metal wiring in semiconductor device
KR100407683B1 (en) * 2000-06-27 2003-12-01 주식회사 하이닉스반도체 Method of forming a contact plug in a semiconductor device
JP2007005380A (en) * 2005-06-21 2007-01-11 Toshiba Corp Semiconductor device
US7402487B2 (en) * 2004-10-18 2008-07-22 Infineon Technologies Richmond, Lp Process for fabricating a semiconductor device having deep trench structures
JP2009088305A (en) * 2007-10-01 2009-04-23 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor device
JP2010171101A (en) * 2009-01-21 2010-08-05 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor apparatus, and substrate processing apparatus

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342792A (en) * 1986-03-07 1994-08-30 Canon Kabushiki Kaisha Method of manufacturing semiconductor memory element
JPH065514A (en) * 1992-06-23 1994-01-14 Nippon Telegr & Teleph Corp <Ntt> Selective growth method for compound semiconductor thin film
US5387538A (en) * 1992-09-08 1995-02-07 Texas Instruments, Incorporated Method of fabrication of integrated circuit isolation structure
JPH08139017A (en) * 1994-11-11 1996-05-31 Nec Corp Manufacture of semiconductor device
KR100334961B1 (en) * 1998-12-30 2002-06-20 박종섭 Method of forming multi-layered metal wiring in semiconductor device
KR100407683B1 (en) * 2000-06-27 2003-12-01 주식회사 하이닉스반도체 Method of forming a contact plug in a semiconductor device
US7402487B2 (en) * 2004-10-18 2008-07-22 Infineon Technologies Richmond, Lp Process for fabricating a semiconductor device having deep trench structures
JP2007005380A (en) * 2005-06-21 2007-01-11 Toshiba Corp Semiconductor device
JP2009088305A (en) * 2007-10-01 2009-04-23 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor device
JP2010171101A (en) * 2009-01-21 2010-08-05 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor apparatus, and substrate processing apparatus

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