CN116525418B - Silicon epitaxial wafer preparation method based on 111 crystal orientation, silicon epitaxial wafer and semiconductor device - Google Patents
Silicon epitaxial wafer preparation method based on 111 crystal orientation, silicon epitaxial wafer and semiconductor device Download PDFInfo
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- CN116525418B CN116525418B CN202310686810.6A CN202310686810A CN116525418B CN 116525418 B CN116525418 B CN 116525418B CN 202310686810 A CN202310686810 A CN 202310686810A CN 116525418 B CN116525418 B CN 116525418B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 95
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 95
- 239000010703 silicon Substances 0.000 title claims abstract description 95
- 239000013078 crystal Substances 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims description 11
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 2
- 239000005052 trichlorosilane Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 21
- 238000004519 manufacturing process Methods 0.000 abstract description 17
- 235000012431 wafers Nutrition 0.000 description 63
- 239000007789 gas Substances 0.000 description 25
- 238000010926 purge Methods 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910000085 borane Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02634—Homoepitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a 111 crystal orientation-based silicon epitaxial wafer preparation method, a silicon epitaxial wafer and a semiconductor device. The method comprises the following steps: carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer; etching the first epitaxial layer; and carrying out low-speed 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer to obtain a second epitaxial layer, wherein the silicon wafer, the etched first epitaxial layer and the etched second epitaxial layer form a silicon epitaxial wafer based on the 111 crystal orientation. According to the invention, the first epitaxial layer is grown on the surface of the silicon wafer at a high speed, so that the efficiency is higher compared with the conventional growth speed, then the first epitaxial layer is etched, the part with fog defects on the surface of the first epitaxial layer can be removed, and finally the low-speed growth is performed on the surface of the first epitaxial layer, so that the surface of the final silicon epitaxial wafer is smooth and stable, the production efficiency is higher compared with the whole-course slow-speed growth, and the problem of fog defects on the surface of the silicon epitaxial wafer grown at a high speed is solved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a 111 crystal orientation-based silicon epitaxial wafer preparation method, a silicon epitaxial wafer and a semiconductor device.
Background
The silicon epitaxial wafer based on the 111 crystal orientation has wide application in power devices such as schottky, triodes, fast recovery diodes and the like, and along with the gradual improvement of the requirements of customers on the manufacturing process and the product quality, the silicon epitaxial wafer based on the 111 crystal orientation has higher uniformity requirements on large-size silicon epitaxial wafers (with the diameter of 200mm and above). Therefore, silicon epitaxial wafer manufacturers generally adopt single-wafer type silicon epitaxial furnaces for production, and compared with multi-wafer type silicon epitaxial furnaces, the absolute advantage of single wafer type silicon epitaxial furnaces in terms of product uniformity is undoubted, and meanwhile, higher requirements are also put on the production efficiency of single wafer type epitaxial furnaces, and higher growth rates are required for achieving.
For a single-wafer silicon epitaxial furnace, when 111-crystal-orientation silicon epitaxial growth is carried out by adopting a conventional process, if the growth rate is higher than 3.6 mu m/min, fog defects appear on the surface of the silicon epitaxial wafer, and the product is unqualified.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a silicon epitaxial wafer based on a 111 crystal orientation, the silicon epitaxial wafer and a semiconductor device, and aims to solve the problem that fog defects exist on the surface of a silicon epitaxial wafer growing at a high rate.
In a first aspect, an embodiment of the present invention provides a method for preparing a silicon epitaxial wafer based on 111 crystal orientation, including:
carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer;
etching the first epitaxial layer;
and carrying out low-speed 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer to obtain a second epitaxial layer, wherein the silicon wafer, the etched first epitaxial layer and the second epitaxial layer form a silicon epitaxial wafer based on the 111 crystal orientation.
In one possible implementation, performing high-rate 111 crystal outgrowth on the surface of the silicon wafer to obtain the first epitaxial layer includes:
and (3) carrying out 111 crystal orientation epitaxial growth with the growth rate of 5.4-6.4 mu m/min on the surface of the silicon wafer to obtain a first epitaxial layer.
In one possible implementation, the thickness of the first epitaxial layer is 5-8 μm.
In one possible implementation, performing high-rate 111 crystal outgrowth on the surface of the silicon wafer to obtain the first epitaxial layer includes:
introducing TCS gas into a reaction cavity of a monolithic epitaxial furnace where the silicon wafer is positioned at the temperature of 990-1090 ℃ at the gas flow of 12-16L/min, introducing doping gas into the reaction cavity at the gas flow of 30-270mL/min, and carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer.
In one possible implementation, etching the first epitaxial layer includes:
and (3) under the condition of 990-1090 ℃, introducing HCl gas into a reaction cavity of the monolithic epitaxial furnace where the silicon wafer is positioned at the gas flow of 0.5-2L/min, and etching the first epitaxial layer.
In one possible implementation, etching the first epitaxial layer includes:
etching the first epitaxial layer to a thickness of 0.5-2 μm.
In one possible implementation, performing low-rate epitaxial growth of 111 crystal directions on the surface of the etched first epitaxial layer, and obtaining the second epitaxial layer includes:
and carrying out 111 crystal orientation epitaxial growth with the growth rate of 2.8-3.6 mu m/min on the surface of the etched first epitaxial layer to obtain the silicon epitaxial wafer based on the 111 crystal orientation.
In one possible implementation, the second epitaxial layer has a thickness of 1-2 μm.
In a second aspect, embodiments of the present invention provide a silicon epitaxial wafer obtained based on the steps of the method as described above in the first aspect or any one of the possible implementation manners of the first aspect.
In a third aspect, embodiments of the present invention provide a semiconductor device including the silicon epitaxial wafer of the above second aspect.
The embodiment of the invention provides a 111 crystal orientation-based silicon epitaxial growth method, which has the beneficial effects that:
according to the invention, the first epitaxial layer is grown on the surface of the silicon wafer at a high speed, so that the efficiency is higher compared with the conventional growth speed, then the first epitaxial layer is etched, the part with fog defects on the surface of the first epitaxial layer can be removed, and finally the low-speed growth is performed on the surface of the first epitaxial layer, so that the surface of the final silicon epitaxial wafer is smooth and stable, the production efficiency is higher compared with the whole-course slow-speed growth, and the problem of fog defects on the surface of the silicon epitaxial wafer grown at a high speed is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an implementation of a method for preparing a silicon epitaxial wafer based on 111 crystal orientation according to an embodiment of the present invention;
fig. 2 is a flowchart of an implementation of a method for preparing a silicon epitaxial wafer based on 111 crystal orientation according to another embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following description will be made by way of specific embodiments with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of an implementation of a preparation method of a silicon epitaxial wafer based on a 111 crystal orientation according to an embodiment of the present invention is shown, and details are as follows:
and step 101, carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer.
In this embodiment, the monolithic silicon epitaxial furnace has absolute advantage in terms of product uniformity as compared to the multi-wafer silicon epitaxial furnace. When the conventional process is adopted for carrying out 111-crystal-orientation silicon epitaxial growth, if the growth rate is higher than 3.6 mu m/min, fog defects appear on the surface of the silicon epitaxial wafer. And etching the silicon epitaxial wafer with the fog defect by a Sirtl method for 5min, and displaying a swirl defect on the lower surface of a microscopic microscope. The cause of the mist defect is mainly related to the micro roughness of the <111> crystal orientation surface, and the micro holes appear on the surface of the silicon epitaxial wafer after high-speed growth. If a low growth rate process is adopted, the occurrence of the surface haze defect of the silicon epitaxial wafer can be effectively restrained, but at the same time, the production efficiency is reduced.
For the above reasons, the first epitaxial layer is grown at a high rate, so that the epitaxial layer can be obtained at a high speed, and the production efficiency requirement of the silicon epitaxial wafer is met.
Step 102, etching the first epitaxial layer.
In this embodiment, since the first epitaxial layer adopts a high-rate growth process, the surface has haze defects, and the first epitaxial layer is etched at this time, the surface of the first epitaxial layer can be smooth, and the problem of the haze defects on the first epitaxial layer is solved.
And 103, carrying out low-speed 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer to obtain a second epitaxial layer, wherein the silicon wafer, the etched first epitaxial layer and the etched second epitaxial layer form a silicon epitaxial wafer based on the 111 crystal orientation.
In this embodiment, the etched first epitaxial layer has a smooth surface and no fog defect, but the etched epitaxial layer has a higher surface activity, and at this time, an epitaxial layer is grown on the etched first epitaxial layer surface, so that the high-activity part of the first epitaxial layer surface can be covered, and the stability of the finally prepared silicon epitaxial wafer is ensured. Meanwhile, since the production efficiency of the epitaxial wafer is already improved in the step 101, enough time is available for the epitaxial layer growth in the step 103, the epitaxial growth can be performed at a low speed, and the surface of the epitaxial layer grown at the time is ensured to have no fog defect.
According to the embodiment of the invention, the first epitaxial layer is grown on the surface of the silicon wafer at a high speed, so that the efficiency is higher compared with the conventional growth speed, then the first epitaxial layer is etched, the part with fog defects on the surface of the first epitaxial layer can be removed, and finally the low-speed growth is performed on the surface of the first epitaxial layer, so that the surface of the final silicon epitaxial wafer is smooth and stable, the production efficiency is higher compared with the whole-course low-speed growth, and the problem that the fog defects exist on the surface of the silicon epitaxial wafer grown at a high speed is solved.
In one possible implementation, performing high-rate 111 crystal outgrowth on the surface of the silicon wafer to obtain the first epitaxial layer includes:
and (3) carrying out 111 crystal orientation epitaxial growth with the growth rate of 5.4-6.4 mu m/min on the surface of the silicon wafer to obtain a first epitaxial layer.
In this embodiment, the growth rate of the first epitaxial layer may be 5.4 to 6.4 μm/min, which can greatly improve the production efficiency compared to the conventional growth rate (not higher than 3.6 μm/min) at which the haze defect is not generated.
In one possible implementation, the thickness of the first epitaxial layer is 5-8 μm.
In this embodiment, the thickness of the epitaxial layer on the silicon epitaxial wafer for the power device is typically 4-10 μm. In the actual production process, the thicker the first epitaxial layer, the more the length of time the high-rate growth is used, i.e. the higher the production efficiency. The thickness of the first epitaxial layer may be determined according to the actual requirements of the thickness of the epitaxial layer and the production efficiency.
In one possible implementation, performing high-rate 111 crystal outgrowth on the surface of the silicon wafer to obtain the first epitaxial layer includes:
introducing TCS gas into a reaction cavity of a monolithic epitaxial furnace where the silicon wafer is positioned at the temperature of 990-1090 ℃ at the gas flow of 12-16L/min, introducing doping gas into the reaction cavity at the gas flow of 30-270mL/min, and carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer.
In this embodiment, TCS (trichlorosilane, siHCl 3) gas is a growth material of an epitaxial layer, and a doping gas may be phosphine, borane, or the like. The type of doping gas is selected according to the actual requirements so as to adjust the electrical properties of the epitaxial layer.
In one possible implementation, etching the first epitaxial layer includes:
and (3) under the condition of 990-1090 ℃, introducing HCl gas into a reaction cavity of the monolithic epitaxial furnace where the silicon wafer is positioned at the gas flow of 0.5-2L/min, and etching the first epitaxial layer.
In the embodiment, HCl gas is common gas for etching, and the etching speed can be controlled in a lower range by 0.5-2L/min gas flow, so that the etching thickness is ensured to meet the production requirement.
In one possible implementation, etching the first epitaxial layer includes:
etching the first epitaxial layer to a thickness of 0.5-2 μm.
In this embodiment, the thickness of the mist defect on the surface of the epitaxial layer based on the 111 crystal orientation is usually 0.5-2 μm, and the etching thickness is selected based on the thickness range to etch the first epitaxial layer, so that the smooth and haze-free surface of the etched first epitaxial layer can be ensured, and the problem of insufficient thickness of the epitaxial layer can be avoided as far as possible.
In one possible implementation, performing low-rate epitaxial growth of 111 crystal directions on the surface of the etched first epitaxial layer, and obtaining the second epitaxial layer includes:
and carrying out 111 crystal orientation epitaxial growth with the growth rate of 2.8-3.6 mu m/min on the surface of the etched first epitaxial layer to obtain the silicon epitaxial wafer based on the 111 crystal orientation.
In the embodiment, when the growth rate is 2.8-3.6 μm/min, the obtained epitaxial layer has no fog defect on the surface, and the growth rate is relatively high, so that the production efficiency is not affected.
In one possible implementation, the second epitaxial layer has a thickness of 1-2 μm.
In this embodiment, the sum of the thickness of the etched first epitaxial layer and the thickness of the etched second epitaxial layer is the thickness of the epitaxial layer on the silicon epitaxial wafer, and the second epitaxial layer can ensure the stability of the epitaxial layer on the silicon epitaxial wafer and ensure that the thickness of the epitaxial layer on the silicon epitaxial wafer meets the production requirement. The thickness of the second epitaxial layer can be preset according to actual conditions, and can be adjusted according to the thickness of the etched first epitaxial layer after etching so as to adjust the thickness of the epitaxial layer on the silicon epitaxial wafer.
In a specific embodiment, the specific process for preparing the silicon epitaxial wafer based on the 111 crystal orientation based on the steps in the above embodiment is as follows:
in the whole process, carrier gas (hydrogen) with constant flow is continuously introduced into the cavity, the flow is 40-80L/min, the pressure in the reaction cavity is kept constant, and the pressure is generally 750-755Torr, and the names and the reaction conditions of the steps are shown in figure 2.
The first step: purging 1, wherein the process temperature is 650-700 ℃;
and a second step of: heating, and raising the process temperature to 1000-1100 ℃;
and a third step of: baking, maintaining the temperature at 1000-1100 ℃, and introducing 0.5-2L/min of HCl gas to perform air polishing on the surface of the silicon wafer;
fourth step: 1, reducing the process temperature to 990-1090 ℃, and introducing 12-16L/min of TCS gas and 30-270mL/min of doping gas for high-rate growth, wherein the growth rate is 5.4-6.4 mu m/min;
fifth step: purging 2, wherein the process temperature is maintained to be 990-1090 ℃;
sixth step: HCl etching, namely, introducing 0.5-2L/min of HCl gas, performing gas polishing on the surface of the epitaxial wafer, and removing surface fog defects;
seventh step: purging 3, wherein the process temperature is maintained to be 990-1090 ℃;
eighth step: depositing 2, namely introducing 4-8L/min of TCS gas and 30-270mL/min of doping gas for low-rate growth, wherein the growth rate is 2.8-3.6 mu m/min;
ninth step: purging 4, wherein the process temperature is maintained to be 990-1090 ℃;
tenth step: cooling to 650-700 deg.c.
The embodiment of the invention provides a silicon epitaxial wafer, which is obtained based on the steps of the method according to the first aspect or any one of the possible implementation manners of the first aspect.
An embodiment of the present invention provides a semiconductor device including the silicon epitaxial wafer of the above second aspect.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (7)
1. The preparation method of the silicon epitaxial wafer based on the 111 crystal orientation is characterized by comprising the following steps of:
carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer;
etching the first epitaxial layer;
carrying out low-speed 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer to obtain a second epitaxial layer, wherein the silicon wafer, the etched first epitaxial layer and the second epitaxial layer form a silicon epitaxial wafer based on the 111 crystal orientation;
and performing high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer, wherein the step of obtaining the first epitaxial layer comprises the following steps of:
carrying out 111 crystal orientation epitaxial growth with the growth rate of 5.4-6.4 mu m/min on the surface of the silicon wafer to obtain a first epitaxial layer;
and performing high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer, wherein the step of obtaining the first epitaxial layer comprises the following steps of:
introducing trichlorosilane gas into a reaction cavity of a monolithic epitaxial furnace where a silicon wafer is positioned at the temperature of 990-1090 ℃ at the gas flow of 12-16L/min, introducing doping gas into the reaction cavity at the gas flow of 30-270mL/min, and carrying out high-speed 111 crystal outward epitaxial growth on the surface of the silicon wafer to obtain a first epitaxial layer;
and carrying out low-rate 111 crystal orientation epitaxial growth on the surface of the etched first epitaxial layer, wherein the second epitaxial layer comprises:
and carrying out 111 crystal orientation epitaxial growth with the growth rate of 2.8-3.6 mu m/min on the surface of the etched first epitaxial layer to obtain the silicon epitaxial wafer based on the 111 crystal orientation.
2. The method for preparing a 111 crystal orientation based silicon epitaxial wafer according to claim 1, wherein the thickness of the first epitaxial layer is 5-8 μm.
3. The method for preparing a 111 crystal orientation-based silicon epitaxial wafer according to claim 1, wherein the etching the first epitaxial layer comprises:
and under the condition of 990-1090 ℃, HCl gas is introduced into a reaction cavity of the monolithic epitaxial furnace where the silicon wafer is positioned at the air flow of 0.5-2L/min, and the first epitaxial layer is etched.
4. The method for preparing a 111 crystal orientation-based silicon epitaxial wafer according to claim 1, wherein the etching the first epitaxial layer comprises:
and etching the first epitaxial layer with the thickness of 0.5-2 mu m.
5. The method for preparing a 111 crystal orientation based silicon epitaxial wafer according to claim 1, wherein the thickness of the second epitaxial layer is 1-2 μm.
6. A silicon epitaxial wafer, characterized in that it is obtained on the basis of the steps of the method according to any one of claims 1 to 5.
7. A semiconductor device comprising the silicon epitaxial wafer according to claim 6.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3945864A (en) * | 1974-05-28 | 1976-03-23 | Rca Corporation | Method of growing thick expitaxial layers of silicon |
| JP2015213102A (en) * | 2014-05-01 | 2015-11-26 | 信越半導体株式会社 | Method for manufacturing epitaxial wafer |
| CN106057650A (en) * | 2016-08-01 | 2016-10-26 | 中国电子科技集团公司第四十六研究所 | Preparation method of silicon epitaxial wafer for LDMOS transistor |
| CN106757324A (en) * | 2016-12-26 | 2017-05-31 | 南京国盛电子有限公司 | A kind of manufacture method of silicon epitaxial wafer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6190453B1 (en) * | 1999-07-14 | 2001-02-20 | Seh America, Inc. | Growth of epitaxial semiconductor material with improved crystallographic properties |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3945864A (en) * | 1974-05-28 | 1976-03-23 | Rca Corporation | Method of growing thick expitaxial layers of silicon |
| JP2015213102A (en) * | 2014-05-01 | 2015-11-26 | 信越半導体株式会社 | Method for manufacturing epitaxial wafer |
| CN106057650A (en) * | 2016-08-01 | 2016-10-26 | 中国电子科技集团公司第四十六研究所 | Preparation method of silicon epitaxial wafer for LDMOS transistor |
| CN106757324A (en) * | 2016-12-26 | 2017-05-31 | 南京国盛电子有限公司 | A kind of manufacture method of silicon epitaxial wafer |
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