CN106057650A - Preparation method of silicon epitaxial wafer for LDMOS transistor - Google Patents
Preparation method of silicon epitaxial wafer for LDMOS transistor Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 56
- 239000010703 silicon Substances 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000012360 testing method Methods 0.000 claims abstract description 35
- 230000007704 transition Effects 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005498 polishing Methods 0.000 claims abstract description 11
- 238000001816 cooling Methods 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 40
- 239000001257 hydrogen Substances 0.000 claims description 39
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 36
- 229910052739 hydrogen Inorganic materials 0.000 claims description 36
- 238000010926 purge Methods 0.000 claims description 32
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 229910003822 SiHCl3 Inorganic materials 0.000 claims description 16
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 16
- 239000002994 raw material Substances 0.000 claims description 15
- 239000000523 sample Substances 0.000 claims description 13
- 229910000085 borane Inorganic materials 0.000 claims description 11
- 230000000694 effects Effects 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 238000009826 distribution Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000002329 infrared spectrum Methods 0.000 claims description 5
- 230000005764 inhibitory process Effects 0.000 claims description 5
- 229910052753 mercury Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 5
- 238000003892 spreading Methods 0.000 claims description 5
- 230000007480 spreading Effects 0.000 claims description 5
- 238000010998 test method Methods 0.000 claims description 5
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 9
- 238000010408 sweeping Methods 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000003595 mist Substances 0.000 description 5
- 238000011109 contamination Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005282 brightening Methods 0.000 description 3
- -1 hydrogen Chemical class 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02634—Homoepitaxy
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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Abstract
The invention relates to a preparation method of a silicon epitaxial wafer for an LDMOS transistor. The method comprises a step of corroding an epitaxial furnace base, loading a silicon single crystal substrate piece into an epitaxial furnace barrel base pit, a step of carrying out HCI polishing on the surface of a silicon substrate piece, a step of growing a layer of intrinsic epitaxial layer on the silicon piece, a step of using HCI gas to remove a part of epitaxial surface with serious autodoping, a step of carrying out variable temperature and variable flow sweeping, a step of growing a doped epitaxial layer, a step of carrying out cooling after the growth of the doped epitaxial layer reaches a predetermined time, and a step of measuring the thickness of the epitaxial wafer, obtaining the thicknesses of five testing points and the resistivity of the five testing points, and using a resistance testing method to measure the transition area structure of the epitaxial wafer. The epitaxial wafer thickness and a resistivity uniformity level are raised, the nonuniformity is smaller than 1.5%, the probability of occurrence of crystal defects is reduced at the same time, the width of a transition area is shortened, the surfaces has no defects of fault, dislocation, glide line, fog and the like, and the use requirement of an LDMOS device is satisfied.
Description
Technical field
The present invention relates to the fabricating technology of a kind of semiconductor epitaxial material, particularly relate to a kind of ldmos transistor and use
The preparation method of silicon epitaxial wafer.
Background technology
Ldmos transistor has the advantages that gain is high, the linearity is good, switch performance is fast and thermal diffusivity is good, is particularly well-suited to
The fields such as CDMA, W-CDMA, Digital Image Processing.Ldmos transistor is as Aero-Space, power electronics and field of wireless communication
Particularly important device, the requirement to key parameter indexs such as its bandwidth, delivery efficiency, running voltages improves constantly.Mesh
The main substrate that front ldmos transistor uses is P-type silicon epitaxial wafer, and this is owing to silicon epitaxial wafer has lower impurity and defect
Content, higher uniformity.By the physical characteristic that it is many, the LDMOS device frequency range based on silicon epitaxial wafer is wide,
Noise coefficient is low, gain amplifier and output high, and since the sixties in last century, silicon epitaxial wafer is all the time as semi-conducting material
Exploitation, the emphasis developed, specification not only promotes.
Silicon epitaxial wafer has particularly important impact to ldmos transistor, evaluates its performance and mainly includes three parameters: thick
Degree, resistivity and crystal defect.Wherein the uniformity of epitaxial thickness, resistivity uniformity to the pressure voltage of device, electric conduction
The stability of resistance plays highly important impact, common demands inhomogeneities < 1.5%.And crystal defect includes road plan, mist, sliding
Line, fault, dislocation, contamination etc., directly affect the performances such as the cut-off frequency of LDMOS device, leakage current.Additionally, epitaxial layer and lining
The transition region diffuseed to form should be the most precipitous at the end, width of transition zone common demands < the 15% of epitaxy layer thickness, if transition region
Width is wide, it will reduce the effective thickness of whole epitaxial layer, and then reduces the breakdown voltage of device, has had a strong impact on device
Performance.Owing to p-type epitaxial layer uses borine as adulterant, boron atomic radius is little, light weight, and same P, As, Sb etc. compare,
In flowing gas, relative diffusion distance is bigger, it is easier to arrives the surface of reaction chamber wall, graphite base etc., and is inhaled in a large number
Attached, so autodoping effect is serious, it is bigger that resistivity evenness compares N-type epitaxial material control difficulty with width of transition zone.Root
Require that the numerical value of silicon epitaxy layer resistivity is suitable with the numerical value of thickness according to the technology of LDMOS device, i.e. epilayer resistance rate is higher
And thinner thickness, therefore the control to auto-dope proposes requirements at the higher level, causes the resistance of domestic ldmos transistor epitaxial wafer
Rate uniformity and transition region pattern with abroad have bigger gap, < 3%, width of transition zone is between epitaxy layer thickness for universal inhomogeneities
15% ~ 20%, still can not fully meet device manufacturer demand.
Summary of the invention
It is an object of the invention to overcome resistivity evenness and the control of width of transition zone present in existing p-type epitaxy technique
Problem processed, passes through process optimization, it is thus achieved that the preparation method of a kind of ldmos transistor silicon epitaxial wafer, significantly improves epitaxial wafer
The uniformity of resistance parameter, improve the structure of transition region simultaneously, reduce the probability of happening of crystal defect, thus not only
Meet the use requirement of LDMOS device, it is also possible to be greatly improved yield and the performance level of prepared device.
The present invention for achieving the above object, is achieved by following technical solution: a kind of ldmos transistor silicon epitaxy
The preparation method of sheet, it is characterised in that: step is as follows,
The first step: extension furnace foundation seat is at high temperature corroded by the HCl first with purity >=99.99%, that removes on pedestal is residual
Remaining deposited material, temperature is set as 1120 ~ 1150 DEG C, and HCl gas flow is set as that 1 ~ 3 L/min, HCl etch period are set as
3~5 min；Pedestal covers after having etched last layer non-impurity-doped polysilicon immediately again, and growth raw material is SiHCl3, flow
Being set as 14 ~ 16 g/min, the time is set as 10 ~ 12 min；
Second step: loading silicon monocrystalline substrate sheet in epitaxial furnace tub base pieces is cheated, silicon chip main reference plane down, utilizes pure successively
Spending nitrogen all >=99.999% and hydrogen purge epitaxial furnace, gas flow is set as 100 ~ 150 L/min, cavity purge time
It is 10 ~ 12 min；
3rd step: the surface of silicon substrate film is carried out HCl polishing, it is thus achieved that good lattice quality, HCl flow set is 1 ~ 3 L/
Min, temperature is set as 1150 ~ 1170 DEG C, and the time is set as 3 ~ 5 min；
4th step: at one layer of intrinsic epitaxial layer of grown above silicon, plays self-enclosed effect to silicon chip surface, stops substrate impurity
Volatilize further out, inhibition of self-doped effect, then carry out the growth of the doped epitaxial layer of LDMOS device needs, serve as a contrast at silicon
Basal surface grows undoped silicon intrinsic epitaxial layer, uses SiHCl3For growth raw material, flow set is 14 ~ 16 g/min, raw
Being set as 1 ~ 1.5 min for a long time, growth temperature is set as 1150 ~ 1160oC；
5th step: utilize HCl gas to be skimmed by the part that auto-dope is serious by epitaxial surface, polishing gas HCl flow set is 3
~ 5 L/min, the time is set as 10 ~ 12 min, and growth temperature is set as 1150 ~ 1160oC；
6th step: carry out alternating temperature variable-flow purge, constantly dilutes impurity and discharges extension cavity, and method is, by extension
Cavity temperature improves 100 ~ 120oC, using hydrogen flowing quantity is 300 ~ 350 L/min, the rising transition time 1 ~ 2 of hydrogen flowing quantity
Min, purge time when gas is stablized is 8 ~ 10 min；Then temperature is reduced by 100 ~ 120oC, hydrogen flowing quantity is set as 100 ~
150 L/min, decline min transit time 1 ~ 2 of hydrogen flowing quantity, purge time when gas is stablized is 8 ~ 10 min, once becomes
The overall process of temperature variable-flow purging is complete, altogether needs to carry out 3 ~ 4 alternating temperature variable-flow processes, to eliminate auto-dope factor, thus
Obtain more preferable transition region pattern and resistivity evenness；
7th step: be doped the growth of epitaxial layer, growth temperature is set as 1150 ~ 1160 DEG C, carries gaseous state with hydrogen
SiHCl3Entering reaction chamber with borane doping agent, hydrogen flowing quantity controls at 290 ~ 300 L/min, growth raw material SiHCl3Flow
Being set as that 25 ~ 28g/min, borine flow set are 102 ~ 105 sccm, the growth time of doped epitaxial layer is set as 4.0 ~ 4.5
Min, it is 3 ~ 4 r/min that epitaxial furnace obtains pedestal speed setting, and the height that pedestal is taken over a business simultaneously is set as that 45 ~ 55mm, epitaxial furnace set
The connected mode of standby heat induced coil serve as theme circle 1# binding post and 3# binding post phase short circuit, the 1# of secondary coil connects simultaneously
Terminal all keeps short circuit to 8# binding post, contributes to extension pedestal and obtains the field distribution of uniform temperature；
8th step: doped epitaxial layer growth starts cooling after reaching the scheduled time, hydrogen and nitrogen flow are set as 290 ~ 310
L/min, purging epitaxial furnace reaction chamber 10 ~ 12 min, then takes out epitaxial wafer from pedestal successively；
9th step: utilize Fourier infrared spectrograph equipment that the thickness of epitaxial wafer is measured, test pattern choosing in arranging
Selecting standard epitaxial reflection interference method, slice, thin piece size Selection " 100 ~ 150 mm ", infrared spectrum is arranged at the scanning times of each point
For " 2 ~ 4 times ", the scanning resolution " 2.0 ~ 4.0cm of infrared spectrum-1", records center point, four, upper and lower, left and right are away from edge 10
The position of mm, the altogether thickness of five test points, utilize mercury probe CV method of testing to measure the resistivity of silicon epitaxial wafer, its
In prefabricated voltage be set to 0 ~ 10V, before test, probe stationary set of time is 0 ~ 7000msec, and test starting voltage is set to-3
~-5V, test end voltage is set to-8 ~-20V, and sample frequency is set to 1500 ~ 5000mv/sec, compensates electric capacity and is set to
1.0 ~ 1.2pF, hydrargyrum contact area is set to 0.02 ~ 0.022cm2, records center point, four, upper and lower, left and right are away from edge 10 mm
Position, the resistivity of five test points altogether, utilize Spreading resistance method measure epitaxial wafer transition region structure；
Epitaxial furnace used is PE2061S type normal pressure cylinder epitaxial furnace.
The invention has the beneficial effects as follows, achieve the control to p-type epitaxial layer auto-dope factor by epitaxy technique optimization,
Improve epitaxial wafer thickness and resistivity evenness level, < 1.5%, the generation simultaneously reducing crystal defect is general for inhomogeneities
Rate, shortens the width of transition region, and surface is wanted without the defects such as fault, dislocation, skid wire, mist, the use meeting LDMOS device
Ask.
Accompanying drawing explanation
The thickness distribution schematic diagram of Fig. 1 embodiment of the present invention 1；
The resistivity distribution schematic diagram of Fig. 2 embodiment of the present invention 1；
Transition region shape appearance figure between substrate and the epitaxial layer of Fig. 3 embodiment of the present invention 1；
The thickness distribution schematic diagram of Fig. 4 embodiment of the present invention 2；
The resistivity distribution schematic diagram of Fig. 5 embodiment of the present invention 2；
Fig. 6 is the transition region shape appearance figure between substrate and the epitaxial layer of the embodiment of the present invention 2；
The thickness distribution schematic diagram of Fig. 7 embodiment of the present invention 3；
The resistivity distribution schematic diagram of Fig. 8 embodiment of the present invention 3；
Fig. 9 is the transition region shape appearance figure between substrate and the epitaxial layer of the embodiment of the present invention 3.
Detailed description of the invention
Below in conjunction with accompanying drawing, the detailed description of the invention of the present invention is described in detail:
Equipment used by the present invention is PE2061S type epitaxial furnace, and epitaxial furnace pedestal rotating speed controls at 3r/min, the height that pedestal is taken over a business
Degree is set as 45 ~ 50 mm, uses high purity graphite tub pedestal as high-frequency induction heating body.The heat induced of epitaxial furnace equipment
The connected mode of coil serve as theme circle 1# binding post and 3# binding post phase short circuit, the 1# binding post of secondary coil is to 8# wiring simultaneously
Post all keeps short circuit.
Embodiment 1
The first step: extension furnace foundation seat is at high temperature corroded by the HCl gas first with purity >=99.99%, removes base completely
Residual deposits material on seat, temperature is set as 1150 DEG C, and HCl gas flow is set as 3 L/min, and HCl etch period sets
Being 5 min, immediately to the pedestal again undoped polysilicon of bag last layer after having etched, growth raw material is SiHCl3Gas,
Flow set is 15g/min, and the bag silicon time is set as 10min.
Second step: load P-type silicon single crystal substrate slice in epitaxial furnace tub base pieces is cheated, utilize successively purity all >=
The nitrogen of 99.999% and hydrogen purge epitaxial furnace cavity 10min, gas flow is set as 300 L/min.
3rd step: utilizing HCl gas that silicon substrate film carries out surface finish, HCl flow set is 3 L/min, reaction temperature
Degree is set as 1160 DEG C, and polishing time is set as 3 min.
4th step: at one layer of intrinsic epitaxial layer of grown above silicon, plays self-enclosed effect to silicon chip surface, stops substrate miscellaneous
The volatilization further out of matter, inhibition of self-doped effect, then carry out the growth of the doped epitaxial layer of LDMOS device needs, adopt
Use SiHCl3For growth raw material, flow set is 15 g/min, and growth time is set as 1.2 min, and growth temperature is set as
1150oC。
5th step: utilize HCl gas to be skimmed by the part that auto-dope is serious by epitaxial surface, polishing gas HCl flow sets
Being set to 5 L/min, the time is set as 11 min, and growth temperature is set as 1150oC。
6th step: carry out alternating temperature variable-flow purge, constantly dilutes impurity and discharges extension cavity, and method is will outward
Prolong cavity temperature and improve 100oC, using hydrogen flowing quantity is 350 L/min, and the rising transition time 1min of hydrogen flowing quantity, gas is steady
The purge time of timing is 10 min, then temperature is reduced by 100oC, hydrogen flowing quantity is set as 100L/min, hydrogen flowing quantity
Declining min transit time 1, purge time when gas is stablized is 8 min, and this is the overall process of an alternating temperature variable-flow purging,
Altogether need to carry out 4 alternating temperature variable-flow processes, to eliminate as much as auto-dope factor.
7th step: carry out the growth of required doped epitaxial layer under the atmospheric pressure environment of 0.1MPa, growth temperature is set as
1150 DEG C, carry gaseous state SiHCl with hydrogen3Entering reaction chamber with borane doping agent, hydrogen flowing quantity controls at 290 L/min,
Growth raw material SiHCl3Flow set is 25g/min, and borine flow set is 104 sccm, and the growth time of epitaxial layer is set as
4.5 min。
8th step: outer layer growth starts cooling after reaching the scheduled time, hydrogen and nitrogen flow are set as 300 L/
Min, purging epitaxial furnace reaction chamber 10 min, then takes out epitaxial wafer from pedestal successively.
9th step: utilize Fourier infrared spectrograph equipment to measure the thickness of epitaxial wafer, tests mould in arranging
Formula selects standard epitaxial reflection interference method (Standard EPI-Interferogram subtract), slice, thin piece size Selection
" 150 mm ", infrared spectrum is set to " 2 times " at the scanning times of each point, the scanning resolution " 4.0cm of infrared spectrum-1",
Records center point, the position away from edge 10 mm, four, the upper and lower, left and right, the thickness of five test points altogether, central point thickness is
10.234 μm, four, the upper and lower, left and right position thickness away from edge 10 mm is followed successively by 10.092,10.375,10.268,
10.276 μm, utilize mercury probe CV method of testing to measure the resistivity of silicon epitaxial wafer, and the most prefabricated voltage is set to 10V,
Before test, probe stationary set of time is 3500msec, and test starting voltage is set to-5V, test end voltage is set to-
20V, sample frequency is set to 1500mv/sec, compensates electric capacity and is set to 1.2pF, and hydrargyrum contact area is set to 0.021cm2, note
Record central point, the position away from edge 10 mm, four, the upper and lower, left and right, the resistivity of five test points altogether, central point resistivity
Be 11.368 cm, four, the upper and lower, left and right position resistivity away from edge 10 mm is followed successively by 11.028,11.462,
11.355,11.387 cm, utilizes SRP 2000 Spreading resistance instrument, it is thus achieved that the width of silicon epitaxial wafer transition region.
The conduction type of the silicon epitaxy layer that embodiment 1 prepares is p-type, epitaxial wafer surface-brightening, without road plan, fault, dislocation,
The surface defects such as skid wire, mist, Pericarpium Citri tangerinae, contamination, thickness average value is 10.25 μm, and thickness offset is 0.99%, resistivity
Meansigma methods is 11.32 cm, and resistivity inhomogeneities is 1.48%, and width of transition zone is 1.3 m, and width is put down less than epitaxial layer
All the 15% of thickness, meets the use requirement of LDMOS device, thickness and resistivity measurement result institute as shown in Figure 1, Figure 2 from parameter
Showing, transition region test result is as shown in Figure 3.
Embodiment 2
The first step: extension furnace foundation seat is at high temperature corroded by the HCl gas first with purity >=99.99%, removes on pedestal
Residual deposits material, temperature is set as 1130 DEG C, and HCl gas flow is set as that 3 L/min, HCl etch period are set as 3
Min, immediately to the pedestal again undoped polysilicon of bag last layer after having etched, growth raw material is SiHCl3Gas, flow
It is set as that 14g/min, bag silicon time are set as 10min.
Second step: load P-type silicon single crystal substrate slice in epitaxial furnace tub base pieces is cheated, utilize successively purity all >=
The nitrogen of 99.999% and hydrogen purge epitaxial furnace cavity 12 min, gas flow is set as 290 L/min.
3rd step: utilize HCl gas to be polished silicon substrate film surface, HCl flow set is 1 L/min, reaction temperature
Degree is set as 1150 DEG C, and polishing time is set as 5 min.
4th step: at one layer of intrinsic epitaxial layer of grown above silicon, plays self-enclosed effect to silicon chip surface, stops substrate miscellaneous
The volatilization further out of matter, inhibition of self-doped effect, then carry out the growth of the doped epitaxial layer of LDMOS device needs, adopt
Use SiHCl3For growth raw material, flow set is 15 g/min, and growth time is set as 1 min, and growth temperature is set as
1150oC。
5th step: utilize HCl gas to be skimmed by the part that auto-dope is serious by epitaxial surface, polishing gas HCl flow sets
Being set to 5 L/min, the time is set as 11 min, and growth temperature is set as 1150oC。
6th step: carry out alternating temperature variable-flow purge, constantly dilutes impurity and discharges extension cavity, and method is will outward
Prolong cavity temperature and improve 120oC, using hydrogen flowing quantity is 350 L/min, and the rising transition time 1min of hydrogen flowing quantity, gas is steady
The purge time of timing is 8 min, then temperature is reduced by 120oC, hydrogen flowing quantity is set as 100L/min, under hydrogen flowing quantity
Fall min transit time 1, purge time when gas is stablized is 8 min, and this is the overall process of an alternating temperature variable-flow purging, always
4 these alternating temperature variable-flow processes need to be carried out altogether, to eliminate as much as auto-dope factor.
7th step: carry out the growth of required doped epitaxial layer under the atmospheric pressure environment of 0.1MPa, growth temperature is set as
1150 DEG C, carry gaseous state SiHCl with hydrogen3Entering reaction chamber with borane doping agent, hydrogen flowing quantity controls at 290 L/min,
Growth raw material SiHCl3Flow set is 25g/min, and borine flow set is 104 sccm, and the growth time of epitaxial layer is set as
4.5 min。
8th step: outer layer growth starts cooling after reaching the scheduled time, hydrogen and nitrogen flow are set as 300 L/
Min, purging epitaxial furnace reaction chamber 10 min, then takes out epitaxial wafer from pedestal successively.
9th step: utilize Fourier infrared spectrograph equipment to measure the thickness of epitaxial wafer, tests mould in arranging
Formula selects standard epitaxial reflection interference method (Standard EPI-Interferogram subtract), slice, thin piece size Selection
" 150 mm ", infrared spectrum is set to " 2 times " at the scanning times of each point, the scanning resolution " 2.0cm of infrared spectrum-1",
Records center point, the position away from edge 10 mm, four, the upper and lower, left and right, the thickness of five test points altogether, central point thickness is
10.015 μm, four, the upper and lower, left and right position thickness away from edge 10 mm is followed successively by 9.987,10.195,10.024,10.032
μm, utilizes mercury probe CV method of testing to measure the resistivity of silicon epitaxial wafer, and the most prefabricated voltage is set to 0V, visits before test
Head is set to 4000msec stabilization time, and test starting voltage is set to-5V, and test end voltage is set to-20V, sampling frequency
Rate is set to 2000mv/sec, compensates electric capacity and is set to 1.0pF, and hydrargyrum contact area is set to 0.021cm2, records center point,
The position away from edge 10 mm, four, the upper and lower, left and right, the resistivity of five test points altogether, central point resistivity is 11.284
Cm, four, the upper and lower, left and right position resistivity away from edge 10 mm is followed successively by 10.987,11.413,11.283,11.32
Cm, utilizes SRP 2000 Spreading resistance instrument, it is thus achieved that the width of transition zone of silicon epitaxial wafer.
The conduction type of the silicon epitaxy layer that embodiment 2 prepares is p-type, epitaxial wafer surface-brightening, without road plan, fault, dislocation,
The surface defects such as skid wire, mist, Pericarpium Citri tangerinae, contamination, thickness average value is 10.05 μm, and thickness offset is 0.82%, resistivity
Meansigma methods is 11.26 cm, and resistivity inhomogeneities is 1.43%, and width of transition zone is 1.1 m, and width is average less than epitaxial layer
The 15% of thickness, meets the use requirement of LDMOS device, thickness and resistivity measurement result as shown in Figure 4, Figure 5 from parameter,
Transition region test result is as shown in Figure 6.
Embodiment 3
The first step: extension furnace foundation seat is at high temperature corroded by the HCl gas first with purity >=99.99%, removes on pedestal
Residual deposits material, temperature is set as 1150 DEG C, and HCl gas flow is set as that 1 L/min, HCl etch period are set as 5
Min, immediately to the pedestal again undoped polysilicon of bag last layer after having etched, growth raw material is SiHCl3Gas, flow
It is set as that 16g/min, bag silicon time are set as 10min.
Second step: load P-type silicon single crystal substrate slice in epitaxial furnace tub base pieces is cheated, utilize successively purity all >=
The nitrogen of 99.999% and hydrogen purge epitaxial furnace cavity 10 min, gas flow is set as 310 L/min.
3rd step: utilize HCl gas to be polished silicon substrate film surface, HCl flow set is 1 L/min, reaction temperature
Degree is set as 1150 DEG C, and polishing time is set as 3 min.
4th step: at one layer of intrinsic epitaxial layer of grown above silicon, plays self-enclosed effect to silicon chip surface, stops substrate miscellaneous
The volatilization further out of matter, inhibition of self-doped effect, then carry out the growth of the doped epitaxial layer of LDMOS device needs, adopt
Use SiHCl3For growth raw material, flow set is 15 g/min, and growth time is set as 1.5 min, and growth temperature is set as
1150oC。
5th step: utilize HCl gas to be skimmed by the part that auto-dope is serious by epitaxial surface, polishing gas HCl flow sets
Being set to 3 L/min, the time is set as 11 min, and growth temperature is set as 1150oC。
6th step: carry out alternating temperature variable-flow purge, constantly dilutes impurity and discharges extension cavity, and method is will outward
Prolong cavity temperature and improve 100oC, using hydrogen flowing quantity is 350 L/min, and the rising transition time 1min of hydrogen flowing quantity, gas is steady
The purge time of timing is 8 min, then temperature is reduced by 100oC, hydrogen flowing quantity is set as 100L/min, under hydrogen flowing quantity
Fall min transit time 1, purge time when gas is stablized is 8 min, and this is the overall process of an alternating temperature variable-flow purging, always
3 alternating temperature variable-flow processes need to be carried out altogether, eliminate as much as auto-dope factor.
7th step: carry out the growth of required doped epitaxial layer under the atmospheric pressure environment of 0.1MPa, growth temperature is set as
1150 DEG C, carry gaseous state SiHCl with hydrogen3Entering reaction chamber with borane doping agent, hydrogen flowing quantity controls at 290 L/min,
Growth raw material SiHCl3Flow set is 25g/min, and borine flow set is 104 sccm, and the growth time of epitaxial layer is set as
4.5 min。
8th step: outer layer growth starts cooling after reaching the scheduled time, hydrogen and nitrogen flow are set as 300 L/
Min, purging epitaxial furnace reaction chamber 10 min, then takes out epitaxial wafer from pedestal successively.
9th step: utilize Fourier infrared spectrograph equipment to measure the thickness of epitaxial wafer, tests mould in arranging
Formula selects standard epitaxial reflection interference method (Standard EPI-Interferogram subtract), slice, thin piece size Selection
" 150 mm ", infrared spectrum is set to " 2 times " at the scanning times of each point, the scanning resolution " 3.0cm of infrared spectrum-1",
Records center point, the position away from edge 10 mm, four, the upper and lower, left and right, the thickness of five test points altogether, central point thickness is
10.362 μm, four, the upper and lower, left and right position thickness away from edge 10 mm is followed successively by 10.213,10.432,10.382,
10.395 μm, utilize mercury probe CV method of testing to measure the resistivity of silicon epitaxial wafer, and the most prefabricated voltage is set to 5V, survey
Before examination, probe stationary set of time is 2000msec, and test starting voltage is set to-5V, and test end voltage is set to-20V,
Sample frequency is set to 3000mv/sec, compensates electric capacity and is set to 1.1pF, and hydrargyrum contact area is set to 0.020cm2, in record
Heart point, the position away from edge 10 mm, four, the upper and lower, left and right, the resistivity of five test points altogether, central point resistivity is
11.432 cm, four, the upper and lower, left and right position resistivity away from edge 10 mm is followed successively by 11.174,11.573,11.362,
11.391 cm, utilize SRP 2000 Spreading resistance instrument, it is thus achieved that the width of transition zone of silicon epitaxial wafer.
The conduction type of the silicon epitaxy layer that embodiment 3 prepares is p-type, epitaxial wafer surface-brightening, without road plan, fault, dislocation,
The surface defects such as skid wire, mist, Pericarpium Citri tangerinae, contamination, thickness average value is 10.36 μm, and thickness offset is 0.81%, resistivity
Meansigma methods is 11.39 cm, and resistivity inhomogeneities is 1.26%, and width of transition zone is 1.0 m, and width is average less than epitaxial layer
The 15% of thickness, meets the use requirement of LDMOS device, thickness and resistivity measurement result as shown in Figure 7, Figure 8 from parameter,
Transition region test result is as shown in Figure 9.
Extension uniformity compared with embodiment 1, embodiment 2, under its corresponding process conditions, obtained by embodiment 3
And width of transition zone index is optimum.Therefore, embodiment 3 is highly preferred embodiment of the present invention.
Obviously, those skilled in the art the preparation method of the present invention can be carried out various change and modification without deviating from
The spirit and scope of the present invention.So, if to the present invention these amendment and modification belong to the claims in the present invention and etc.
Within the scope of technology, then the present invention is also intended to comprise these change and modification.
Claims (1)
1. the preparation method of a ldmos transistor silicon epitaxial wafer, it is characterised in that: step is as follows,
The first step: extension furnace foundation seat is at high temperature corroded by the HCl first with purity >=99.99%, that removes on pedestal is residual
Remaining deposited material, temperature is set as 1120 ~ 1150 DEG C, and HCl gas flow is set as that 1 ~ 3 L/min, HCl etch period are set as
3~5 min；Pedestal covers after having etched last layer non-impurity-doped polysilicon immediately again, and growth raw material is SiHCl3, flow
Being set as 14 ~ 16 g/min, the time is set as 10 ~ 12 min；
Second step: loading silicon monocrystalline substrate sheet in epitaxial furnace tub base pieces is cheated, silicon chip main reference plane down, utilizes pure successively
Spending nitrogen all >=99.999% and hydrogen purge epitaxial furnace, gas flow is set as 100 ~ 150 L/min, cavity purge time
It is 10 ~ 12 min；
3rd step: the surface of silicon substrate film is carried out HCl polishing, it is thus achieved that good lattice quality, HCl flow set is 1 ~ 3 L/
Min, temperature is set as 1150 ~ 1170 DEG C, and the time is set as 3 ~ 5 min；
4th step: at one layer of intrinsic epitaxial layer of grown above silicon, plays self-enclosed effect to silicon chip surface, stops substrate impurity
Volatilize further out, inhibition of self-doped effect, then carry out the growth of the doped epitaxial layer of LDMOS device needs, serve as a contrast at silicon
Basal surface grows undoped silicon intrinsic epitaxial layer, uses SiHCl3For growth raw material, flow set is 14 ~ 16 g/min, raw
Being set as 1 ~ 1.5 min for a long time, growth temperature is set as 1150 ~ 1160oC；
5th step: utilize HCl gas to be skimmed by the part that auto-dope is serious by epitaxial surface, polishing gas HCl flow set is 3
~ 5 L/min, the time is set as 10 ~ 12 min, and growth temperature is set as 1150 ~ 1160oC；
6th step: carry out alternating temperature variable-flow purge, constantly dilutes impurity and discharges extension cavity, and method is, by extension
Cavity temperature improves 100 ~ 120oC, using hydrogen flowing quantity is 300 ~ 350 L/min, the rising transition time 1 ~ 2 of hydrogen flowing quantity
Min, purge time when gas is stablized is 8 ~ 10 min；Then temperature is reduced by 100 ~ 120oC, hydrogen flowing quantity is set as 100 ~
150 L/min, decline min transit time 1 ~ 2 of hydrogen flowing quantity, purge time when gas is stablized is 8 ~ 10 min, once becomes
The overall process of temperature variable-flow purging is complete, altogether needs to carry out 3 ~ 4 alternating temperature variable-flow processes, to eliminate auto-dope factor, thus
Obtain more preferable transition region pattern and resistivity evenness；
7th step: be doped the growth of epitaxial layer, growth temperature is set as 1150 ~ 1160 DEG C, carries gaseous state SiHCl with hydrogen3
Entering reaction chamber with borane doping agent, hydrogen flowing quantity controls at 290 ~ 300 L/min, growth raw material SiHCl3Flow set is
25 ~ 28g/min, borine flow set is 102 ~ 105 sccm, and the growth time of doped epitaxial layer is set as 4.0 ~ 4.5 min,
It is 3 ~ 4 r/min that epitaxial furnace obtains pedestal speed setting, and the height that pedestal is taken over a business simultaneously is set as 45 ~ 55mm, epitaxial furnace equipment
The connected mode of heat induced coil serve as theme circle 1# binding post and 3# binding post phase short circuit, simultaneously the 1# binding post of secondary coil
All keep short circuit to 8# binding post, contribute to extension pedestal and obtain the field distribution of uniform temperature；
8th step: doped epitaxial layer growth starts cooling after reaching the scheduled time, hydrogen and nitrogen flow are set as 290 ~ 310
L/min, purging epitaxial furnace reaction chamber 10 ~ 12 min, then takes out epitaxial wafer from pedestal successively；
9th step: utilize Fourier infrared spectrograph equipment that the thickness of epitaxial wafer is measured, test pattern choosing in arranging
Selecting standard epitaxial reflection interference method, slice, thin piece size Selection " 100 ~ 150 mm ", infrared spectrum is arranged at the scanning times of each point
For " 2 ~ 4 times ", the scanning resolution " 2.0 ~ 4.0cm of infrared spectrum-1", records center point, four, upper and lower, left and right are away from edge 10
The position of mm, the altogether thickness of five test points, utilize mercury probe CV method of testing to measure the resistivity of silicon epitaxial wafer, its
In prefabricated voltage be set to 0 ~ 10V, before test, probe stationary set of time is 0 ~ 7000msec, and test starting voltage is set to-3
~-5V, test end voltage is set to-8 ~-20V, and sample frequency is set to 1500 ~ 5000mv/sec, compensates electric capacity and is set to
1.0 ~ 1.2pF, hydrargyrum contact area is set to 0.02 ~ 0.022cm2, records center point, four, upper and lower, left and right are away from edge 10 mm
Position, the resistivity of five test points altogether, utilize Spreading resistance method measure epitaxial wafer transition region structure；
Epitaxial furnace used is PE2061S type normal pressure cylinder epitaxial furnace.
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Effective date of registration: 20210425 Address after: 300220 No. 26 Dongting Road, Tianjin, Hexi District Patentee after: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.46 Research Institute Patentee after: CLP Jinghua (Tianjin) semiconductor materials Co.,Ltd. Address before: 300220 No. 26 Dongting Road, Tianjin, Hexi District Patentee before: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.46 Research Institute |
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