CN115537922B - Method for reducing self-doping of epitaxial wafer - Google Patents
Method for reducing self-doping of epitaxial wafer Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000007789 gas Substances 0.000 claims abstract description 44
- 239000001257 hydrogen Substances 0.000 claims abstract description 36
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 36
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims abstract description 8
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000010926 purge Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000006243 chemical reaction Methods 0.000 claims description 31
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 25
- 239000005052 trichlorosilane Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 239000005922 Phosphane Substances 0.000 claims description 9
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 9
- 229910000064 phosphane Inorganic materials 0.000 claims description 9
- 238000001816 cooling Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000012546 transfer Methods 0.000 abstract description 3
- 239000007790 solid phase Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 50
- 238000012360 testing method Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010835 comparative analysis Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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Abstract
The invention discloses a method for reducing self-doping of an epitaxial wafer. According to the method, on the premise of ensuring low-flow hydrogen chloride gas etching and high-temperature baking, two layers of intrinsic materials are sequentially designed and grown on a substrate, so that the resistivity non-uniformity of an epitaxial wafer is reduced from more than 5% to less than 1%, and the use requirement of a product is met. The method comprises the steps of setting the growth time of a first layer to be 80 seconds, setting the growth time of a second layer to be 60 seconds, setting the hydrogen purging time at an intermediate interval to be 3-10 minutes, and setting the rotating speed of a base to be 30 r/min; the double-intrinsic layer is developed to inhibit the self-doping effect of the substrate, a double-layer structure is established to inhibit the volatilization and solid phase transfer of impurity elements in the substrate through the growth of the double-intrinsic layer, the doping of the impurity elements is reduced, the growth environment of the subsequent epitaxial layer is more ideal, a remarkably better electrical result can be obtained, and the outstanding beneficial effect that the resistivity nonuniformity is lower than 1% is achieved.
Description
Technical Field
The invention relates to a preparation technology of a semiconductor material, in particular to a method for reducing self-doping of an epitaxial wafer.
Background
Epitaxy is one type of semiconductor process. In the bipolarar process, the bottom layer of the silicon wafer is P-type substrate silicon (with a buried layer), and then a layer of monocrystalline silicon, called an epitaxial layer, is grown on the substrate. The silicon epitaxy is to grow one or more layers of silicon single crystal films on a polished silicon single crystal wafer through gas phase chemical reaction at high temperature, epitaxial layers with different resistivities, different thicknesses and different types can be obtained by controlling growth conditions, the semiconductor silicon epitaxial wafer is applied to high-grade semiconductor devices with higher requirements on stability, defect density, high voltage, current tolerance and the like in a large scale, the semiconductor silicon epitaxial wafer mainly comprises power devices such as MOSFETs, transistors and the like, analog devices such as CIS, PMIC and the like, the terminal application comprises automobile and high-end equipment manufacturing, energy management, communication, consumer electronics and the like, and the product use requirement on the epitaxial wafer with the resistivity of 27-29 omega cm is less than 1%.
Chinese patent ZL202010341314.3 discloses a preparation method of a silicon epitaxial wafer for a Schottky device, however, aiming at the product, the self-doping effect is obvious due to volatilization and transfer of heavily doped boron at the growth temperature of 1115-1125 ℃, and the resistivity of the epitaxial wafer of 27-29 omega cm is difficult to stabilize in the actual production process. The method of the Chinese patent ZL20110320451. X reduces the self-doping in the epitaxial layer growth process by adopting a high-temperature baking and low-temperature variable-speed air-expelling method, however, the method is adopted to carry out the production test, and the non-uniformity of the resistivity of 27-29 Ω & cm can only be reduced to about 5%.
At present, the preparation of the silicon epitaxial wafer is developed from low resistivity to high resistivity and low thickness to high thickness, the size of the epitaxial wafer is gradually increased, and the resistivity non-uniformity caused by self doping is higher than 5%, so that the requirement of the subsequent process is difficult to meet. Therefore, technical innovation is urgently required to meet the use requirement that the resistivity of the epitaxial wafer is not uniform by less than 1%.
Disclosure of Invention
In order to solve the problem that in the prior art, the resistivity non-uniformity of an epitaxial wafer is always higher than 5% due to self-doping of a substrate at a high temperature, so that the product use requirement is difficult to meet, the invention provides a method for reducing the self-doping of the epitaxial wafer.
The technical scheme adopted by the invention is as follows: the method for reducing the self-doping of the epitaxial wafer comprises the following steps:
s1, introducing hydrogen chloride gas into the reaction chamber of the epitaxial furnace, setting the gas flow to be 10-20L/min, and etching the residual deposition substances on the substrate and the chamber in the reaction chamber of the epitaxial furnace at the high temperature of 1140-1160 ℃ for 110-130 seconds.
S2, setting the flow of hydrogen to be 60-80L/min in the silicon packaging process, enabling the trichlorosilane which is wrapped with gas by a bubbler to jointly enter the reaction chamber of the epitaxial furnace, setting the flow of the trichlorosilane to be 8-12L/min, and enabling the silicon packaging time on the base to be 10-30 seconds.
And S3, placing the substrate into a reaction chamber base, heating to 1140-1160 ℃, baking the reaction chamber of the epitaxial furnace for 1-3 min, and then cooling to 1110-1130 ℃.
S4, purging the internal environment of the reaction chamber of the epitaxial furnace with hydrogen, wherein the hydrogen flow is set to be 60-70L/min, and the purging time is set to be 50-70 seconds.
S5, setting the flow rate of hydrogen to be 50-70L/min, wrapping trichlorosilane gas and entering the reaction chamber through a bubbler, and setting the flow rate of trichlorosilane to be 5-20L/min; and (3) introducing hydrogen into the lower part of the base, wherein the flow rate of the hydrogen is set to be 14-18L/min.
S6, two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to 80 seconds, the growth time of the second layer is set to 60 seconds, the hydrogen purging time at the middle interval is 3-10 minutes, and the rotating speed of the base is 30r/min.
S7, wrapping the hydrogen with doped phosphane gas to form a mixed gas, wherein the evacuation time of a doping pipeline is 40-80 seconds, the hydrogen flow is set to be 15-20L/min, the doped phosphane gas is set to be 40-60 ppm, and the proportion of the doped phosphane gas in the mixed gas is 10-30%.
And S8, setting the flow rate of hydrogen carrying trichlorosilane to be 40-80L/min in epitaxial layer growth, wrapping trichlorosilane gas and entering a reaction chamber through a bubbler, setting the flow rate of the trichlorosilane gas to be 5-20L/min, setting the flow rate of doping pipeline gas to be 40-60 sccm, setting the growth time to be 500-1500 seconds, and setting the rotating speed of a base to be 30r/min.
And S9, after the growth of the epitaxial layer is finished, the reaction chamber starts to be cooled to form an epitaxial wafer, and after the temperature is reduced to 300 ℃, the epitaxial wafer is taken out from the reaction chamber.
The substrate selects the heavily boron-doped substrate with the diameter of 150mm, and the resistivity of the heavily boron-doped substrate is lower than 0.004 ohm cm.
The epitaxial furnace used in the invention is a northern Hua Chuang 630 multi-piece epitaxial furnace.
The purity of the hydrogen chloride gas used in the invention is more than or equal to 99.99 percent, and the purity of the trichlorosilane gas is more than or equal to 99.95 percent.
The beneficial effects of the invention are as follows: on the premise of ensuring the etching of small-flow hydrogen chloride gas and the high-temperature baking, two layers of intrinsic materials are sequentially designed and grown on the substrate, so that the resistivity non-uniformity of the epitaxial wafer is reduced from more than 5% to less than 1%, and the use requirement of the product is met.
The invention adopts the development of the double intrinsic layers to inhibit the self-doping effect of the substrate, and is characterized in that a double-layer structure is established to inhibit the volatilization and solid phase transfer of impurity elements in the substrate by the growth of the double intrinsic layers, so that the doping of the impurity elements is reduced, the growth environment of the subsequent epitaxial layers is more ideal, obviously better electrical results can be obtained, and the outstanding beneficial effect that the resistivity nonuniformity is lower than 1 percent is obtained.
In the experimental process, the single-layer intrinsic, the double-layer intrinsic and the three-layer intrinsic are subjected to comparative analysis, so that the control performance of the double-layer intrinsic and the three-layer intrinsic on the resistivity non-uniformity is better than that of the single-layer intrinsic, and the resistivity non-uniformity of the double-layer intrinsic and the three-layer intrinsic is not greatly different; meanwhile, the double-layer intrinsic is more advantageous than the three-layer intrinsic in terms of economy and scheme control technical difficulty.
Drawings
FIG. 1 is a resistivity profile of example 1 of the present invention;
FIG. 2 is a resistivity profile of example 2 of the present invention;
FIG. 3 is a resistivity profile of example 3 of the present invention;
FIG. 4 is a resistivity profile of example 4 of the present invention;
FIG. 5 is a resistivity profile of example 5 of the present invention.
Description of the embodiments
The following describes in detail the embodiments of the present invention with reference to the drawings and examples.
The epitaxial furnace used in the invention is a northern Hua Chuang 630 multi-piece epitaxial furnace. The purity of the hydrogen chloride gas is more than or equal to 99.99 percent, and the purity of the trichlorosilane gas is more than or equal to 99.95 percent. And selecting a heavily boron-doped substrate with the diameter of 150mm, wherein the resistivity of the heavily boron-doped substrate is lower than 0.004 ohm cm.
The resistivity index of the epitaxial wafer is tested by adopting an MCV-530 resistivity measuring instrument, and a 5-point test method is adopted, wherein the 5-point test position is a center point with a main parameter facing upwards and four points which are 6mm away from the edge and are right above, below, left and right from the center point. The average value of the resistivity 5 points of the prepared silicon epitaxial layer is 27-29 omega cm.
Examples
(1) Hydrogen chloride gas is introduced into the reaction chamber of the epitaxial furnace, the gas flow is set to be 16L/min, and the residual deposition substances on the base and the chamber in the reaction chamber of the epitaxial furnace are etched for 120 seconds at the high temperature of 1150 ℃.
(2) In the process of silicon encapsulation, the flow rate of hydrogen is set to be 70L/min, the gaseous trichlorosilane wrapped and clamped by a bubbler jointly enters the reaction chamber of the epitaxial furnace, the flow rate of the trichlorosilane is set to be 10L/min, and the silicon encapsulation time on the base is set to be 20 seconds.
(3) And placing the substrate into a reaction chamber base, heating to 1150 ℃, baking the reaction chamber of the epitaxial furnace for 2min, and then cooling to 1120 ℃.
(4) The internal environment of the reaction chamber of the epitaxial furnace is purged by hydrogen, the hydrogen flow is set to 65L/min, and the purging time is 60 seconds.
(5) The flow rate of the hydrogen is set to be 60L/min, the trichlorosilane gas is wrapped and clamped by a bubbler and enters the reaction chamber together, the flow rate of the trichlorosilane is set to be 12L/min, the evacuation time of the trichlorosilane gas in a pipeline is 40 seconds, the hydrogen is introduced into the lower part of the base, and the flow rate of the hydrogen is set to be 16L/min.
(6) Two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to 40 seconds, the growth time of the second layer is set to 20 seconds, the hydrogen is purged for 5 minutes at intervals, and the rotating speed of the base is 30r/min.
(7) The hydrogen is wrapped with the mixed gas formed by doping the phosphane gas and is jointly introduced into the chamber, the hydrogen flow is set to be 18L/min, the doping phosphane gas is set to be 50ppm, the proportion of the doping phosphane gas in the mixed gas is 15%, and the emptying time of the doping pipeline is 60 seconds.
(8) In the epitaxial layer growth, the hydrogen flow carrying the trichlorosilane is set to be 60L/min, the trichlorosilane gas is wrapped and clamped by a bubbler and enters the reaction chamber of the epitaxial furnace together, the trichlorosilane gas flow is set to be 10L/min, the growth time is 960 seconds, the rotating speed of a base is 30r/min, and the gas flow of a doping pipeline is 50 sccm.
(9) And after the epitaxial layer grows, the reaction chamber starts to cool down to form a silicon epitaxial wafer, and after the temperature is lowered to 300 ℃, the epitaxial wafer is taken out from the reaction chamber.
The epitaxial layer obtained in example 1 has a resistivity distribution chart shown in FIG. 1, in which the 5-point position test values were 27.75Ω·cm,27.64Ω·cm,26.85Ω·cm,27.76 Ω·cm,27.85Ω·cm, and the calculated average value was 27.57 Ω·cm, and the unevenness was 1.48%.
Example 2:
in the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to be 50 seconds, the growth time of the second layer is set to be 30 seconds, the hydrogen is purged for 5 minutes at intervals, and the rotating speed of the base is 30r/min. Other steps and parameter settings are the same as those of embodiment 1, and a description thereof will not be repeated.
The resistivity profile of the silicon epitaxial layer obtained in example 2 was shown in FIG. 2, and the 5-point position test values were 27.63. Omega. Cm, 27.82. Omega. Cm, 26.95. Omega. Cm, 27.96. Omega. Cm, and 27.81. Omega. Cm, respectively, and the calculated average value was 27.63. Omega. Cm, and the unevenness was 1.44%.
Examples
In the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to 60 seconds, the growth time of the second layer is set to 40 seconds, the hydrogen is purged for 5 minutes at intervals, and the rotating speed of the base is 30r/min. Other steps and parameter settings are the same as those of embodiment 1, and a description thereof will not be repeated.
The resistivity distribution of the silicon epitaxial layer obtained in example 3 was shown in FIG. 3, and the 5-point position test values were 27.46. Omega. Cm, 27.9. Omega. Cm, 26.98. Omega. Cm, 27.88. Omega. Cm, and 27.56. Omega. Cm, respectively, and the calculated average value was 27.56. Omega. Cm, and the unevenness was 1.36%.
Examples
In the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to be 70 seconds, the growth time of the second layer is set to be 50 seconds, the hydrogen is purged for 5 minutes at intervals, and the rotating speed of the base is 30r/min. Other steps and parameter settings are the same as those of embodiment 1, and a description thereof will not be repeated.
The resistivity distribution of the silicon epitaxial layer obtained in example 4 was shown in FIG. 4, and the 5-point position test values were 27.59. Omega. Cm, 27.96. Omega. Cm, 26.99. Omega. Cm, 27.79. Omega. Cm, and 27.54. Omega. Cm, respectively, and the calculated average value was 27.57. Omega. Cm, and the unevenness was 1.33%.
Examples
In the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to 80 seconds, the growth time of the second layer is set to 60 seconds, the hydrogen is purged for 5 minutes at intervals, and the rotating speed of the base is 30r/min. Other steps and parameter settings are the same as those of embodiment 1, and a description thereof will not be repeated.
The resistivity profile of the silicon epitaxial layer obtained in example 5 is shown in FIG. 5, and the measured values at the 5-point position are 27.62. Omega. Cm, 27.85. Omega. Cm, 27.23. Omega. Cm, 27.73. Omega. Cm, and 27.57. Omega. Cm, respectively, and the calculated average value is 27.6. Omega. Cm, and the unevenness is 0.85%.
Compared with the example 1, the example 2, the example 3 and the example 4, the silicon epitaxial layer prepared in the example 5 has the optimal resistivity non-uniformity index under the corresponding process conditions. The respective growth times of the two layers continue to be increased, there is no further improvement in resistivity non-uniformity, and there is no economic advantage. Thus, example 5 is the preferred embodiment of the present invention.
Claims (1)
1. The method for reducing the self-doping of the epitaxial wafer is characterized by comprising the following steps of:
s1, introducing hydrogen chloride gas into a reaction chamber of an epitaxial furnace, setting the gas flow to be 10-20L/min, and etching a base in the reaction chamber of the epitaxial furnace and residual deposition substances on the chamber for 110-130 seconds at a high temperature of 1140-1160 ℃;
s2, setting the flow rate of hydrogen to be 60-80L/min in the silicon packaging process, enabling the hydrogen to be wrapped with gaseous trichlorosilane through a bubbler to enter an epitaxial furnace reaction chamber together, setting the flow rate of the trichlorosilane to be 8-12L/min, and enabling the silicon packaging time on the base to be 10-30 seconds;
s3, placing the substrate into a reaction chamber base, heating to 1140-1160 ℃, baking the reaction chamber of the epitaxial furnace for 1-3 min, and then cooling to 1110-1130 ℃;
s4, purging the internal environment of the reaction chamber of the epitaxial furnace with hydrogen, wherein the hydrogen flow is set to be 60-70L/min, and the purging time is 50-70 seconds;
s5, setting the flow rate of hydrogen to be 50-70L/min, wrapping trichlorosilane gas and entering the reaction chamber through a bubbler, and setting the flow rate of trichlorosilane to be 5-20L/min; introducing hydrogen into the lower part of the base, wherein the flow rate of the hydrogen is set to be 14-18L/min;
s6, two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to 80 seconds, the growth time of the second layer is set to 60 seconds, the hydrogen purging time at the middle interval is 3-10 minutes, and the rotating speed of the base is 30 r/min;
s7, wrapping the hydrogen with doped phosphane gas to form a mixed gas, wherein the evacuation time of a doping pipeline is 40-80 seconds, the hydrogen flow is set to be 15-20L/min, the doped phosphane gas is set to be 40-60 ppm, and the proportion of the doped phosphane gas in the mixed gas is 10-30%;
s8, setting the flow rate of hydrogen carrying trichlorosilane to be 40-80L/min in epitaxial layer growth, wrapping trichlorosilane gas and entering a reaction chamber through a bubbler, setting the flow rate of the trichlorosilane gas to be 5-20L/min, setting the flow rate of the doping pipeline gas to be 40-60 sccm, setting the growth time to be 500-1500 seconds, and setting the rotating speed of a base to be 30 r/min;
s9, after the growth of the epitaxial layer is finished, the reaction chamber starts to be cooled to form an epitaxial wafer, and after the temperature is reduced to 300 ℃, the epitaxial wafer is taken out from the reaction chamber;
the substrate is a heavily boron-doped substrate with the diameter of 150mm, and the resistivity of the heavily boron-doped substrate is lower than 0.004 ohm cm;
the used epitaxial furnace is a northern Hua Chuang 630 multi-piece epitaxial furnace;
the purity of the hydrogen chloride gas is more than or equal to 99.99 percent, and the purity of the trichlorosilane gas is more than or equal to 99.95 percent.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211502896.4A CN115537922B (en) | 2022-11-29 | 2022-11-29 | Method for reducing self-doping of epitaxial wafer |
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| CN202211502896.4A CN115537922B (en) | 2022-11-29 | 2022-11-29 | Method for reducing self-doping of epitaxial wafer |
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| CN115537922A CN115537922A (en) | 2022-12-30 |
| CN115537922B true CN115537922B (en) | 2024-01-09 |
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