CN115537922A - Method for reducing self-doping of epitaxial wafer - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000007789 gas Substances 0.000 claims abstract description 43
- 239000001257 hydrogen Substances 0.000 claims abstract description 34
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 34
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000010926 purge Methods 0.000 claims abstract description 14
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims abstract description 7
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims description 31
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 26
- 239000005052 trichlorosilane Substances 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 6
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 6
- 238000001816 cooling Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000012546 transfer Methods 0.000 abstract description 3
- 239000007790 solid phase Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 53
- 238000012360 testing method Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000005922 Phosphane Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000064 phosphane Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010835 comparative analysis Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- C30B25/02—Epitaxial-layer growth
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Abstract
The invention discloses a method for reducing self-doping of an epitaxial wafer. The method reduces the nonuniformity of the resistivity of the epitaxial wafer from more than 5% to within 1% by designing and growing two layers of intrinsic substances on the substrate in sequence on the premise of ensuring the etching of low-flow hydrogen chloride gas and high-temperature baking, thereby meeting the use requirements of products. Setting the growth time of a first layer to be 40 to 80 seconds, the growth time of a second layer to be 20 to 60 seconds, the intermediate interval hydrogen purging time to be 3 to 10 min, and the rotating speed of a base to be 30 r/min; the double intrinsic layers are developed to inhibit the autodoping effect of the substrate, the double-layer structure is established to inhibit volatilization and solid phase transfer of impurity elements in the substrate through growth of the double intrinsic layers, and doping of the impurity elements is reduced, so that the growth environment of a subsequent epitaxial layer is more ideal, a remarkably better electrical result can be obtained, and a remarkable beneficial effect that the nonuniformity of the resistivity is lower than 1% is obtained.
Description
Technical Field
The invention relates to a preparation technology of a semiconductor material, in particular to a method for reducing self-doping of an epitaxial wafer.
Background
Epitaxy is one of the semiconductor processes. In the bipolar process, the bottom layer of a silicon wafer is P-type substrate silicon (with a buried point layer), and then a layer of monocrystalline silicon called epitaxial layer is grown on the substrate. The silicon epitaxy is to grow one or more layers of silicon single crystal thin films on a polished silicon single crystal wafer through a gas phase chemical reaction at a high temperature, epitaxial layers with different resistivities, different thicknesses and different models can be obtained by controlling growth conditions, the semiconductor silicon epitaxy wafer is applied to high-grade semiconductor devices with higher requirements on stability, defect density, high voltage, current tolerance and the like in a large scale and mainly comprises power devices such as MOSFETs, transistors and the like and analog devices such as CIS, PMIC and the like, terminal applications comprise automobile, high-end equipment manufacturing, energy management, communication, consumer electronics and the like, and the nonuniformity of the resistivity of the epitaxial wafer with the resistivity of 27 to 29 omega cm is required to be less than 1 percent when the product is used.
Chinese patent ZL202010341314.3 discloses a preparation method of a silicon epitaxial wafer for a Schottky device, however, aiming at the product, under the growth temperature of 1115 to 1125 ℃, the self-doping effect is obvious due to volatilization and transfer of heavily doped boron, and the resistivity of the epitaxial wafer from 27 to 29 omega cm is difficult to stabilize in the actual production process. Chinese patent ZL201110320451.X reduces autodoping in the epitaxial layer growth process by adopting a high-temperature baking and low-temperature variable-speed gas driving method, but production tests carried out by adopting the method can only reduce the nonuniformity of the resistivity from 27 to 29 omega cm to about 5%.
At present, the preparation of the silicon epitaxial wafer is developed from low resistivity to high resistivity and low thickness to high thickness, the size of the epitaxial wafer is gradually increased, the nonuniformity of the resistivity caused by self-doping is higher than 5%, and the requirements of the subsequent process are difficult to meet. Therefore, technical innovation is urgently needed to meet the use requirement that the resistivity of the epitaxial wafer is not uniform and is less than 1%.
Disclosure of Invention
In order to solve the problem that the use requirement of a product is difficult to meet due to the fact that the resistivity nonuniformity of an epitaxial wafer is always higher than 5% caused by the self-doping of a substrate at high temperature in the prior art, the invention provides a method for reducing the self-doping of the epitaxial wafer.
The technical scheme adopted by the invention is as follows: a method for reducing the self-doping of an epitaxial wafer comprises the following steps:
s1, introducing hydrogen chloride gas into the reaction chamber of the epitaxial furnace, setting the gas flow rate to be 10-20L/min, and etching the base in the reaction chamber of the epitaxial furnace and residual deposited substances on the chamber at the high temperature of 1140-1160 ℃ for 110-130 seconds.
S2, in the silicon coating process, setting the flow of hydrogen to be 60-80L/min, wrapping gaseous trichlorosilane together through a bubbler, and allowing the gaseous trichlorosilane to enter a reaction chamber of the epitaxial furnace, setting the flow of the trichlorosilane to be 8-12L/min, and setting the silicon coating time on the base to be 10-30 seconds.
S3, putting the substrate into a reaction cavity base, heating to 1140 to 1160 ℃, baking for 1 to 3 min in an epitaxial furnace reaction cavity, and then cooling to 1110 to 1130 ℃.
And S4, purging the internal environment of the reaction chamber of the epitaxial furnace by using hydrogen, wherein the hydrogen flow is set to be 60 to 70L/min, and the purging time is 50 to 70 seconds.
S5, setting the flow of hydrogen to be 50-70L/min, and allowing trichlorosilane gas wrapped by a bubbler to enter a reaction chamber together, wherein the flow of trichlorosilane is set to be 5-20L/min; and introducing hydrogen into the lower part of the base, wherein the hydrogen flow is set to be 14 to 18L/min.
S6, two layers of intrinsic materials grow on the substrate successively, the growth time of the first layer is set to be 40-80 seconds, the growth time of the second layer is set to be 20-60 seconds, the middle interval hydrogen purging time is 3-10 min, and the rotating speed of the base is 30r/min.
S7, carrying out hydrogen-doped phosphine gas to form a mixed gas, wherein the evacuation time of a doping pipeline is 40-80 seconds, the hydrogen flow is set to be 15-20L/min, the doped phosphine gas is set to be 40-60 ppm, and the proportion of the doped phosphine gas in the mixed gas is 10-30%.
S8, setting the hydrogen flow carrying trichlorosilane to be 40-80L/min during the growth of the epitaxial layer, leading trichlorosilane gas to enter a reaction cavity together through a bubbler, setting the trichlorosilane gas flow to be 5-20L/min, setting the gas flow of a doping pipeline to be 40-60 sccm, setting the growth time to be 500-1500 seconds, and setting the rotation speed of the base to be 30r/min.
And S9, after the growth of the epitaxial layer is finished, cooling the reaction chamber to form an epitaxial wafer, and taking out the epitaxial wafer from the reaction chamber after the temperature is reduced to 300 ℃.
The invention has the beneficial effects that: on the premise of ensuring small-flow hydrogen chloride gas etching and high-temperature baking, two layers of intrinsic substances are designed and grown on the substrate in sequence, so that the nonuniformity of the epitaxial wafer resistivity is reduced to within 1% from more than 5%, and the use requirement of the product is met.
The method adopts the development of the double intrinsic layers to inhibit the self-doping effect of the substrate, and is characterized in that the double-layer structure is established to inhibit the volatilization and solid phase transfer of impurity elements in the substrate through the growth of the double intrinsic layers, so that the doping of the impurity elements is reduced, the growth environment of the subsequent epitaxial layer is more ideal, a remarkably better electrical result can be obtained, and the remarkable beneficial effect that the nonuniformity of the resistivity is lower than 1% is obtained.
In the experimental process, by carrying out comparative analysis on the single-layer intrinsic property, the double-layer intrinsic property and the three-layer intrinsic property, the control performance of the double-layer intrinsic property and the three-layer intrinsic property on the nonuniformity of the resistivity is more excellent than that of the single-layer intrinsic property, and the nonuniformity of the resistivity of the double-layer intrinsic property and that of the three-layer intrinsic property are not greatly different; meanwhile, the dual-layer intrinsic has advantages over the three-layer intrinsic in terms of economy and technical difficulty of scheme control.
Drawings
FIG. 1 is a resistivity profile of example 1 of the present invention;
FIG. 2 is a resistivity profile of example 2 of the present invention;
FIG. 3 is a resistivity profile of example 3 of the present invention;
FIG. 4 is a resistivity profile of example 4 of the present invention;
FIG. 5 is a resistivity profile of example 5 of the present invention.
Detailed Description
The following detailed description of specific embodiments of the present invention is made with reference to the accompanying drawings and examples.
The epitaxial furnace used by the invention is a northern HuaChuan 630 multi-piece epitaxial furnace. The purity of the used hydrogen chloride gas is more than or equal to 99.99 percent, and the purity of the trichlorosilane gas is more than or equal to 99.95 percent. And selecting a heavily-doped boron substrate with the diameter of 150mm, wherein the resistivity of the heavily-doped boron substrate is lower than 0.004 ohm-cm.
The resistivity index of the epitaxial wafer is tested by adopting an MCV-530 resistivity measuring instrument, a 5-point testing method is adopted, and the 5-point testing position is a central point mainly taking the upward direction and four points which are right above, below, left and right of the central point and are 6mm away from the edge. The mean value of the resistivity 5 points of the prepared silicon epitaxial layer is 27-29 omega cm.
Example 1:
(1) And (3) introducing hydrogen chloride gas into the reaction chamber of the epitaxial furnace, setting the gas flow to be 16L/min, and etching the base in the reaction chamber of the epitaxial furnace and residual deposited substances on the chamber at the high temperature of 1150 ℃ for 120 seconds.
(2) In the silicon coating process, the flow of hydrogen is set to be 70L/min, gaseous trichlorosilane is wrapped by a bubbler and enters the reaction chamber of the epitaxial furnace together, the flow of trichlorosilane is set to be 10L/min, and the silicon coating time on the base is 20 seconds.
(3) And putting the substrate into a reaction chamber base, heating to 1150 ℃, baking the reaction chamber of the epitaxial furnace for 2min, and then cooling to 1120 ℃.
(4) And (3) purging the internal environment of the reaction chamber of the epitaxial furnace by using hydrogen, wherein the hydrogen flow is set to be 65L/min, and the purging time is 60 seconds.
(5) Setting the flow of hydrogen to be 60L/min, enabling the trichlorosilane gas wrapped by the bubbler to enter the reaction chamber together, setting the flow of the trichlorosilane to be 12L/min, enabling the evacuation time of the trichlorosilane gas in the pipeline to be 40 seconds, introducing the hydrogen into the lower part of the base, and setting the flow of the hydrogen to be 16L/min.
(6) Two layers of intrinsic materials grow on the substrate in sequence, the growth time of the first layer is set to be 40 seconds, the growth time of the second layer is set to be 20 seconds, hydrogen purging is carried out for 5min at intervals, and the rotating speed of the base is 30r/min.
(7) The hydrogen is wrapped by the doped phosphane gas to form mixed gas, the mixed gas is introduced into the chamber together, the hydrogen flow is set to be 18L/min, the doped phosphane gas is set to be 50ppm, the proportion of the doped phosphane gas in the mixed gas is 15%, and the emptying time of the doped pipeline is 60 seconds.
(8) In the epitaxial layer growth, the hydrogen flow carrying trichlorosilane is set to be 60L/min, trichlorosilane gas wrapped by a bubbler enters an epitaxial furnace reaction chamber together, the trichlorosilane gas flow is set to be 10L/min, the growth time is 960 seconds, the rotation speed of a base is 30r/min, and the gas flow of a doping pipeline is 50 sccm.
(9) And after the growth of the epitaxial layer is finished, the reaction chamber begins to cool to form a silicon epitaxial wafer, and after the temperature is reduced to 300 ℃, the epitaxial wafer is taken out from the reaction chamber.
The resistivity profile of the epitaxial layer obtained in example 1 is shown in FIG. 1, and the 5-point position test values are 27.75. Omega. Cm, 27.64. Omega. Cm, 26.85. Omega. Cm, 27.76. Omega. Cm, and 27.85. Omega. Cm, respectively, and the calculated mean value is 27.57. Omega. Cm, and the unevenness is 1.48%.
Example 2:
in the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate in sequence, the growth time of the first layer is set to be 50 seconds, the growth time of the second layer is set to be 30 seconds, hydrogen purging is carried out for 5min at the interval between the first layer and the second layer, and the rotating speed of the base is 30r/min. The other steps and parameter settings are the same as in example 1, and a description thereof will not be repeated.
The resistivity profile of the silicon epitaxial layer obtained in example 2 is shown in FIG. 2, and the 5-point position test values were 27.63. Omega. Cm, 27.82. Omega. Cm, 26.95. Omega. Cm, 27.96. Omega. Cm, and 27.81. Omega. Cm, respectively, and the calculated mean value was 27.63. Omega. Cm, and the nonuniformity was 1.44%.
Example 3:
in the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate successively, the growth time of the first layer is set to be 60 seconds, the growth time of the second layer is set to be 40 seconds, hydrogen purging is carried out for 5min at intervals, and the rotating speed of the base is 30r/min. The other steps and parameter settings are the same as in example 1, and a description thereof will not be repeated.
The resistivity profile of the silicon epitaxial layer obtained in example 3 is shown in fig. 3, and the 5-point position test values were 27.46 Ω · cm,27.9 Ω · cm,26.98 Ω · cm,27.88 Ω · cm, and 27.56 Ω · cm, respectively, and the calculated mean value was 27.56 Ω · cm, and the unevenness was 1.36%.
Example 4:
in the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate in sequence, the growth time of the first layer is set to be 70 seconds, the growth time of the second layer is set to be 50 seconds, hydrogen purging is carried out for 5min at intervals, and the rotating speed of the base is 30r/min. Other steps and parameter settings are the same as those in embodiment 1, and a description thereof will not be repeated.
The resistivity profile of the silicon epitaxial layer obtained in example 4 is shown in FIG. 4, and the 5-point position test values were 27.59. Omega. Cm, 27.96. Omega. Cm, 26.99. Omega. Cm, 27.79. Omega. Cm, and 27.54. Omega. Cm, respectively, and the calculated mean value was 27.57. Omega. Cm, and the nonuniformity was 1.33%.
Example 5:
in the embodiment, in the step (6), two layers of intrinsic materials are grown on the substrate in sequence, the growth time of the first layer is set to be 80 seconds, the growth time of the second layer is set to be 60 seconds, hydrogen purging is carried out for 5min at the interval between the first layer and the second layer, and the rotating speed of the base is 30r/min. Other steps and parameter settings are the same as those in embodiment 1, and a description thereof will not be repeated.
The resistivity profile of the silicon epitaxial layer obtained in example 5 is shown in FIG. 5, and the 5-point position test values were 27.62. Omega. Cm, 27.85. Omega. Cm, 27.23. Omega. Cm, 27.73. Omega. Cm, and 27.57. Omega. Cm, respectively, and the calculated mean value was 27.6. Omega. Cm, and the nonuniformity was 0.85%.
Compared with the embodiments 1, 2, 3 and 4, the non-uniformity index of the resistivity of the silicon epitaxial layer prepared in the embodiment 5 is optimal under the corresponding process conditions. Continuing to increase the intrinsic respective growth times of the two layers does not further promote resistivity non-uniformity and is economically disadvantageous. Therefore, example 5 is the most preferred embodiment of the present invention.
Claims (4)
1. A method for reducing the autodoping of an epitaxial wafer is characterized by comprising the following steps:
s1, introducing hydrogen chloride gas into a reaction chamber of an epitaxial furnace, setting the gas flow rate to be 10-20L/min, and etching the base in the reaction chamber of the epitaxial furnace and residual deposited substances on the chamber at the high temperature of 1140-1160 ℃ for 110-130 seconds;
s2, in the silicon coating process, setting the flow of hydrogen to be 60-80L/min, wrapping gaseous trichlorosilane together through a bubbler, and allowing the gaseous trichlorosilane to enter a reaction chamber of an epitaxial furnace, setting the flow of the trichlorosilane to be 8-12L/min, and setting the silicon coating time on the base to be 10-30 seconds;
s3, putting the substrate into a reaction chamber base, heating to 1140-1160 ℃, baking the reaction chamber of the epitaxial furnace for 1-3 min, and then cooling to 1110-1130 ℃;
s4, purging the internal environment of the reaction chamber of the epitaxial furnace by using hydrogen, wherein the hydrogen flow is set to be 60 to 70L/min, and the purging time is 50 to 70 seconds;
s5, setting the flow of hydrogen to be 50-70L/min, and allowing trichlorosilane gas wrapped by a bubbler to enter a reaction chamber together, wherein the flow of trichlorosilane is set to be 5-20L/min; introducing hydrogen into the lower part of the base, wherein the hydrogen flow is set to be 14 to 18L/min;
s6, two layers of intrinsic materials grow on the substrate successively, the growth time of the first layer is set to be 40-80 seconds, the growth time of the second layer is set to be 20-60 seconds, the middle interval hydrogen purging time is 3-10 min, and the rotation speed of the base is 30 r/min;
s7, carrying doped phosphine gas by hydrogen to form a mixed gas, wherein the evacuation time of a doping pipeline is 40-80 seconds, the hydrogen flow is set to be 15-20L/min, the doped phosphine gas is set to be 40-60 ppm, and the proportion of the doped phosphine gas in the mixed gas is 10-30%;
s8, setting the hydrogen flow carrying trichlorosilane to be 40-80L/min during the growth of the epitaxial layer, leading trichlorosilane gas to enter a reaction cavity together through a bubbler, setting the trichlorosilane gas flow to be 5-20L/min, setting the gas flow of a doping pipeline to be 40-60 sccm, setting the growth time to be 500-1500 seconds, and setting the rotation speed of a base to be 30 r/min;
and S9, finishing the growth of the epitaxial layer, cooling the reaction chamber to form the epitaxial wafer, and taking out the epitaxial wafer from the reaction chamber after the temperature is reduced to 300 ℃.
2. The method for reducing the autodoping of the epitaxial wafer according to claim 1, wherein the purity of the hydrogen chloride gas is greater than or equal to 99.99%, and the purity of the trichlorosilane gas is greater than or equal to 99.95%.
3. The method for reducing the self-doping of the epitaxial wafer according to claim 1, wherein the substrate is a heavily boron-doped substrate with a diameter of 150mm, and the resistivity of the heavily boron-doped substrate is lower than 0.004 Ω -cm.
4. The method of claim 1, wherein the epitaxial furnace is a northern Huashen 630 multi-wafer epitaxial furnace.
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