CN103541001A - Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice - Google Patents
Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice Download PDFInfo
- Publication number
- CN103541001A CN103541001A CN201310527944.XA CN201310527944A CN103541001A CN 103541001 A CN103541001 A CN 103541001A CN 201310527944 A CN201310527944 A CN 201310527944A CN 103541001 A CN103541001 A CN 103541001A
- Authority
- CN
- China
- Prior art keywords
- flow
- epitaxial
- substrate
- slice
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention relates to a preparation method for improving the electrical resistivity and thickness consistency of an epitaxial slice. The preparation method comprises the following steps: 1, putting a substrate slice, raising the substrate slice into a cavity body, sequentially blowing nitrogen and hydrogen, finally completing the reaction in the following each step in a primary hydrogen environment, and raising the temperature of the cavity body; 2, substrate gaseous phase polishing: using HCL to polish the surface of a substrate; 3, variable-flow blowing: changing the flow of a main H2 gas, and gradually diluting the impurity content of the surface layer of the substrate; 4, intrinsic growing; and 5, epitaxial growing: determining the incident angle of a conical top tray of a cylindrical epitaxial furnace, filling reaction gases into the cavity body of the epitaxial furnace along the incident angle alpha of the conical top tray, which is between 0 degree and 28 degrees, thus forming uniform gas stream field distribution, cooling the cavity of an equipment furnace and removing the slice after the epitaxial growing, thus producing a silicon epitaxial slice. The silicon epitaxial slice which is prepared by adopting the method has the electrical resistivity nonuniformity being less than 2% and the thickness nonuniformity being less than 1.5%, so that the processing technology of the silicon epitaxial slice is widened.
Description
Technical field
The present invention relates to semiconductor material preparation technology, relate in particular to a kind of preparation method who improves epitaxial wafer resistivity and thick consistency.
Background technology
At present, the main method of preparing silicon epitaxial material is chemical gas phase epitaxy method (CVD), utilize the gaseous substances such as trichlorosilane, hydrogen to react under hot environment, in silicon monocrystalline substrate, form the thin-layer silicon monocrystal material with certain resistivity and thickness.In this reaction process, it is two key factors wherein that cavity temperature and gas flow rate distribute.Enter gas in cavity owing to there is temperature contrast with cavity, will certainly affect the warm field uniformity in cavity, and the gas that enters cavity also can affect the gas flow rate in cavity, certainly will cause flow field uniformity difference.And the homogeneity in cavity Nei Wenchang and flow field affects the chemical reaction intensity at each position in cavity, thus the consistence of final decision product parameters and stability.
In conventional epitaxial wafer preparation technology, the incident mode of reactant gases adopts always takes over a business the flat shape of taking over a business to be designed to of cartridge type epitaxial furnace, and its reactant gases incident angle can only be fixed as 0 °.Draw with experiment by analysis, this gas incident mode is affect epitaxial wafer parameter consistency so that affect the important factor of semiconductor device yield, and therefore, improving epitaxial wafer parameter consistency is the inexorable trend that adapts to current semiconducter device suitability for industrialized production.
Summary of the invention
The object of the invention is the problem existing according to prior art, a kind of preparation method who improves epitaxial wafer resistivity and thick consistency is provided.Present method is by changing the mode (as shown in Figure 1) of the inlet air flow angle [alpha] of cartridge type epitaxial furnace pedestal top, according to the thickness of epitaxial wafer, determine the incident angle that the taper of cartridge type epitaxial furnace is taken over a business, adjusting gas flowfield in epitaxial furnace cavity distributes, and grope optimum process condition, thereby realize the conforming object of improving epitaxial wafer resistivity and thickness.
The technical scheme that the present invention takes is: a kind of preparation method who improves epitaxial wafer resistivity and thick consistency, it is characterized in that, and described preparation method comprises the following steps:
Step 1: pack substrate slice into, rise up into cavity, carry out successively nitrogen, hydrogen purge, finally make following each step all react under hydrogen primary climate, an actor's rendering of an operatic tune body of going forward side by side heats up, intensification temperature to 1100 ~ 1200 ℃, and stable.
Step 2: substrate gas phase polishing: use HCL substrate to be carried out to surface finish, polish temperature: 1100 ~ 1200 ℃, H
2flow: 280 ~ 320L/min, HCl flow: 1 ~ 3L/min, polishing time: 4 ~ 5min.
Step 3: variable-flow purges: adopting is at 1100 ~ 1200 ℃ at cavity temperature, changes H
2main gas flow, dilute gradually underlayer surface foreign matter content, H
2gas flow is down to 50 ~ 100L/min by 280 ~ 400L/min, falls flow time: 1 ~ 4min, and low flow is held time: 1 ~ 3min, then H
2flow rises to 280 ~ 400L/min by 50 ~ 100L/min, up-flow amount time: 1 ~ 4min, and high flow capacity is held time: 1 ~ 3min.
Step 4: intrinsic growth: carry out intrinsic growth, H at substrate surface
2flow: 280 ~ 320L/min, TCS flow: 20 ~ 60Gr/min, intrinsic growth temperature: 1100 ~ 1200 ℃, intrinsic growth time: 3 ~ 5min.
Step 5: epitaxy: under condition of normal pressure, epitaxial growth temperature: 1100 ~ 1200 ℃, epitaxy time: 15 ~ 25min, H
2flow: 280 ~ 320L/min, TCS flow: 20 ~ 60Gr/min, PH
3doping flow: 20 ~ 60sccm, according to the thickness of epitaxial wafer, determine the incident angle that the taper of cartridge type epitaxial furnace is taken over a business, making incident angle that reactant gases is taken over a business in taper is to enter in epitaxial furnace cavity within the scope of 28 ° of 0 ° of ﹤ α ﹥, form uniform gas Flow Field Distribution, after epitaxy, equipment furnace chamber is lowered the temperature, is got sheet, makes silicon epitaxial wafer.
The invention has the beneficial effects as follows: the silicon epitaxial wafer that adopts present method to prepare, its resistivity ununiformity <2%, thickness offset <1.5%, thus expanded silicon epitaxial wafer Technology.
Accompanying drawing explanation
Fig. 1 adopts taper to take over a business to change gas incident angle schematic diagram in cartridge type epitaxial furnace cavity.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described: the present invention utilizes taper to take over a business, change the flow state of process gas in reaction cavity, as shown in Figure 1, the angle of inclined-plane and horizontal direction is taken over a business in angle [alpha] representative, and the direction of arrow represents the flow direction of process gas.By change, take over a business cone point angle, form different gas incident modes, grope optimum process condition, obtain high uniformity, surface-brightening, without the epitaxial wafer of slip line.
Of the present inventionly take over a business overall diameter and fix, and large along with taking over a business the change of inclined-plane angle, the height of taking over a business increases gradually, due to the restriction of furnace chamber height, take over a business maximum angle can accomplish 28 °, and in common process, incident gas angle can only be fixed as 0 °.SHAPE \* MERGEFORMAT
Embodiment 1: a kind of preparation method's step of improving epitaxial wafer resistivity and thick consistency is as follows:
Step 1: pack substrate slice into, rise up into cavity, carry out successively nitrogen, hydrogen purge, finally make following each step all react under hydrogen primary climate, an actor's rendering of an operatic tune body of going forward side by side heats up, intensification temperature to 1130 ℃, and stable.
Step 2: substrate gas phase polishing: use HCL substrate to be carried out to surface finish, polish temperature: 1130 ℃, H
2flow: 280L/min, HCl flow: 1L/min, polishing time: 4min.
Step 3: variable-flow purges: adopting is at 1130 ℃ at cavity temperature, changes H
2main gas flow, dilute gradually underlayer surface foreign matter content, H
2gas flow is down to 100L/min by 280L/min, falls flow time: 1min, and low flow is held time: 1min, then H
2flow rises to 280L/min by 100L/min, up-flow amount time: 1min, and high flow capacity is held time: 1min.
Step 4: intrinsic growth: carry out intrinsic growth at substrate surface, resistivity is longitudinally significantly raise, H
2flow: 280L/min, TCS flow: 40Gr/min, intrinsic growth temperature: 1130 ℃, intrinsic growth time: 3min.
Step 5: epitaxy: chamber pressure 0.1MPa, epitaxial growth temperature: 1130 ℃, epitaxy time: 20min, H
2flow: 280L/min, TCS flow: 40Gr/min, PH
3doping flow: 35sccm, adopts the flat shape of conventional cartridge type epitaxial furnace to take over a business, its incident angle α=0 °, and after epitaxy, equipment furnace chamber is lowered the temperature, is got sheet, makes silicon epitaxial wafer.After testing, under above processing condition, adopt the flat shape of conventional cartridge type epitaxial furnace to take over a business, its incident angle α=0 °, silicon epitaxial wafer surface-brightening, zero defect that embodiment 1 makes, its resistivity ununiformity is 1.71%, thickness offset <1.97%.
Embodiment 2: a kind of preparation method's step of improving epitaxial wafer resistivity and thick consistency is as follows:
Step 1: pack substrate slice into, rise up into cavity, carry out successively nitrogen, hydrogen purge, finally make following each step all react under hydrogen primary climate, an actor's rendering of an operatic tune body of going forward side by side heats up, intensification temperature to 1130 ℃, and stable.
Step 2: substrate gas phase polishing: use HCL substrate to be carried out to surface finish, polish temperature: 1130 ℃, H
2flow: 290L/min, HCl flow: 1L/min, polishing time: 4min.
Step 3: variable-flow purges: adopting is at 1130 ℃ at cavity temperature, changes H
2main gas flow, dilute gradually underlayer surface foreign matter content, H
2gas flow is down to 80L/min by 290L/min, falls flow time: 2min, and low flow is held time: 2min, then H
2flow rises to 290L/min by 80L/min, up-flow amount time: 2min, and high flow capacity is held time: 2min.
Step 4: intrinsic growth: carry out intrinsic growth at substrate surface, resistivity is longitudinally significantly raise, H
2flow: 290L/min, TCS flow: 40Gr/min, intrinsic growth temperature: 1130 ℃, intrinsic growth time: 3min.
Step 5: epitaxy: chamber pressure 0.1MPa, epitaxial growth temperature: 1130 ℃, epitaxy time: 20min, H
2flow: 290L/min, TCS flow: 40Gr/min, PH
3doping flow: 35sccm, adopts the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=8 °, and after epitaxy, equipment furnace chamber is lowered the temperature, is got sheet, makes silicon epitaxial wafer.
After testing, under above processing condition, adopt the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=8 °, silicon epitaxial wafer surface-brightening, zero defect that embodiment 2 makes, its resistivity ununiformity is 1.71%, thickness offset <1.43%.
Embodiment 3: a kind of preparation method's step of improving epitaxial wafer resistivity and thick consistency is as follows:
Step 1: pack substrate slice into, rise up into cavity, carry out successively nitrogen, hydrogen purge, finally make following each step all react under hydrogen primary climate, an actor's rendering of an operatic tune body of going forward side by side heats up, intensification temperature to 1150 ℃, and stable.
Step 2: substrate gas phase polishing: use HCL substrate to be carried out to surface finish, polish temperature: 1150 ℃, H
2flow: 310L/min, HCl flow: 2L/min, polishing time: 4min.
Step 3: variable-flow purges: adopting is at 1150 ℃ at cavity temperature, changes H
2main gas flow, dilute gradually underlayer surface foreign matter content, H
2gas flow is down to 60L/min by 310L/min, falls flow time: 3min, and low flow is held time: 3min, then H
2flow rises to 310L/min by 60L/min, up-flow amount time: 3min, and high flow capacity is held time: 3min.
Step 4: intrinsic growth: carry out intrinsic growth at substrate surface, resistivity is longitudinally significantly raise, H
2flow: 310L/min, TCS flow: 40Gr/min, intrinsic growth temperature: 1150 ℃, intrinsic growth time: 3min.
Step 5: epitaxy: chamber pressure 0.1MPa, epitaxial growth temperature: 1150 ℃, epitaxy time: 20min, H
2flow: 310L/min, TCS flow: 40Gr/min, PH
3doping flow: 35sccm, adopts the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=18 °, and after epitaxy, equipment furnace chamber is lowered the temperature, is got sheet, makes silicon epitaxial wafer.
After testing, under above processing condition, adopt the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=18 °, silicon epitaxial wafer surface-brightening, zero defect that embodiment 3 makes, its resistivity ununiformity is 1.10%, thickness offset <0.67%.
Embodiment 4: a kind of preparation method's step of improving epitaxial wafer resistivity and thick consistency is as follows:
Step 1: pack substrate slice into, rise up into cavity, carry out successively nitrogen, hydrogen purge, finally make following each step all react under hydrogen primary climate, an actor's rendering of an operatic tune body of going forward side by side heats up, intensification temperature to 1150 ℃, and stable.
Step 2: substrate gas phase polishing: use HCL substrate to be carried out to surface finish, polish temperature: 1150 ℃, H
2flow: 320L/min, HCl flow: 3L/min, polishing time: 4min.
Step 3: variable-flow purges: adopting is at 1150 ℃ at cavity temperature, changes H
2main gas flow, dilute gradually underlayer surface foreign matter content, H
2gas flow is down to 50L/min by 320L/min, falls flow time: 3min, and low flow is held time: 3min, then H
2flow rises to 320L/min by 50L/min, up-flow amount time: 3min, and high flow capacity is held time: 3min.
Step 4: intrinsic growth: carry out intrinsic growth at substrate surface, resistivity is longitudinally significantly raise, H
2flow: 320L/min, TCS flow: 40Gr/min, intrinsic growth temperature: 1150 ℃, intrinsic growth time: 3min.
Step 5: epitaxy: chamber pressure 0.1MPa, epitaxial growth temperature: 1150 ℃, epitaxy time: 20min, H
2flow: 320L/min, TCS flow: 40Gr/min, PH
3doping flow: 35sccm, adopts the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=28 °, and after epitaxy, equipment furnace chamber is lowered the temperature, is got sheet, makes silicon epitaxial wafer.
After testing, under above processing condition, adopt the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=28 °, silicon epitaxial wafer surface-brightening, zero defect that embodiment 4 makes, its resistivity ununiformity is 1.35%, thickness offset <0.96%.
The present invention is applicable to the production of 45V, 60V, 100V schottky device use silicon epitaxial wafer, the specification that above embodiment adopts is 45V schottky device epitaxial wafer, and the ununiformity of products made thereby resistivity and thickness is as the standard of weighing processing method good level.For realizing better Product Level, require the ununiformity of epitaxial material low as much as possible.
Above four embodiment, data to the ununiformity of the epitaxial wafer resistivity after after testing and thickness contrast and can draw: embodiment 1 adopts the flat shape of conventional cartridge type epitaxial furnace to take over a business, its incident angle α=0 °, prepared silicon epitaxial wafer, its resistivity ununiformity is 1.71%, thickness offset <1.97%, under its corresponding processing condition, the ununiformity of embodiment 1 prepared epitaxial wafer is relatively high.And embodiment 3 adopts the taper of cartridge type epitaxial furnace to take over a business, its incident angle α=18 °, prepared silicon epitaxial wafer, its resistivity ununiformity is 1.10%, thickness offset <0.67%, with embodiment 1, embodiment 2 with implement 4 and compare, under its corresponding processing condition, the ununiformity of embodiment 3 prepared epitaxial wafers is relatively low, i.e. made epitaxial wafer electrical parameter, geometric parameter optimum.Therefore, embodiment 3 is most preferred embodiment of the present invention.
Claims (1)
1. a preparation method who improves epitaxial wafer resistivity and thick consistency, is characterized in that, described preparation method comprises the following steps:
Step 1: pack substrate slice into, rise up into cavity, carry out successively nitrogen, hydrogen purge, finally make following each step all react under hydrogen primary climate, an actor's rendering of an operatic tune body of going forward side by side heats up, intensification temperature to 1100 ~ 1200 ℃, and stable;
Step 2: substrate gas phase polishing: use HCL substrate to be carried out to surface finish, polish temperature: 1100 ~ 1200 ℃, H
2flow: 280 ~ 320L/min, HCl flow: 1 ~ 3L/min, polishing time: 4 ~ 5min;
Step 3: variable-flow purges: adopting is at 1100 ~ 1200 ℃ at cavity temperature, changes H
2main gas flow, dilute gradually underlayer surface foreign matter content, H
2gas flow is down to 50 ~ 100L/min by 280 ~ 400L/min, falls flow time: 1 ~ 4min, and low flow is held time: 1 ~ 3min, then H
2flow rises to 280 ~ 400L/min by 50 ~ 100L/min, up-flow amount time: 1 ~ 4min, and high flow capacity is held time: 1 ~ 3min;
Step 4: intrinsic growth: carry out intrinsic growth, H at substrate surface
2flow: 280 ~ 320L/min, TCS flow: 20 ~ 60Gr/min, intrinsic growth temperature: 1100 ~ 1200 ℃, intrinsic growth time: 3 ~ 5min;
Step 5: epitaxy: under condition of normal pressure, epitaxial growth temperature: 1100 ~ 1200 ℃, epitaxy time: 15 ~ 25min, H
2flow: 280 ~ 320L/min, TCS flow: 20 ~ 60Gr/min, PH
3doping flow: 20 ~ 60sccm, according to the thickness of epitaxial wafer, determine the incident angle that the taper of cartridge type epitaxial furnace is taken over a business, making incident angle that reactant gases is taken over a business in taper is to enter in epitaxial furnace cavity within the scope of 28 ° of 0 ° of ﹤ α ﹥, form uniform gas Flow Field Distribution, after epitaxy, equipment furnace chamber is lowered the temperature, is got sheet, makes silicon epitaxial wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310527944.XA CN103541001A (en) | 2013-10-31 | 2013-10-31 | Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310527944.XA CN103541001A (en) | 2013-10-31 | 2013-10-31 | Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103541001A true CN103541001A (en) | 2014-01-29 |
Family
ID=49964830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310527944.XA Pending CN103541001A (en) | 2013-10-31 | 2013-10-31 | Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103541001A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269354A (en) * | 2014-10-23 | 2015-01-07 | 中国电子科技集团公司第四十六研究所 | Method for improving thickness homogeneity of silicon extending slices for CCD device |
| CN104282535A (en) * | 2014-10-23 | 2015-01-14 | 中国电子科技集团公司第四十六研究所 | Method for improving electrical resistivity evenness of P-type silicon epitaxial wafer for CCD |
| CN104319235A (en) * | 2014-10-23 | 2015-01-28 | 中国电子科技集团公司第四十六研究所 | Manufacture method of silicon epitaxial slice for fast recovery diode |
| CN104947183A (en) * | 2015-05-29 | 2015-09-30 | 中国电子科技集团公司第四十六研究所 | Production method of heavily phosphorus-doped thin substrate silicon epitaxial layer for Schottky devices |
| CN105489478A (en) * | 2015-12-09 | 2016-04-13 | 河北普兴电子科技股份有限公司 | Regulation control method for thin layer epitaxial transition region of heavily doped PH substrate |
| CN106757324A (en) * | 2016-12-26 | 2017-05-31 | 南京国盛电子有限公司 | A kind of manufacture method of silicon epitaxial wafer |
| CN106876246A (en) * | 2017-02-14 | 2017-06-20 | 河北普兴电子科技股份有限公司 | The method for improving resistivity evenness in epitaxial wafer piece |
| CN107012506A (en) * | 2017-04-18 | 2017-08-04 | 中国电子科技集团公司第四十六研究所 | A kind of preparation method of step-recovery diode silicon epitaxial wafer |
| CN107099840A (en) * | 2017-04-18 | 2017-08-29 | 中国电子科技集团公司第四十六研究所 | A kind of preparation method of transient voltage suppressor silicon epitaxial wafer |
| CN115029773A (en) * | 2022-05-23 | 2022-09-09 | 中环领先半导体材料有限公司 | Process for improving thick epitaxial particles |
| CN115537922A (en) * | 2022-11-29 | 2022-12-30 | 中国电子科技集团公司第四十六研究所 | Method for reducing self-doping of epitaxial wafer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02267191A (en) * | 1989-04-10 | 1990-10-31 | Furukawa Electric Co Ltd:The | Apparatus for vapor growth |
| CN103337506A (en) * | 2013-06-17 | 2013-10-02 | 中国电子科技集团公司第四十六研究所 | Preparation technology of silicon epitaxial wafer for CCD device |
-
2013
- 2013-10-31 CN CN201310527944.XA patent/CN103541001A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02267191A (en) * | 1989-04-10 | 1990-10-31 | Furukawa Electric Co Ltd:The | Apparatus for vapor growth |
| CN103337506A (en) * | 2013-06-17 | 2013-10-02 | 中国电子科技集团公司第四十六研究所 | Preparation technology of silicon epitaxial wafer for CCD device |
Non-Patent Citations (1)
| Title |
|---|
| 殷海丰等: "高阻外延层电阻率均匀性控制技术分析", 《甘肃科技》, vol. 28, no. 14, 31 July 2012 (2012-07-31) * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319235B (en) * | 2014-10-23 | 2017-07-07 | 中国电子科技集团公司第四十六研究所 | A kind of manufacture method of fast recovery diode silicon epitaxial wafer |
| CN104282535A (en) * | 2014-10-23 | 2015-01-14 | 中国电子科技集团公司第四十六研究所 | Method for improving electrical resistivity evenness of P-type silicon epitaxial wafer for CCD |
| CN104319235A (en) * | 2014-10-23 | 2015-01-28 | 中国电子科技集团公司第四十六研究所 | Manufacture method of silicon epitaxial slice for fast recovery diode |
| CN104269354A (en) * | 2014-10-23 | 2015-01-07 | 中国电子科技集团公司第四十六研究所 | Method for improving thickness homogeneity of silicon extending slices for CCD device |
| CN104947183A (en) * | 2015-05-29 | 2015-09-30 | 中国电子科技集团公司第四十六研究所 | Production method of heavily phosphorus-doped thin substrate silicon epitaxial layer for Schottky devices |
| CN105489478A (en) * | 2015-12-09 | 2016-04-13 | 河北普兴电子科技股份有限公司 | Regulation control method for thin layer epitaxial transition region of heavily doped PH substrate |
| CN105489478B (en) * | 2015-12-09 | 2018-01-09 | 河北普兴电子科技股份有限公司 | The regulation and control method of heavily doped phosphorus Substrate lamina extension transition region |
| CN106757324B (en) * | 2016-12-26 | 2019-05-21 | 南京国盛电子有限公司 | A kind of manufacturing method of silicon epitaxial wafer |
| WO2018120731A1 (en) * | 2016-12-26 | 2018-07-05 | 南京国盛电子有限公司 | Manufacturing method for silicon epitaxial wafer |
| CN106757324A (en) * | 2016-12-26 | 2017-05-31 | 南京国盛电子有限公司 | A kind of manufacture method of silicon epitaxial wafer |
| CN106876246A (en) * | 2017-02-14 | 2017-06-20 | 河北普兴电子科技股份有限公司 | The method for improving resistivity evenness in epitaxial wafer piece |
| CN107012506A (en) * | 2017-04-18 | 2017-08-04 | 中国电子科技集团公司第四十六研究所 | A kind of preparation method of step-recovery diode silicon epitaxial wafer |
| CN107099840A (en) * | 2017-04-18 | 2017-08-29 | 中国电子科技集团公司第四十六研究所 | A kind of preparation method of transient voltage suppressor silicon epitaxial wafer |
| CN107012506B (en) * | 2017-04-18 | 2019-05-24 | 中国电子科技集团公司第四十六研究所 | A kind of preparation method of step-recovery diode silicon epitaxial wafer |
| CN115029773A (en) * | 2022-05-23 | 2022-09-09 | 中环领先半导体材料有限公司 | Process for improving thick epitaxial particles |
| CN115537922A (en) * | 2022-11-29 | 2022-12-30 | 中国电子科技集团公司第四十六研究所 | Method for reducing self-doping of epitaxial wafer |
| CN115537922B (en) * | 2022-11-29 | 2024-01-09 | 中国电子科技集团公司第四十六研究所 | Method for reducing self-doping of epitaxial wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103541001A (en) | Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice | |
| CN103370454B (en) | Epitaxial silicon carbide single crystal substrate and manufacture method thereof | |
| CN104947183B (en) | A kind of preparation method of schottky device silicon epitaxy layer on heavily doped thin phosphorus substrate | |
| CN107068539B (en) | The method for reducing silicon carbide epitaxy base plane dislocation density | |
| CN106757324B (en) | A kind of manufacturing method of silicon epitaxial wafer | |
| CN102844474A (en) | Epitaxial silicon carbide single-crystal substrate and method for producing the same | |
| CN103715069B (en) | A kind of reduce the method for defect in silicon carbide epitaxial film | |
| CN103228827A (en) | Method for producing epitaxial silicon carbide single crystal substrate | |
| CN104319235B (en) | A kind of manufacture method of fast recovery diode silicon epitaxial wafer | |
| CN102157359B (en) | Method for manufacturing 6-inch POWERMOS transistor epitaxial layer | |
| WO2009061599A1 (en) | Methods of selectively depositing silicon-containing films | |
| CN103337506B (en) | A kind of preparation technology of silicon epitaxial wafer for CCD device | |
| US10450672B2 (en) | Method for producing epitaxial silicon carbide wafers | |
| CN106783540A (en) | The method for reducing epitaxial wafer surface scratch | |
| CN106910673B (en) | A kind of epitaxy method reducing SiC epitaxial wafer surface triangles defect | |
| CN103603048B (en) | A kind of chemical vapor depsotition equipment for producing silicon carbide epitaxial wafer | |
| CN100485873C (en) | Control method for epitaxial layer transition zone on re-mixed arsenic underlay | |
| JP5786759B2 (en) | Method for manufacturing epitaxial silicon carbide wafer | |
| JP6245416B1 (en) | Method for manufacturing silicon carbide epitaxial wafer and method for manufacturing silicon carbide semiconductor device | |
| CN102456551A (en) | Epitaxial growth method | |
| CN104465721B (en) | A kind of silicon carbide epitaxy material and preparation method thereof | |
| CN103996608B (en) | The method improving epilayer resistance rate uniformity | |
| CN105671631B (en) | Method for cleaning back surface of 200mm-300mm epitaxial equipment base in situ | |
| CN105489478B (en) | The regulation and control method of heavily doped phosphorus Substrate lamina extension transition region | |
| CN102851735B (en) | Chemical vapor deposition growing epitaxial silicon method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140129 |