CN100485873C - Control method for epitaxial layer transition zone on re-mixed arsenic underlay - Google Patents
Control method for epitaxial layer transition zone on re-mixed arsenic underlay Download PDFInfo
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- CN100485873C CN100485873C CNB2007100616846A CN200710061684A CN100485873C CN 100485873 C CN100485873 C CN 100485873C CN B2007100616846 A CNB2007100616846 A CN B2007100616846A CN 200710061684 A CN200710061684 A CN 200710061684A CN 100485873 C CN100485873 C CN 100485873C
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Abstract
The invention discloses a control method for an external extension transition section on a heavy doping arsenic underlay, which adopts chemical vapor deposition technology to grow light doping thin silicon extension layer at two times on a n-type heavy doping arsenic silicon underlay. After the growing of a first own extension layer, reduce the temperature to 870 to 930 DEG C. and take it out. During the process, remove the memory effect by putting in a HCI erosion base. After the completion of erosion, place the piece in furnace under the temperature of 870 to 930 DEG C. and then grow the residual extension layer. By checking and comparing the extension layer made with ordinary method and the method in the invention via an extension resistance analyzer, it is proved that the extension layer made of the method in the invention has steepy transition section and resistance of the extension layer has excellent evenness.
Description
Technical field
The present invention relates to a kind of manufacturing technology of silicon epitaxial wafer, refer in particular to a kind of control method of epitaxial layer transition zone on re-mixed arsenic underlay.
Background technology
Present heavily doped arsenic substrate silicon epitaxy technology is used more and more widely in the manufacturing of electronic device, and its range of application relates to aspects such as Schottky diode, triode, VDMOS, variable capacitance diode, automotive electronics, IGBT.Electronic devices and components producer all needs the consistency of heavily doped arsenic substrate silicon epitaxial wafer and the transition region of epitaxial loayer are carried out strictness control in order to improve die yield.
In chemical vapor deposition processes, inevitably have impurity and occur, the precipitous degree of Impurity Distribution in the transition region between epitaxial wafer and the substrate can influence the quality and the electrical quantity of epitaxial wafer.It is very difficult making the interior precipitous thin epitaxy layer of impurity concentration gradient of transition region, and the method for making the precipitous transition region of Impurity Distribution gradient is constantly pursued by each producer.In the actual process production process, not only will be according to the designing requirement of electric elements, accurately control is because the influence to the epitaxial loayer electrical quantity is stain in the system that the calandria of heating furnace etc. cause, but also to manage to reduce autodoping in the epitaxial deposition process, promptly reduce the impurity content of transition region, control profile of impurities gradient.
At present, the silicon epitaxy process of the heavily doped arsenic substrate that extension producer is ripe is the technology that is called as " two step epitaxys "." two step epitaxy " grow earlier one deck intrinsic epitaxial loayer on heavily doped arsenic substrate, the hydrogen that feeds big flow then in stove is caught up with gas, catch up with the epitaxial loayer of regrowth remainder behind the gas, up to meeting the requirements of thickness.Its basic step is as follows:
With the substrate shove charge, be warming up to 1000～1200 ℃, feed hydrogen chloride polishing then
This step is at high temperature to corrode substrate with HCl, and substrate is played polishing action, and is of value to the improvement of the lattice structure of the epitaxial loayer that is about to growth.
2. with big flow H
2Flushing
In heating furnace, feed big flow hydrogen, thereby substrate and bell jar are washed, catch up with gas, the impurity that is adsorbed on wafer, base-plates surface and is trapped in the boundary-layer is taken away by primary air.
3. growth regulation one deck intrinsic epitaxial loayer
Utilize chemical vapour deposition technique growth regulation one deck intrinsic epitaxial loayer on substrate.Ground floor intrinsic epitaxial loayer plays sealing process to wafer surface, stops the further outwards volatilization of impurity in the substrate.The thickness of general intrinsic epitaxial loayer can be determined according to the requirement of epilayer resistance rate.
4 for the second time big flow H
2Flushing
In stove, feed the hydrogen of big flow once more, the intrinsic epitaxial loayer on bell jar, pedestal, substrate and the substrate is washed, catches up with gas, the impurity that is adsorbed on wafer, base-plates surface and is trapped in the epitaxial loayer boundary-layer is further taken away by primary air.
5 carry out the growth of second stage, reach requirement up to the thickness of epitaxial loayer.
The shortcoming and the deficiency of existing " two step epitaxys " technology are:
At first, though the corrosion of the HCl under the high temperature can be polished substrate, and it is useful to improving lattice structure, but it also will produce some accessory substances when also having weak point: HCl polishing, and the surface of substrate is peeled a layer from when at high temperature polishing, so the impurity in these accessory substances and the substrate is understood in some atmosphere that enters vapour deposition, thereby the intrinsic epitaxial loayer that influences first step generation is the impurity content of transition zone.
Next, the risk that occurs the high resistance interlayer in the intrinsic epitaxial loayer of first step growth is bigger.As dopant in growth in the heavily doped arsenic substrate can be difficult to it is controlled, thereby very likely make the intrinsic epitaxial loayer resistive formation occur to outdiffusion.
In addition, though the uniformity of the raising epitaxial loayer that this technology can be bigger, by test, its resistivity evenness preferably also can only reach 4%, can't further improve again; This result may reach hardly for the extension that requires the thin layer high resistant, the controllability extreme difference of its resistivity evenness.
The 4th, this method is for preventing that vertical autodoping is effective, for the horizontal autodoping DeGrain then that prevents on the interface.
Conventional silicon epitaxy process, transition region is very long, seek out very difficulty of precipitous transition region.For inhibition of self-doped, obtain the resistivity evenness that precipitous transition region is become reconciled, can adopt following certain methods in the general technology, gas time, pedestal bag silicon etc. are caught up with in intrinsic epitaxial loayer, the prolongation of carry on the back as use and seal substrate, reduce growth temperature, growth is thicker.
Said method has certain effect to the steepness of control epitaxial loayer, but it is thinner for epitaxy layer thickness, or the epilayer resistance rate is higher, or the extremely low extension of resistance substrate rate, above method all is difficult to obtain ideal results, and along with the increase of intrinsic epitaxy layer thickness, the forward conduction resistance of device also can increase, and forward characteristic degenerates; And pedestal bag silicon tends to influence the roughness and the evenness at the epitaxial wafer back side, edge, causes the edge to be difficult to pass through step photo-etching machine.
Summary of the invention
Even the technical issues that need to address of the present invention provide a kind of precipitous transition region and good resistivity evenness silicon epitaxy method of also can obtaining on the extension of thin layer high resistant.
The present invention is achieved in that
It is based on two step epitaxy technologies, and it comprises silicon substrate shove charge, intensification, feeding HCl polishing, feeds big flow H
2Flushing, feeding trichlorosilane form silicon chip with chemical vapor process growth one deck intrinsic epitaxial loayer, take following measure and step simultaneously:
A reduces to 870-930 ℃ of blow-on and takes out silicon chip after the ground floor intrinsic of having grown;
B takes out during the silicon chip, corrodes pedestal with HCl;
After C etches, in the time of 870-930 ℃, again this silicon chip shove charge;
The D remaining epitaxial loayer that regrows is up to meeting the requirements of thickness.
Concrete process conditions of the present invention are:
A master H
2Flow: 20～200SLM,
The optimum temperature of b HCl corrosion is 1130～1190 ℃,
The c suitable temperature of growing for the first time: 1050～1190 ℃,
D is growth temperature for the second time: 1130～1170 ℃,
E trichlorosilane optimum flow is: 3～20g/min,
Etching time between twice extension of f is 15～120 seconds,
Corrosion temperature between twice extension of g is: 1130～1190 ℃.
The technological progress that the present invention obtains is:
Behind the ground floor intrinsic epitaxial loayer of having grown, silicon chip is taken out in stove, and pedestal and bell jar are corroded with HCl, so just removed the memory effect of substrate, and the impurity in the stove has been cleaned out, the interior impurity content of stove is reduced greatly.Even such method is produced the epitaxial wafer of thin layer high resistant, also can obtain precipitous transition region and good resistivity evenness.
Adopt twice epitaxial growth method of the present invention that impurity content in the transition region is reduced, the resistivity gradient of transition region is increased, can access precipitous transition region.The uniformity of the resistivity of epitaxial loayer generally can reach below 1%, is far superior to two conventional step extensions; Even for requiring the thin layer high resistant, its resistivity evenness is also fine.
Because impurity content reduces greatly, so the danger that occurs the high resistance interlayer between substrate and the epitaxial loayer reduces greatly.Method of the present invention not only can prevent vertical autodoping simultaneously, but also has prevented the generation of horizontal autodoping.
Method of the present invention, is suitable for producing in enormous quantities so production efficiency is low unlike conventional epitaxy method because catch up with the gas time to be used to corrode pedestal conventional epitaxially grown.
Description of drawings
Fig. 1 is the schematic diagram that calculates the method for transition zone steepness;
Fig. 2 is the vertical distributed resistance figure of epitaxial wafer that utilizes conventional " two step epitaxys " to obtain;
Fig. 3 is the vertical distributed resistance figure of epitaxial wafer that utilizes method of the present invention to obtain;
Fig. 4 is that the intrinsic thickness that makes with common process " two step epitaxys " is the vertical distributed resistance figure of epitaxial wafer of 1.5um.
Embodiment
Below in conjunction with the specific embodiment of the present invention the present invention is described in further details:
In an embodiment of the present invention, the measurement computational methods of transition region are: behind the sample angle lap, utilize the spreading resistance analyzer, measure vertical distribution curve of its epitaxy layer thickness and resistivity concentration, adopt the intersection tangent method then, obtain transition region thickness, specific algorithm as shown in Figure 1.
In the present embodiment, method shown in the present and conventional " two step epitaxys " are contrasted.In twice epitaxy method of the present invention, the concrete growth conditions of silicon epitaxy is:
A master H
2Flow: 100SLM.
It is 870 ℃ that the B dress is got the sheet temperature,
C hydrogen bake temperature is 1160 ℃,
D ground floor (inferior) growth temperature: 1170 ℃,
The E second layer (inferior) growth temperature: 1160 ℃,
F TCS (trichlorosilane) flow is: 10g/min,
Etching time between twice extension of G is 20 seconds,
Corrosion temperature between twice extension of H is: 1180 ℃.
Be the result of the test of present embodiment below:
Table 1 is the test comparison result of resistivity evenness.Measured resistivity position in the table 1 on the epitaxial wafer of " upper, middle and lower, left and right " expression, the test position of data is that the unit of data is 0hm.cm in the table at 10mm place, distance sample edge.Its uniformity represents with percentage, percentage be maximum resistivity on the same sample and minimum resistance rate variance with and ratio.
Data by table 1 contrast as can be seen, and the resistivity evenness of " twice epitaxy " of the present invention gained is better than conventional method far away.
Table 1
Fig. 2 is the vertical distribution map of resistivity that utilizes the silicon epitaxial wafer that conventional " two step epitaxial growth methods " make, and the intrinsic layer thickness of silicon epitaxial wafer is 2.6 microns, can be seen by Fig. 2, tangible high resistance interlayer is arranged in its silicon epitaxial wafer, and transition region is longer.
Fig. 4 also is the resistivity distribution figure that utilizes the silicon epitaxial wafer that conventional " two step epitaxial growth methods " make, and the intrinsic layer thickness of silicon epitaxial wafer is 1.5 microns.By seeing among Fig. 4, very long, transition region is slowly arranged in the silicon epitaxial wafer.
Fig. 3 is the resistivity distribution figure of the silicon epitaxial wafer that makes of " twice " of the present invention epitaxy, and it is through twice extension, and intrinsic grown layer thickness is 1um.Comparison diagram 2,4 and Fig. 3 as can be known, the steepness of the transition zone of Fig. 3 is obviously greater than Fig. 2,4, and the high resistant interlayer does not appear in method of the present invention.
From above result as can be known, adopt two conventional step epitaxial growths, resistivity evenness and transition region are difficult to be well controlled, and adopt twice epitaxial growth both can obtain precipitous transition region, resistivity evenness also is better than two conventional step extensions, because catch up with the gas time to be used to corrode pedestal,, be suitable for producing in enormous quantities so efficient is low unlike conventional extension conventional epitaxially grown.
Claims (2)
1, the control method of epitaxial layer transition zone on re-mixed arsenic underlay, it comprises that substrate shove charge, intensification, the polishing of feeding hydrogen chloride, the big flow hydrogen of feeding are washed, feed trichlorosilane grows one deck intrinsic epitaxial loayer with chemical gaseous phase depositing process on substrate, form silicon chip, it is characterized in that, also comprise following measure and step:
A reduces to 870-930 ℃ of blow-on and takes out silicon chip behind one deck intrinsic epitaxial loayer of having grown;
B takes out during the silicon chip, feeds the hydrogen-chloride etching pedestal in stove;
After C etches, in the time of 870-930 ℃, again this silicon chip shove charge;
D uses the chemical gaseous phase depositing process grown epitaxial layer once more, meets the requirements of thickness up to epitaxial loayer.
2, the control method of epitaxial layer transition zone on re-mixed arsenic underlay according to claim 1 is characterized in that technological parameter also comprises following parameter area:
A is growth temperature for the second time: 1130～1170 ℃,
Etching time between twice extension of b is 15～120 seconds,
Corrosion temperature between twice extension of c is: 1130～1190 ℃.
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| CN102420111A (en) * | 2011-09-15 | 2012-04-18 | 上海晶盟硅材料有限公司 | Method for improving resistivity uniformity of epitaxial layer, epitaxial wafer and semiconductor device |
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| CN102386067B (en) * | 2010-08-31 | 2013-12-18 | 中国科学院上海微系统与信息技术研究所 | Epitaxial growth method for effectively restraining self-doping effect |
| CN102538732A (en) * | 2012-01-17 | 2012-07-04 | 河北普兴电子科技股份有限公司 | Non-destructive testing method for transition zone of silicon epitaxial layer |
| CN104711675B (en) * | 2015-02-16 | 2017-11-10 | 浙江金瑞泓科技股份有限公司 | The N-type adulterating vertical pulling silicon monocrystalline and its silicon epitaxial wafer of phosphorus arsenic antimony codope |
| CN109920877A (en) * | 2019-01-30 | 2019-06-21 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | The preparation method for dividing furnace extension type silicon substrate to stop impurity band terahertz detector |
| CN113322513A (en) * | 2021-08-03 | 2021-08-31 | 南京国盛电子有限公司 | Method for growing thin-layer high-resistance silicon epitaxial wafer and epitaxial wafer prepared by same |
| CN115506010A (en) * | 2022-10-11 | 2022-12-23 | 中环领先半导体材料有限公司 | Process method for improving depth of epitaxial edge flat area of ultra-heavily doped Ph substrate |
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| CN102420111A (en) * | 2011-09-15 | 2012-04-18 | 上海晶盟硅材料有限公司 | Method for improving resistivity uniformity of epitaxial layer, epitaxial wafer and semiconductor device |
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